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use timer

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This commit is contained in:
wmano
2025-08-23 11:54:16 +08:00
parent 975f8b4930
commit 45965db185
18 changed files with 591 additions and 7266 deletions
Download Patch File Download Diff File Expand all files Collapse all files
apps/chrg/.config
+5 -4
View File
@@ -1485,10 +1485,10 @@ CONFIG_BSP_USING_UART2=y
CONFIG_BSP_USING_UART3=y CONFIG_BSP_USING_UART3=y
# CONFIG_BSP_UART3_RX_USING_DMA is not set # CONFIG_BSP_UART3_RX_USING_DMA is not set
# CONFIG_BSP_UART3_TX_USING_DMA is not set # CONFIG_BSP_UART3_TX_USING_DMA is not set
CONFIG_BSP_USING_UART4=y # CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_UART4_RX_USING_DMA is not set CONFIG_BSP_USING_UART5=y
# CONFIG_BSP_UART4_TX_USING_DMA is not set # CONFIG_BSP_UART5_RX_USING_DMA is not set
# CONFIG_BSP_USING_UART5 is not set # CONFIG_BSP_UART5_TX_USING_DMA is not set
CONFIG_BSP_USING_UART6=y CONFIG_BSP_USING_UART6=y
# CONFIG_BSP_UART6_RX_USING_DMA is not set # CONFIG_BSP_UART6_RX_USING_DMA is not set
# CONFIG_BSP_UART6_TX_USING_DMA is not set # CONFIG_BSP_UART6_TX_USING_DMA is not set
@@ -1497,6 +1497,7 @@ CONFIG_BSP_USING_I2C1=y
CONFIG_BSP_USING_I2C2=y CONFIG_BSP_USING_I2C2=y
CONFIG_BSP_USING_I2C3=y CONFIG_BSP_USING_I2C3=y
CONFIG_BSP_USING_I2C4=y CONFIG_BSP_USING_I2C4=y
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_RNG is not set # CONFIG_BSP_USING_RNG is not set
# CONFIG_BSP_USING_UDID is not set # CONFIG_BSP_USING_UDID is not set
# end of On-chip Peripheral Drivers # end of On-chip Peripheral Drivers
apps/chrg/applications/led_show.c
-11
View File
@@ -1,11 +0,0 @@
#include "led_show.h"
void led_init (void)
{
rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
}
apps/chrg/applications/led_show.h
-13
View File
@@ -1,13 +0,0 @@
#ifndef __LED_H__
#define __LED_H__
#include "drv_gpio.h"
#define LED0_PIN GET_PIN(A, 8) // GET_PIN(C, 13)
#define LED1_PIN GET_PIN(C, 14)
#define LED2_PIN GET_PIN(C, 15)
extern void led_init (void);
#endif
apps/chrg/applications/main.c
+1 -9
View File
@@ -7,8 +7,6 @@
#include <rtdevice.h> #include <rtdevice.h>
#endif /* RT_USING_NANO */ #endif /* RT_USING_NANO */
#include "led_show.h"
void show_app_version (void) void show_app_version (void)
{ {
rt_kprintf("\r\n\r\n================================================\r\n"); rt_kprintf("\r\n\r\n================================================\r\n");
@@ -26,13 +24,7 @@ int main(void)
finsh_set_prompt("chrg "); finsh_set_prompt("chrg ");
#endif #endif
led_init(); while (1) {
while (1)
{
rt_pin_write(LED0_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED0_PIN, PIN_LOW);
rt_thread_mdelay(500); rt_thread_mdelay(500);
} }
} }
apps/chrg/applications/tmr_clk.c
+48
View File
@@ -0,0 +1,48 @@
#include <stdio.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "tmr_clk.h"
struct tmr_clk_t tmrclk = {
.cnt = 0,
};
static void tmr_clk_callback (void *args)
{
struct tmr_clk_t *pCLK = (struct tmr_clk_t *)args;
pCLK->cnt++;
if (pCLK->cnt % 60 == 0) {
rt_kprintf("R : %d mins\r\n", pCLK->cnt/60);
}
//rt_kprintf("\r\n");
}
static int tmr_clk_init (void)
{
rt_err_t ret = RT_EOK;
rt_timer_t timer_fd;
timer_fd = rt_timer_create("tmr_clk", tmr_clk_callback,
&tmrclk, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
if (timer_fd == RT_NULL) {
//LOG_E("create tmr_clk");
return -1;
} else {
ret = rt_timer_start(timer_fd);
if (ret != RT_EOK) {
//LOG_E("start tmr_clk");
return ret;
}
}
return RT_EOK;
}
INIT_APP_EXPORT(tmr_clk_init);
apps/chrg/applications/tmr_clk.h
+14
View File
@@ -0,0 +1,14 @@
#ifndef __TMR_CLK_H__
#define __TMR_CLK_H__
struct tmr_clk_t {
rt_uint32_t cnt;
};
extern struct tmr_clk_t tmrclk;
#endif
apps/chrg/applications/tmr_pin.c
+245
View File
@@ -0,0 +1,245 @@
#include <rtthread.h>
#include "tmr_pin.h"
struct tmr_pin_t tmrpins[TOTAL_PINS] = {
[IDX_PIN_LED1] = {
.index = IDX_PIN_LED1,
.pin_name = PIN_NAME_LED1,
.pin_base = PIN_LED1,
.pin_mode = PIN_MODE_OUTPUT,
.pin_value = PIN_HIGH,
.tmr_name = TMR_NAME_LED1,
.tmr_fd = RT_NULL,
.tmr_stage = PIN_STAGE_IDLE,
.tmr_millis_on = PULSE_TIME*8,
.tmr_millis_off = PULSE_TIME*8,
.tmr_times = 1,
.tmr_cnt = 0,
}/*,
[IDX_PIN_LED2] = {
.index = IDX_PIN_LED2,
.pin_name = PIN_NAME_LED2,
.pin_base = PIN_LED2,
.pin_mode = PIN_MODE_OUTPUT,
.pin_value = PIN_HIGH,
.tmr_name = TMR_NAME_LED2,
.tmr_fd = RT_NULL,
.tmr_stage = PIN_STAGE_IDLE,
.tmr_millis_on = PULSE_TIME*8,
.tmr_millis_off = PULSE_TIME*8,
.tmr_times = 1,
.tmr_cnt = 0,
},
[IDX_PIN_LED3] = {
.index = IDX_PIN_LED3,
.pin_name = PIN_NAME_LED3,
.pin_base = PIN_LED3,
.pin_mode = PIN_MODE_OUTPUT,
.pin_value = PIN_HIGH,
.tmr_name = TMR_NAME_LED3,
.tmr_fd = RT_NULL,
.tmr_stage = PIN_STAGE_IDLE,
.tmr_millis_on = PULSE_TIME*8,
.tmr_millis_off = PULSE_TIME*8,
.tmr_times = 1,
.tmr_cnt = 0,
}*/
};
rt_int32_t tmr_pin_get (ePIN_IDX index)
{
if (index >= TOTAL_PINS) {
return -1;
}
struct tmr_pin_t *pPIN = &tmrpins[index];
pPIN->pin_value = rt_pin_read(pPIN->pin_base);
return pPIN->pin_value;
}
rt_int32_t tmr_pin_set (struct tmr_pin_t *pPIN, rt_uint8_t value)
{
pPIN->pin_value = value;
rt_pin_write(pPIN->pin_base, pPIN->pin_value);
return 0;
}
rt_int32_t tmr_pin_toggle (ePIN_IDX index)
{
if (index >= TOTAL_PINS) {
return -1;
}
struct tmr_pin_t *pPIN = &tmrpins[index];
pPIN->pin_value = !pPIN->pin_value;
rt_pin_write(pPIN->pin_base, pPIN->pin_value);
return 0;
}
static rt_int32_t tmr_pin_timer_set_on (struct tmr_pin_t *pPIN)
{
return rt_timer_control(pPIN->tmr_fd, RT_TIMER_CTRL_SET_TIME, (void *)&pPIN->tmr_millis_on);
}
static rt_int32_t tmr_pin_timer_set_off (struct tmr_pin_t *pPIN)
{
return rt_timer_control(pPIN->tmr_fd, RT_TIMER_CTRL_SET_TIME, (void *)&pPIN->tmr_millis_off);
}
rt_int32_t tmr_pin_pulsing (struct tmr_pin_t *pPIN, rt_uint8_t state)
{
rt_int32_t ret = 0;
if (state == PULSE_OFF) {
pPIN->tmr_stage = PIN_STAGE_IDLE;
tmr_pin_set(pPIN, PIN_HIGH);
} else {
if (pPIN->tmr_millis_on == HOLD_ZERO) { // 常低
pPIN->tmr_stage = PIN_STAGE_IDLE;
rt_timer_stop(pPIN->tmr_fd);
tmr_pin_set(pPIN, PIN_HIGH);
} else if (pPIN->tmr_millis_off == HOLD_ZERO) { // 常高
pPIN->tmr_stage = PIN_STAGE_IDLE;
tmr_pin_set(pPIN, PIN_LOW);
} else { // 交替
if (pPIN->tmr_stage == PIN_STAGE_IDLE) {
pPIN->tmr_stage = PIN_STAGE_ON;
tmr_pin_set(pPIN, PIN_LOW);
tmr_pin_timer_set_on(pPIN);
ret = rt_timer_start(pPIN->tmr_fd);
}
}
}
return ret;
}
static void tmr_pin_timer_timeout_callback (void* parameter)
{
struct tmr_pin_t *pPIN = (struct tmr_pin_t *)parameter;
if (pPIN->tmr_stage == PIN_STAGE_ON) {
pPIN->tmr_stage = PIN_STAGE_OFF;
tmr_pin_set(pPIN, PIN_HIGH);
tmr_pin_timer_set_off(pPIN);
rt_timer_start(pPIN->tmr_fd);
} else if (pPIN->tmr_stage == PIN_STAGE_OFF) {
pPIN->tmr_stage = PIN_STAGE_IDLE;
if ((pPIN->tmr_times == TIMES_ALWAYS)&&(pPIN->tmr_millis_off != HOLD_ZERO)) { // 保持闪烁
pPIN->tmr_stage = PIN_STAGE_ON;
tmr_pin_set(pPIN, PIN_LOW);
tmr_pin_timer_set_on(pPIN);
rt_timer_start(pPIN->tmr_fd);
} else { // 计数闪烁
if (++pPIN->tmr_cnt >= pPIN->tmr_times) {
pPIN->tmr_cnt = 0;
rt_timer_stop(pPIN->tmr_fd);
} else {
pPIN->tmr_stage = PIN_STAGE_ON;
tmr_pin_set(pPIN, PIN_LOW);
tmr_pin_timer_set_on(pPIN);
rt_timer_start(pPIN->tmr_fd);
}
}
}
}
static rt_int32_t tmr_pin_timer_start (ePIN_IDX index)
{
if (index >= TOTAL_PINS) {
return -1;
}
struct tmr_pin_t *pPIN = RT_NULL;
pPIN = &tmrpins[index];
pPIN->tmr_fd = rt_timer_create(pPIN->tmr_name, tmr_pin_timer_timeout_callback,
pPIN, pPIN->tmr_millis_on, RT_TIMER_FLAG_ONE_SHOT);
if (pPIN->tmr_fd == RT_NULL) {
//LOG_E("tmr '%s'", pPIN->tmr_name);
return -1;
}
return 0;
}
rt_int32_t tmr_pin_timer_delete (ePIN_IDX index)
{
if (index >= TOTAL_PINS) {
return -1;
}
return rt_timer_delete(tmrpins[index].tmr_fd);
}
static rt_int32_t tmr_pin_show (struct tmr_pin_t *pPIN, rt_uint32_t times, rt_uint32_t on, rt_uint32_t off)
{
rt_int32_t ret = 0;
pPIN->tmr_millis_on = on;
pPIN->tmr_millis_off = off;
pPIN->tmr_times = times;
pPIN->tmr_cnt = 0;
if (pPIN->tmr_millis_on == HOLD_ZERO) {
ret = tmr_pin_pulsing(pPIN, PULSE_OFF);
} else {
ret = tmr_pin_pulsing(pPIN, PULSE_ON);
}
return ret;
}
rt_int32_t tmr_led_flashing (ePIN_IDX index, rt_uint32_t times, rt_uint32_t on, rt_uint32_t off)
{
rt_int32_t ret = -1;
struct tmr_pin_t *pPIN = NULL;
if (index < TOTAL_PINS) {
pPIN = &tmrpins[index];
ret = tmr_pin_show(pPIN, times, on, off);
}
return ret;
}
static int tmr_pins_init (void)
{
rt_uint8_t i = 0;
struct tmr_pin_t *pPIN = RT_NULL;
for (i = 0; i < TOTAL_PINS; i++) {
pPIN = &tmrpins[i];
rt_pin_mode(pPIN->pin_base, pPIN->pin_mode);
if (pPIN->pin_mode == PIN_MODE_OUTPUT) {
pPIN->pin_value = PIN_HIGH;
rt_pin_write(pPIN->pin_base, pPIN->pin_value);
}
//LOG_I("I : set '%s'(%d) mode %d", pPIN->pin_name, pPIN->pin_base, pPIN->pin_mode);
tmr_pin_timer_start((ePIN_IDX)i);
}
tmr_led_flashing(IDX_PIN_LED1, TIMES_ALWAYS, PULSE_TIME*8, PULSE_TIME*8);
return 0;
}
INIT_ENV_EXPORT(tmr_pins_init);
apps/chrg/applications/tmr_pin.h
+75
View File
@@ -0,0 +1,75 @@
#ifndef __PIN_TMR_H__
#define __PIN_TMR_H__
#include <rttypes.h>
#include <rtdef.h>
#include "drv_gpio.h"
#define PIN_NAME_LED1 "led1"
#define PIN_NAME_LED2 "led2"
#define PIN_NAME_LED3 "led3"
#define TMR_NAME_LED1 "tmr_led1"
#define TMR_NAME_LED2 "tmr_led2"
#define TMR_NAME_LED3 "tmr_led3"
#define PIN_LED1 GET_PIN(A, 8) //GET_PIN(C, 13)
#define PIN_LED2 GET_PIN(C, 14)
#define PIN_LED3 GET_PIN(C, 15)
#define TIMES_ALWAYS (0) // 无限周期
#define TIMES_ONE (1) // 单个周期
#define HOLD_ZERO (0) // 屏蔽参数
#define HOLD_ON (1) // 保持亮，on!=0,off=0
#define HOLD_OFF (1) // 保持灭，on=0, off!=0
#define PULSE_OFF (0) // 脉宽低
#define PULSE_ON (1) // 脉宽高
#define PULSE_TIME (25) // 脉冲动作持续时间，单位 ms
typedef enum {
IDX_PIN_LED1 = 0, // LED1
// IDX_PIN_LED2 = 1, // LED2
// IDX_PIN_LED3 = 2, // LED3
TOTAL_PINS
} ePIN_IDX;
typedef enum {
PIN_STAGE_IDLE = (0x00), // 空闲
PIN_STAGE_ON = (0x01), // 保持高
PIN_STAGE_OFF = (0x02), // 保持低
PIN_STAGE_END
} ePIN_STAGE;
struct tmr_pin_t {
rt_uint8_t index; // 引脚索引
char *pin_name; // 引脚名
rt_int32_t pin_base; // 引脚映射值
rt_int32_t pin_value; // 引脚值
rt_uint8_t pin_mode; // 引脚控制方向 0:out 1:in
const char *tmr_name; // 定时器名
rt_timer_t tmr_fd; // 定时器对象
ePIN_STAGE tmr_stage; // 定时器状态机
rt_uint32_t tmr_millis_on; // 定时器单次高持续时间 ms=ticks (基于 1000 ticks/s)
rt_uint32_t tmr_millis_off; // 定时器单次低持续时间 ms=ticks (基于 1000 ticks/s)
rt_uint32_t tmr_times; // 定时器执行周期总次数
rt_uint32_t tmr_cnt; // 定时器已执行周期次数
};
extern struct tmr_pin_t tmrpins[TOTAL_PINS];
extern rt_int32_t tmr_pin_set (struct tmr_pin_t *pPIN, rt_uint8_t value);
extern rt_int32_t tmr_pin_toggle (ePIN_IDX index);
extern rt_int32_t tmr_pin_pulsing (struct tmr_pin_t *pPIN, rt_uint8_t state);
extern rt_int32_t tmr_led_flashing (ePIN_IDX index, rt_uint32_t times, rt_uint32_t on, rt_uint32_t off);
#endif
apps/chrg/applications/usart2.c
+1 -1
View File
@@ -10,7 +10,7 @@ rt_err_t usart2_rx_irq(rt_device_t dev, rt_size_t size)
return RT_EOK; return RT_EOK;
} }
rt_err_t usart2_open(void) static int usart2_open(void)
{ {
rt_err_t ret; rt_err_t ret;
apps/chrg/board/Kconfig
+10
View File
@@ -250,6 +250,16 @@ menu "On-chip Peripheral Drivers"
endif endif
menuconfig BSP_USING_CAN
bool "Enable On Board CAN"
select RT_USING_CAN
default n
if BSP_USING_CAN
config BSP_USING_CAN1
bool "Enable On Board CAN1"
default n
endif
source "$(RTT_DIR)/bsp/stm32/libraries/HAL_Drivers/drivers/Kconfig" source "$(RTT_DIR)/bsp/stm32/libraries/HAL_Drivers/drivers/Kconfig"
endmenu endmenu
apps/chrg/project.uvprojx
+189 -184
View File
@@ -337,9 +337,9 @@
<v6Rtti>0</v6Rtti> <v6Rtti>0</v6Rtti>
<VariousControls> <VariousControls>
<MiscControls></MiscControls> <MiscControls></MiscControls>
<Define>RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, STM32F405xx, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_LIBC, USE_HAL_DRIVER, USER_VECT_TAB_ADDRESS=0x08010000</Define> <Define>RT_USING_ARMLIBC, RT_USING_LIBC, __RTTHREAD__, __STDC_LIMIT_MACROS, __CLK_TCK=RT_TICK_PER_SECOND, STM32F405xx, USE_HAL_DRIVER</Define>
<Undefine></Undefine> <Undefine></Undefine>
<IncludePath>..\..\rt-thread\components\libc\posix\io\poll;..\..\rt-thread\components\drivers\include;..\..\rt-thread\components\libc\compilers\common\extension\fcntl\octal;..\..\rt-thread\components\drivers\smp_call;..\..\rt-thread\libcpu\arm\common;..\..\rt-thread\components\drivers\include;..\..\rt-thread\components\libc\posix\io\eventfd;..\..\libs\cmsis-core\Include;board;..\..\libs\freemodbus\modbus\tcp;..\..\rt-thread\bsp\stm32\libraries\HAL_Drivers\drivers\config;..\..\rt-thread\include;..\..\rt-thread\libcpu\arm\cortex-m4;..\..\rt-thread\bsp\stm32\libraries\HAL_Drivers;applications;..\..\libs\freemodbus\port;..\..\rt-thread\components\drivers\include;..\..\rt-thread\components\drivers\phy;board\CubeMX_Config\Inc;..\..\rt-thread\components\libc\posix\ipc;..\..\libs\stm32f4\STM32F4_HAL\Inc\Legacy;..\..\rt-thread\bsp\stm32\libraries\HAL_Drivers\drivers;..\..\rt-thread\components\libc\posix\io\epoll;..\..\libs\stm32f4\STM32F4_CMSIS\Include;..\..\rt-thread\components\libc\compilers\common\extension;..\..\rt-thread\components\drivers\include;..\..\rt-thread\components\drivers\include;..\..\libs\freemodbus\modbus\include;..\..\libs\freemodbus\modbus\ascii;.;..\..\rt-thread\components\libc\compilers\common\include;..\..\libs\freemodbus\modbus\rtu;..\..\libs\stm32f4\STM32F4_HAL\Inc;..\..\rt-thread\components\finsh;..\..\rt-thread\components\drivers\include</IncludePath> <IncludePath>..\..\libs\freemodbus\modbus\include;..\..\rt-thread\include;..\..\rt-thread\components\libc\posix\ipc;..\..\rt-thread\components\drivers\include;..\..\libs\freemodbus\modbus\tcp;..\..\rt-thread\bsp\stm32\libraries\HAL_Drivers;..\..\rt-thread\components\drivers\smp_call;..\..\libs\stm32f4\STM32F4_HAL\Inc;..\..\rt-thread\components\libc\compilers\common\include;..\..\libs\freemodbus\modbus\rtu;..\..\rt-thread\bsp\stm32\libraries\HAL_Drivers\drivers\config;..\..\rt-thread\components\drivers\include;..\..\rt-thread\components\drivers\include;..\..\rt-thread\components\drivers\include;..\..\rt-thread\libcpu\arm\common;..\..\libs\stm32f4\STM32F4_HAL\Inc\Legacy;board;..\..\rt-thread\components\libc\posix\io\eventfd;.;..\..\rt-thread\bsp\stm32\libraries\HAL_Drivers\drivers;..\..\rt-thread\components\libc\compilers\common\extension\fcntl\octal;..\..\rt-thread\components\drivers\include;..\..\libs\freemodbus\modbus\ascii;..\..\rt-thread\components\libc\posix\io\epoll;..\..\rt-thread\components\drivers\include;..\..\rt-thread\components\libc\compilers\common\extension;..\..\rt-thread\components\drivers\phy;board\CubeMX_Config\Inc;..\..\libs\stm32f4\STM32F4_CMSIS\Include;..\..\rt-thread\libcpu\arm\cortex-m4;..\..\libs\cmsis-core\Include;..\..\rt-thread\components\finsh;applications;..\..\rt-thread\components\libc\posix\io\poll;..\..\libs\freemodbus\port</IncludePath>
</VariousControls> </VariousControls>
</Cads> </Cads>
<Aads> <Aads>
@@ -383,16 +383,21 @@
<Group> <Group>
<GroupName>Applications</GroupName> <GroupName>Applications</GroupName>
<Files> <Files>
<File>
<FileName>tmr_pin.c</FileName>
<FileType>1</FileType>
<FilePath>applications\tmr_pin.c</FilePath>
</File>
<File>
<FileName>tmr_clk.c</FileName>
<FileType>1</FileType>
<FilePath>applications\tmr_clk.c</FilePath>
</File>
<File> <File>
<FileName>usart2.c</FileName> <FileName>usart2.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>applications\usart2.c</FilePath> <FilePath>applications\usart2.c</FilePath>
</File> </File>
<File>
<FileName>led_show.c</FileName>
<FileType>1</FileType>
<FilePath>applications\led_show.c</FilePath>
</File>
<File> <File>
<FileName>main.c</FileName> <FileName>main.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
@@ -1328,16 +1333,6 @@
<Group> <Group>
<GroupName>Finsh</GroupName> <GroupName>Finsh</GroupName>
<Files> <Files>
<File>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\rt-thread\components\finsh\shell.c</FilePath>
</File>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\rt-thread\components\finsh\msh.c</FilePath>
</File>
<File> <File>
<FileName>msh_parse.c</FileName> <FileName>msh_parse.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
@@ -1348,101 +1343,46 @@
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\rt-thread\components\finsh\cmd.c</FilePath> <FilePath>..\..\rt-thread\components\finsh\cmd.c</FilePath>
</File> </File>
<File>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\rt-thread\components\finsh\shell.c</FilePath>
</File>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\rt-thread\components\finsh\msh.c</FilePath>
</File>
</Files> </Files>
</Group> </Group>
<Group> <Group>
<GroupName>FreeModbus</GroupName> <GroupName>FreeModbus</GroupName>
<Files> <Files>
<File>
<FileName>mbfuncinput_m.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\functions\mbfuncinput_m.c</FilePath>
</File>
<File>
<FileName>mb.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\mb.c</FilePath>
</File>
<File>
<FileName>mbfuncother.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\functions\mbfuncother.c</FilePath>
</File>
<File>
<FileName>mb_m.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\mb_m.c</FilePath>
</File>
<File>
<FileName>mbrtu.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\rtu\mbrtu.c</FilePath>
</File>
<File>
<FileName>mbfuncdiag.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\functions\mbfuncdiag.c</FilePath>
</File>
<File>
<FileName>porttimer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\port\porttimer.c</FilePath>
</File>
<File> <File>
<FileName>mbfuncholding.c</FileName> <FileName>mbfuncholding.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\functions\mbfuncholding.c</FilePath> <FilePath>..\..\libs\freemodbus\modbus\functions\mbfuncholding.c</FilePath>
</File> </File>
<File> <File>
<FileName>mbfunccoils_m.c</FileName> <FileName>sample_mb_slave.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\functions\mbfunccoils_m.c</FilePath> <FilePath>..\..\libs\freemodbus\samples\sample_mb_slave.c</FilePath>
</File> </File>
<File> <File>
<FileName>user_mb_app.c</FileName> <FileName>mbfuncinput.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\port\user_mb_app.c</FilePath> <FilePath>..\..\libs\freemodbus\modbus\functions\mbfuncinput.c</FilePath>
</File> </File>
<File> <File>
<FileName>sample_mb_master.c</FileName> <FileName>portserial.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\samples\sample_mb_master.c</FilePath> <FilePath>..\..\libs\freemodbus\port\portserial.c</FilePath>
</File>
<File>
<FileName>mbfuncholding_m.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\functions\mbfuncholding_m.c</FilePath>
</File>
<File>
<FileName>mbfuncdisc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\functions\mbfuncdisc.c</FilePath>
</File> </File>
<File> <File>
<FileName>porttcp.c</FileName> <FileName>porttcp.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\port\porttcp.c</FilePath> <FilePath>..\..\libs\freemodbus\port\porttcp.c</FilePath>
</File> </File>
<File>
<FileName>user_mb_app_m.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\port\user_mb_app_m.c</FilePath>
</File>
<File>
<FileName>portevent.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\port\portevent.c</FilePath>
</File>
<File>
<FileName>mbfuncdisc_m.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\functions\mbfuncdisc_m.c</FilePath>
</File>
<File>
<FileName>portserial_m.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\port\portserial_m.c</FilePath>
</File>
<File> <File>
<FileName>mbrtu_m.c</FileName> <FileName>mbrtu_m.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
@@ -1454,24 +1394,49 @@
<FilePath>..\..\libs\freemodbus\port\port.c</FilePath> <FilePath>..\..\libs\freemodbus\port\port.c</FilePath>
</File> </File>
<File> <File>
<FileName>mbutils.c</FileName> <FileName>user_mb_app_m.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\functions\mbutils.c</FilePath> <FilePath>..\..\libs\freemodbus\port\user_mb_app_m.c</FilePath>
</File> </File>
<File> <File>
<FileName>mbfuncinput.c</FileName> <FileName>sample_mb_master.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\functions\mbfuncinput.c</FilePath> <FilePath>..\..\libs\freemodbus\samples\sample_mb_master.c</FilePath>
</File> </File>
<File> <File>
<FileName>portevent_m.c</FileName> <FileName>mbfuncholding_m.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\port\portevent_m.c</FilePath> <FilePath>..\..\libs\freemodbus\modbus\functions\mbfuncholding_m.c</FilePath>
</File> </File>
<File> <File>
<FileName>mbcrc.c</FileName> <FileName>mbrtu.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\rtu\mbcrc.c</FilePath> <FilePath>..\..\libs\freemodbus\modbus\rtu\mbrtu.c</FilePath>
</File>
<File>
<FileName>mbfuncinput_m.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\functions\mbfuncinput_m.c</FilePath>
</File>
<File>
<FileName>mb.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\mb.c</FilePath>
</File>
<File>
<FileName>mbfuncdisc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\functions\mbfuncdisc.c</FilePath>
</File>
<File>
<FileName>mbfunccoils_m.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\functions\mbfunccoils_m.c</FilePath>
</File>
<File>
<FileName>mbfuncdisc_m.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\functions\mbfuncdisc_m.c</FilePath>
</File> </File>
<File> <File>
<FileName>porttimer_m.c</FileName> <FileName>porttimer_m.c</FileName>
@@ -1479,9 +1444,19 @@
<FilePath>..\..\libs\freemodbus\port\porttimer_m.c</FilePath> <FilePath>..\..\libs\freemodbus\port\porttimer_m.c</FilePath>
</File> </File>
<File> <File>
<FileName>sample_mb_slave.c</FileName> <FileName>mbutils.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\samples\sample_mb_slave.c</FilePath> <FilePath>..\..\libs\freemodbus\modbus\functions\mbutils.c</FilePath>
</File>
<File>
<FileName>porttimer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\port\porttimer.c</FilePath>
</File>
<File>
<FileName>portserial_m.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\port\portserial_m.c</FilePath>
</File> </File>
<File> <File>
<FileName>mbfunccoils.c</FileName> <FileName>mbfunccoils.c</FileName>
@@ -1489,9 +1464,39 @@
<FilePath>..\..\libs\freemodbus\modbus\functions\mbfunccoils.c</FilePath> <FilePath>..\..\libs\freemodbus\modbus\functions\mbfunccoils.c</FilePath>
</File> </File>
<File> <File>
<FileName>portserial.c</FileName> <FileName>mbfuncother.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\port\portserial.c</FilePath> <FilePath>..\..\libs\freemodbus\modbus\functions\mbfuncother.c</FilePath>
</File>
<File>
<FileName>mbcrc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\rtu\mbcrc.c</FilePath>
</File>
<File>
<FileName>mbfuncdiag.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\functions\mbfuncdiag.c</FilePath>
</File>
<File>
<FileName>user_mb_app.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\port\user_mb_app.c</FilePath>
</File>
<File>
<FileName>portevent.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\port\portevent.c</FilePath>
</File>
<File>
<FileName>mb_m.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\modbus\mb_m.c</FilePath>
</File>
<File>
<FileName>portevent_m.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\freemodbus\port\portevent_m.c</FilePath>
</File> </File>
</Files> </Files>
</Group> </Group>
@@ -2343,16 +2348,6 @@
<Group> <Group>
<GroupName>klibc</GroupName> <GroupName>klibc</GroupName>
<Files> <Files>
<File>
<FileName>kstdio.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\rt-thread\src\klibc\kstdio.c</FilePath>
</File>
<File>
<FileName>kstring.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\rt-thread\src\klibc\kstring.c</FilePath>
</File>
<File> <File>
<FileName>kerrno.c</FileName> <FileName>kerrno.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
@@ -2363,11 +2358,21 @@
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\rt-thread\src\klibc\rt_vsscanf.c</FilePath> <FilePath>..\..\rt-thread\src\klibc\rt_vsscanf.c</FilePath>
</File> </File>
<File>
<FileName>kstdio.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\rt-thread\src\klibc\kstdio.c</FilePath>
</File>
<File> <File>
<FileName>rt_vsnprintf_tiny.c</FileName> <FileName>rt_vsnprintf_tiny.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\rt-thread\src\klibc\rt_vsnprintf_tiny.c</FilePath> <FilePath>..\..\rt-thread\src\klibc\rt_vsnprintf_tiny.c</FilePath>
</File> </File>
<File>
<FileName>kstring.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\rt-thread\src\klibc\kstring.c</FilePath>
</File>
</Files> </Files>
</Group> </Group>
<Group> <Group>
@@ -2403,86 +2408,21 @@
<Group> <Group>
<GroupName>STM32F4-CMSIS</GroupName> <GroupName>STM32F4-CMSIS</GroupName>
<Files> <Files>
<File>
<FileName>system_stm32f4xx.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_CMSIS\Source\Templates\system_stm32f4xx.c</FilePath>
</File>
<File> <File>
<FileName>startup_stm32f405xx.s</FileName> <FileName>startup_stm32f405xx.s</FileName>
<FileType>2</FileType> <FileType>2</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_CMSIS\Source\Templates\arm\startup_stm32f405xx.s</FilePath> <FilePath>..\..\libs\stm32f4\STM32F4_CMSIS\Source\Templates\arm\startup_stm32f405xx.s</FilePath>
</File> </File>
<File>
<FileName>system_stm32f4xx.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_CMSIS\Source\Templates\system_stm32f4xx.c</FilePath>
</File>
</Files> </Files>
</Group> </Group>
<Group> <Group>
<GroupName>STM32F4-HAL</GroupName> <GroupName>STM32F4-HAL</GroupName>
<Files> <Files>
<File>
<FileName>stm32f4xx_hal_rcc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_rcc.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_uart.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_rng.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_rng.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_cryp_ex.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_cryp_ex.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_dma.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_pwr.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_pwr.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_usart.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_usart.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_cec.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_cec.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_cortex.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_cortex.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_cryp.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_cryp.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_pwr_ex.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_pwr_ex.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_i2c.c</FilePath>
</File>
<File> <File>
<FileName>stm32f4xx_hal_crc.c</FileName> <FileName>stm32f4xx_hal_crc.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
@@ -2494,9 +2434,29 @@
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_i2c_ex.c</FilePath> <FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_i2c_ex.c</FilePath>
</File> </File>
<File> <File>
<FileName>stm32f4xx_hal_dma_ex.c</FileName> <FileName>stm32f4xx_hal_cortex.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_dma_ex.c</FilePath> <FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_cortex.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_i2c.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_gpio.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_pwr_ex.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_pwr_ex.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_dma.c</FilePath>
</File> </File>
<File> <File>
<FileName>stm32f4xx_hal_rcc_ex.c</FileName> <FileName>stm32f4xx_hal_rcc_ex.c</FileName>
@@ -2504,9 +2464,54 @@
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_rcc_ex.c</FilePath> <FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_rcc_ex.c</FilePath>
</File> </File>
<File> <File>
<FileName>stm32f4xx_hal_gpio.c</FileName> <FileName>stm32f4xx_hal_pwr.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_gpio.c</FilePath> <FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_pwr.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_rng.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_rng.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_uart.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_rcc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_rcc.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_usart.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_usart.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_dma_ex.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_dma_ex.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_cec.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_cec.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_cryp_ex.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_cryp_ex.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_cryp.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_cryp.c</FilePath>
</File> </File>
</Files> </Files>
</Group> </Group>
apps/chrg/rtconfig.h
+1 -1
View File
@@ -463,7 +463,7 @@
#define BSP_USING_UART1 #define BSP_USING_UART1
#define BSP_USING_UART2 #define BSP_USING_UART2
#define BSP_USING_UART3 #define BSP_USING_UART3
#define BSP_USING_UART4 #define BSP_USING_UART5
#define BSP_USING_UART6 #define BSP_USING_UART6
#define BSP_USING_I2C #define BSP_USING_I2C
#define BSP_USING_I2C1 #define BSP_USING_I2C1
apps/chrg/template.uvprojx
+1 -1
View File
@@ -336,7 +336,7 @@
<v6Rtti>0</v6Rtti> <v6Rtti>0</v6Rtti>
<VariousControls> <VariousControls>
<MiscControls></MiscControls> <MiscControls></MiscControls>
<Define>STM32F405xx, USE_HAL_DRIVER, USER_VECT_TAB_ADDRESS=0x08010000</Define> <Define>STM32F405xx, USE_HAL_DRIVER</Define>
<Undefine></Undefine> <Undefine></Undefine>
<IncludePath>.;..\..\..\include;applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;packages\led;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include</IncludePath> <IncludePath>.;..\..\..\include;applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;packages\led;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include</IncludePath>
</VariousControls> </VariousControls>
libs/cmsis-core/Include/core_cm1.h
-984
View File
@@ -1,984 +0,0 @@
/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.1.0
* @date 04. April 2023
******************************************************************************/
/*
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ti__)
#if defined __ARM_FP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
libs/cmsis-core/Include/core_cm7.h
-2407
View File
File diff suppressed because it is too large Load Diff
libs/stm32f4/STM32F4_CMSIS/Source/Templates/system_stm32f4xx.c
+1 -4
View File
@@ -92,9 +92,6 @@
anywhere in Flash or Sram, else the vector table is kept at the automatic anywhere in Flash or Sram, else the vector table is kept at the automatic
remap of boot address selected */ remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */ /* #define USER_VECT_TAB_ADDRESS */
#if !defined(USER_VECT_TAB_ADDRESS)
#define USER_VECT_TAB_ADDRESS 0x0
#endif
#if defined(USER_VECT_TAB_ADDRESS) #if defined(USER_VECT_TAB_ADDRESS)
/*!< Uncomment the following line if you need to relocate your vector Table /*!< Uncomment the following line if you need to relocate your vector Table
@@ -108,7 +105,7 @@
#else #else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET USER_VECT_TAB_ADDRESS /*0x00000000U /*!< Vector Table base offset field. #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */ #endif /* VECT_TAB_SRAM */
#endif /* USER_VECT_TAB_ADDRESS */ #endif /* USER_VECT_TAB_ADDRESS */
rt-thread/bsp/stm32/libraries/HAL_Drivers/CMSIS/Include/core_cm1.h
-976
View File
@@ -1,976 +0,0 @@
/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.0
* @date 23. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
rt-thread/bsp/stm32/libraries/HAL_Drivers/CMSIS/Include/core_cm7.h
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