first commit for chrg
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wmano
@@ -0,0 +1,320 @@
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/*
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* Copyright (c) 2022, sakumisu
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef CHERRYUSB_CONFIG_H
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#define CHERRYUSB_CONFIG_H
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/* ================ USB common Configuration ================ */
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#ifdef __RTTHREAD__
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#include <rtthread.h>
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#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__)
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#else
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#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__)
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#endif
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#ifndef CONFIG_USB_DBG_LEVEL
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#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO
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#endif
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/* Enable print with color */
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#define CONFIG_USB_PRINTF_COLOR_ENABLE
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// #define CONFIG_USB_DCACHE_ENABLE
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/* data align size when use dma or use dcache */
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#ifdef CONFIG_USB_DCACHE_ENABLE
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#define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64
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#else
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#define CONFIG_USB_ALIGN_SIZE 4
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#endif
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/* attribute data into no cache ram */
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#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable")))
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/* use usb_memcpy default for high performance but cost more flash memory.
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* And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4.
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*/
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// #define CONFIG_USB_MEMCPY_DISABLE
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/* ================= USB Device Stack Configuration ================ */
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/* Ep0 in and out transfer buffer */
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#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN
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#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512
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#endif
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/* Send ep0 in data from user buffer instead of copying into ep0 reqdata
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* Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE
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*/
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// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY
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/* Check if the input descriptor is correct */
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// #define CONFIG_USBDEV_DESC_CHECK
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/* Enable test mode */
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// #define CONFIG_USBDEV_TEST_MODE
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/* enable advance desc register api */
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#define CONFIG_USBDEV_ADVANCE_DESC
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/* move ep0 setup handler from isr to thread */
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// #define CONFIG_USBDEV_EP0_THREAD
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#ifndef CONFIG_USBDEV_EP0_PRIO
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#define CONFIG_USBDEV_EP0_PRIO 4
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#endif
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#ifndef CONFIG_USBDEV_EP0_STACKSIZE
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#define CONFIG_USBDEV_EP0_STACKSIZE 2048
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#endif
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#ifndef CONFIG_USBDEV_MSC_MAX_LUN
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#define CONFIG_USBDEV_MSC_MAX_LUN 1
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#endif
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#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE
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#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512
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#endif
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#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING
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#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING ""
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#endif
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#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING
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#define CONFIG_USBDEV_MSC_PRODUCT_STRING ""
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#endif
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#ifndef CONFIG_USBDEV_MSC_VERSION_STRING
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#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01"
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#endif
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/* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */
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// #define CONFIG_USBDEV_MSC_POLLING
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/* move msc read & write from isr to thread */
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// #define CONFIG_USBDEV_MSC_THREAD
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#ifndef CONFIG_USBDEV_MSC_PRIO
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#define CONFIG_USBDEV_MSC_PRIO 4
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#endif
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#ifndef CONFIG_USBDEV_MSC_STACKSIZE
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#define CONFIG_USBDEV_MSC_STACKSIZE 2048
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#endif
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#ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE
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#define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048
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#endif
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#ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS
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#define CONFIG_USBDEV_MTP_MAX_OBJECTS 256
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#endif
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#ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME
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#define CONFIG_USBDEV_MTP_MAX_PATHNAME 256
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#endif
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#define CONFIG_USBDEV_MTP_THREAD
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#ifndef CONFIG_USBDEV_MTP_PRIO
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#define CONFIG_USBDEV_MTP_PRIO 4
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#endif
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#ifndef CONFIG_USBDEV_MTP_STACKSIZE
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#define CONFIG_USBDEV_MTP_STACKSIZE 4096
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#endif
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#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE
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#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
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#endif
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/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/
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#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE
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#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580
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#endif
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#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID
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#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff
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#endif
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#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC
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#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB"
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#endif
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#define CONFIG_USBDEV_RNDIS_USING_LWIP
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#define CONFIG_USBDEV_CDC_ECM_USING_LWIP
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/* ================ USB HOST Stack Configuration ================== */
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#define CONFIG_USBHOST_MAX_RHPORTS 1
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#define CONFIG_USBHOST_MAX_EXTHUBS 1
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#define CONFIG_USBHOST_MAX_EHPORTS 4
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#define CONFIG_USBHOST_MAX_INTERFACES 8
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#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 2
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#define CONFIG_USBHOST_MAX_ENDPOINTS 4
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#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4
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#define CONFIG_USBHOST_MAX_HID_CLASS 4
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#define CONFIG_USBHOST_MAX_MSC_CLASS 2
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#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1
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#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1
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#define CONFIG_USBHOST_DEV_NAMELEN 16
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#ifndef CONFIG_USBHOST_PSC_PRIO
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#define CONFIG_USBHOST_PSC_PRIO 0
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#endif
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#ifndef CONFIG_USBHOST_PSC_STACKSIZE
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#define CONFIG_USBHOST_PSC_STACKSIZE 2048
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#endif
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//#define CONFIG_USBHOST_GET_STRING_DESC
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// #define CONFIG_USBHOST_MSOS_ENABLE
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#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE
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#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00
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#endif
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/* Ep0 max transfer buffer */
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#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN
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#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512
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#endif
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#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT
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#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500
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#endif
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#ifndef CONFIG_USBHOST_MSC_TIMEOUT
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#define CONFIG_USBHOST_MSC_TIMEOUT 5000
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#endif
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/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
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* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
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*/
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#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE
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#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048)
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#endif
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/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
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#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE
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#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048)
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#endif
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/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
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* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
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*/
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#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE
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#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048)
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#endif
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/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
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#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE
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#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048)
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#endif
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/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
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* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
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*/
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#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE
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#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048)
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#endif
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/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
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#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE
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#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048)
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#endif
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/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size,
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* you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow.
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*/
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#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE
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#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048)
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#endif
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/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */
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#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE
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#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048)
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#endif
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#define CONFIG_USBHOST_BLUETOOTH_HCI_H4
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// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG
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#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE
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#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048
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#endif
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#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE
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#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048
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#endif
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/* ================ USB Device Port Configuration ================*/
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#ifndef CONFIG_USBDEV_MAX_BUS
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#define CONFIG_USBDEV_MAX_BUS 1
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#endif
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// #define CONFIG_USBDEV_SOF_ENABLE
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/* ---------------- FSDEV Configuration ---------------- */
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//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference
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/* ---------------- DWC2 Configuration ---------------- */
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/* enable dwc2 buffer dma mode for device
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* in xxx32 chips, only pb14/pb15 can support dma mode, pa11/pa12 is not supported(only a few supports, but we ignore them)
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*/
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// #define CONFIG_USB_DWC2_DMA_ENABLE
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/* ---------------- MUSB Configuration ---------------- */
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#define CONFIG_USB_MUSB_EP_NUM 8
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// #define CONFIG_USB_MUSB_SUNXI
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/* ================ USB Host Port Configuration ==================*/
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#ifndef CONFIG_USBHOST_MAX_BUS
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#define CONFIG_USBHOST_MAX_BUS 1
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#endif
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/* ---------------- EHCI Configuration ---------------- */
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#define CONFIG_USB_EHCI_HCCR_OFFSET (0x0)
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#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024
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#define CONFIG_USB_EHCI_QH_NUM 10
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#define CONFIG_USB_EHCI_QTD_NUM (CONFIG_USB_EHCI_QH_NUM * 3)
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#define CONFIG_USB_EHCI_ITD_NUM 4
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// #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE
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// #define CONFIG_USB_EHCI_CONFIGFLAG
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// #define CONFIG_USB_EHCI_ISO
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// #define CONFIG_USB_EHCI_WITH_OHCI
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// #define CONFIG_USB_EHCI_DESC_DCACHE_ENABLE
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/* ---------------- OHCI Configuration ---------------- */
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#define CONFIG_USB_OHCI_HCOR_OFFSET (0x0)
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#define CONFIG_USB_OHCI_ED_NUM 10
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#define CONFIG_USB_OHCI_TD_NUM 3
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// #define CONFIG_USB_OHCI_DESC_DCACHE_ENABLE
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/* ---------------- XHCI Configuration ---------------- */
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#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0)
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/* ---------------- DWC2 Configuration ---------------- */
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// nothing to define
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/* ---------------- MUSB Configuration ---------------- */
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#define CONFIG_USB_MUSB_PIPE_NUM 8
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// #define CONFIG_USB_MUSB_SUNXI
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/* When your chip hardware supports high-speed and wants to initialize it in high-speed mode,
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* the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS.
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*
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* in xxx32 chips, only pb14/pb15 can support hs mode, pa11/pa12 is not supported(only a few supports, but we ignore them).
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*/
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// #define CONFIG_USB_HS
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#ifndef usb_phyaddr2ramaddr
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#define usb_phyaddr2ramaddr(addr) (addr)
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#endif
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#ifndef usb_ramaddr2phyaddr
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#define usb_ramaddr2phyaddr(addr) (addr)
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#endif
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#endif
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