first commit for chrg

rt-thread/libcpu/Kconfig

@@ -0,0 +1,309 @@
+if ARCH_ARMV8 && ARCH_CPU_64BIT
+    orsource "./aarch64/Kconfig"
+endif
+
+config ARCH_CPU_64BIT
+    bool
+
+config RT_USING_CACHE
+    bool
+    default n
+
+config RT_USING_HW_ATOMIC
+    bool
+    default n
+
+config ARCH_CPU_BIG_ENDIAN
+    bool
+
+config ARCH_ARM_BOOTWITH_FLUSH_CACHE
+    bool
+    default n
+
+config ARCH_CPU_STACK_GROWS_UPWARD
+    bool
+    default n
+
+config RT_USING_CPU_FFS
+    bool
+    default n
+
+config ARCH_MM_MMU
+    bool
+
+config ARCH_MM_MPU
+    bool
+
+config ARCH_ARM
+    bool
+
+config ARCH_ARM_CORTEX_M
+    bool
+    select ARCH_ARM
+
+config ARCH_ARM_CORTEX_R
+    bool
+    select ARCH_ARM
+
+config ARCH_ARM_CORTEX_FPU
+    bool
+
+config ARCH_ARM_CORTEX_SECURE
+    bool
+
+config ARCH_ARM_CORTEX_M0
+    bool
+    select ARCH_ARM_CORTEX_M
+
+config ARCH_ARM_CORTEX_M3
+    bool
+    select ARCH_ARM_CORTEX_M
+    select RT_USING_CPU_FFS
+    select RT_USING_HW_ATOMIC
+
+config ARCH_ARM_MPU
+    bool
+    depends on ARCH_ARM
+    select ARCH_MM_MPU
+
+config ARCH_ARM_CORTEX_M4
+    bool
+    select ARCH_ARM_CORTEX_M
+    select RT_USING_CPU_FFS
+    select RT_USING_HW_ATOMIC
+
+config ARCH_ARM_CORTEX_M7
+    bool
+    select ARCH_ARM_CORTEX_M
+    select RT_USING_CPU_FFS
+    select RT_USING_CACHE
+    select RT_USING_HW_ATOMIC
+
+config ARCH_ARM_CORTEX_M85
+    bool
+    select ARCH_ARM_CORTEX_M
+    select RT_USING_CPU_FFS
+    select RT_USING_HW_ATOMIC
+
+config ARCH_ARM_CORTEX_M23
+    bool
+    select ARCH_ARM_CORTEX_M
+    select RT_USING_HW_ATOMIC
+
+config ARCH_ARM_CORTEX_M33
+    bool
+    select ARCH_ARM_CORTEX_M
+    select RT_USING_CPU_FFS
+    select RT_USING_HW_ATOMIC
+
+config ARCH_ARM_CORTEX_R
+    bool
+    select ARCH_ARM
+    select RT_USING_HW_ATOMIC
+
+config ARCH_ARM_CORTEX_R52
+    bool
+    select ARCH_ARM_CORTEX_R
+
+config ARCH_ARM_MMU
+    bool
+    select RT_USING_CACHE
+    select ARCH_MM_MMU
+    depends on ARCH_ARM
+
+if RT_USING_SMART
+    config KERNEL_VADDR_START
+        hex "The virtural address of kernel start"
+        default 0xffff000000000000 if ARCH_ARMV8
+        default 0xc0000000 if ARCH_ARM
+        default 0xffffffc000000000 if ARCH_RISCV && ARCH_REMAP_KERNEL
+        default 0x80000000 if ARCH_RISCV
+        depends on ARCH_MM_MMU
+
+    config RT_IOREMAP_LATE
+        bool "Support to create IO mapping in the kernel address space after system initlalization."
+        default n
+        depends on ARCH_ARM_CORTEX_A
+        depends on ARCH_MM_MMU
+endif
+
+config ARCH_ARM_ARM9
+    bool
+    select ARCH_ARM
+
+config ARCH_ARM_ARM11
+    bool
+    select ARCH_ARM
+
+config ARCH_ARM_CORTEX_A
+    bool
+    select ARCH_ARM
+    select ARCH_ARM_MMU
+    select RT_USING_CPU_FFS
+    select RT_USING_HW_ATOMIC
+
+    if ARCH_ARM_CORTEX_A
+        config RT_SMP_AUTO_BOOT
+            bool
+            default n
+
+        config RT_USING_GIC_V2
+            bool
+            default n
+
+        config RT_USING_GIC_V3
+            bool
+            default n
+
+        config RT_NO_USING_GIC
+            bool
+            default y if !RT_USING_GIC_V2 && !RT_USING_GIC_V3
+    endif
+
+config ARCH_ARM_CORTEX_A5
+    bool
+    select ARCH_ARM_CORTEX_A
+
+config ARCH_ARM_CORTEX_A7
+    bool
+    select ARCH_ARM_CORTEX_A
+
+config ARCH_ARM_CORTEX_A8
+    bool
+    select ARCH_ARM_CORTEX_A
+
+config ARCH_ARM_CORTEX_A9
+    bool
+    select ARCH_ARM_CORTEX_A
+
+config ARCH_ARM_CORTEX_A55
+    bool
+    select ARCH_ARM_CORTEX_A
+
+config ARCH_ARM_SECURE_MODE
+    bool "Running in secure mode [ARM Cortex-A]"
+    default n
+    depends on ARCH_ARM_CORTEX_A
+
+config RT_BACKTRACE_FUNCTION_NAME
+    bool "To show function name when backtrace."
+    default n
+    depends on ARCH_ARM_CORTEX_A
+
+config ARCH_ARMV8
+    bool
+    select ARCH_ARM
+    select ARCH_ARM_MMU
+    select RT_USING_CPU_FFS
+    select ARCH_USING_ASID
+    select ARCH_USING_IRQ_CTX_LIST
+
+config ARCH_MIPS
+    bool
+
+config ARCH_MIPS64
+    bool
+    select ARCH_CPU_64BIT
+
+config ARCH_MIPS_XBURST
+    bool
+    select ARCH_MIPS
+
+config ARCH_ANDES
+    bool
+
+config ARCH_CSKY
+    bool
+
+config ARCH_POWERPC
+    bool
+
+config ARCH_RISCV
+    bool
+
+config ARCH_RISCV_FPU
+    bool
+
+config ARCH_RISCV_VECTOR
+    bool
+
+    if ARCH_RISCV_VECTOR
+        choice
+            prompt "RISCV Vector Vlen"
+            default ARCH_VECTOR_VLEN_128
+
+            config ARCH_VECTOR_VLEN_128
+                bool "128"
+            config ARCH_VECTOR_VLEN_256
+                bool "256"
+        endchoice
+    endif
+
+config ARCH_RISCV_FPU_S
+    select ARCH_RISCV_FPU
+    bool
+
+config ARCH_RISCV_FPU_D
+    select ARCH_RISCV_FPU
+    bool
+
+config ARCH_RISCV32
+    select ARCH_RISCV
+    bool
+
+config ARCH_RISCV64
+    select ARCH_RISCV
+    select ARCH_CPU_64BIT
+    bool
+
+if ARCH_RISCV64
+    config ARCH_USING_NEW_CTX_SWITCH
+        bool
+        default y
+
+    config ARCH_USING_RISCV_COMMON64
+        bool
+        depends on ARCH_RISCV64
+        select RT_USING_CPUTIME
+        select ARCH_USING_NEW_CTX_SWITCH
+        help
+            Using the common64 implementation under ./libcpu/risc-v
+endif
+
+config ARCH_REMAP_KERNEL
+    bool
+    depends on RT_USING_SMART
+    help
+        Remapping kernel image to high virtual address region
+
+config ARCH_USING_ASID
+    bool
+    depends on RT_USING_SMART
+    help
+        Using ASID support from architecture
+
+config ARCH_IA32
+    bool
+
+config ARCH_TIDSP
+    bool
+
+config ARCH_TIDSP_C28X
+    bool
+    select ARCH_TIDSP
+    select ARCH_CPU_STACK_GROWS_UPWARD
+
+config ARCH_HOST_SIMULATOR
+    bool
+
+config ARCH_CPU_STACK_GROWS_UPWARD
+    bool
+    default n
+
+config ARCH_USING_HW_THREAD_SELF
+    bool
+    default n
+
+config ARCH_USING_IRQ_CTX_LIST
+    bool
+    default n

rt-thread/libcpu/SConscript

@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+if rtconfig.ARCH in list:
+    group = group + SConscript(os.path.join(rtconfig.ARCH, 'SConscript'))
+
+Return('group')

rt-thread/libcpu/arm/SConscript

@@ -0,0 +1,18 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd = GetCurrentDir()
+list = os.listdir(cwd)
+
+# add common code files
+group = SConscript(os.path.join('common', 'SConscript'))
+
+# cpu porting code files
+if rtconfig.CPU in list:
+    group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
+
+Return('group')

rt-thread/libcpu/arm/common/SConscript

@@ -0,0 +1,26 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM in ['armcc', 'armclang']:
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM in ['gcc']:
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM in ['iccarm']:
+    src += Glob('*_iar.S')
+
+if not GetDepend('RT_USING_HW_ATOMIC'):
+    SrcRemove(src, 'atomic_arm.c')
+
+group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

rt-thread/libcpu/arm/common/atomic_arm.c

@@ -0,0 +1,188 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-27     flybreak       the first version
+ */
+
+#include <rtthread.h>
+
+#if defined (__IAR_SYSTEMS_ICC__)     /* for IAR Compiler */
+#include <intrinsics.h>
+#include <iccarm_builtin.h>
+#endif
+/**
+ \brief   LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in]    ptr  Pointer to data
+ \return        value of type uint32_t at (*ptr)
+ */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+#define __LDREXW        (rt_atomic_t)__builtin_arm_ldrex
+#elif defined(__ARMCC_VERSION)          /* ARM Compiler V5 */
+#if __ARMCC_VERSION < 5060020
+#define __LDREXW(ptr)                                                        ((rt_atomic_t ) __ldrex(ptr))
+#else
+#define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((rt_atomic_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+#elif defined (__IAR_SYSTEMS_ICC__)     /* for IAR Compiler */
+_Pragma("inline=forced") __intrinsic rt_atomic_t __LDREXW(volatile rt_atomic_t *ptr)
+{
+    return __iar_builtin_LDREX((volatile unsigned int *)ptr);
+}
+#elif defined (__GNUC__)                /* GNU GCC Compiler */
+__attribute__((always_inline))     static inline rt_atomic_t __LDREXW(volatile rt_atomic_t *addr)
+{
+    rt_atomic_t result;
+
+    __asm volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+    return result;
+}
+#endif
+
+/**
+ \brief   STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in]  value  Value to store
+ \param [in]    ptr  Pointer to location
+ \return          0  Function succeeded
+ \return          1  Function failed
+ */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+#define __STREXW        (rt_atomic_t)__builtin_arm_strex
+#elif defined(__ARMCC_VERSION)          /* ARM Compiler V5 */
+#if __ARMCC_VERSION < 5060020
+#define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+#define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+#elif defined (__IAR_SYSTEMS_ICC__)     /* for IAR Compiler */
+_Pragma("inline=forced") __intrinsic rt_atomic_t __STREXW(rt_atomic_t value, volatile rt_atomic_t *ptr)
+{
+    return __STREX(value, (unsigned int *)ptr);
+}
+#elif defined (__GNUC__)                /* GNU GCC Compiler */
+__attribute__((always_inline))     static inline rt_atomic_t __STREXW(volatile rt_atomic_t value, volatile rt_atomic_t *addr)
+{
+    rt_atomic_t result;
+
+    __asm volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+    return result;
+}
+#endif
+
+rt_atomic_t rt_hw_atomic_load(volatile rt_atomic_t *ptr)
+{
+    rt_atomic_t oldval;
+    do
+    {
+        oldval = __LDREXW(ptr);
+    } while ((__STREXW(oldval, ptr)) != 0U);
+    return oldval;
+}
+
+void rt_hw_atomic_store(volatile rt_atomic_t *ptr, rt_atomic_t val)
+{
+    do
+    {
+        __LDREXW(ptr);
+    } while ((__STREXW(val, ptr)) != 0U);
+}
+
+rt_atomic_t rt_hw_atomic_add(volatile rt_atomic_t *ptr, rt_atomic_t val)
+{
+    rt_atomic_t oldval;
+    do
+    {
+        oldval = __LDREXW(ptr);
+    } while ((__STREXW(oldval + val, ptr)) != 0U);
+    return oldval;
+}
+
+rt_atomic_t rt_hw_atomic_sub(volatile rt_atomic_t *ptr, rt_atomic_t val)
+{
+    rt_atomic_t oldval;
+    do
+    {
+        oldval = __LDREXW(ptr);
+    } while ((__STREXW(oldval - val, ptr)) != 0U);
+    return oldval;
+}
+
+rt_atomic_t rt_hw_atomic_and(volatile rt_atomic_t *ptr, rt_atomic_t val)
+{
+    rt_atomic_t oldval;
+    do
+    {
+        oldval = __LDREXW(ptr);
+    } while ((__STREXW(oldval & val, ptr)) != 0U);
+    return oldval;
+}
+
+rt_atomic_t rt_hw_atomic_or(volatile rt_atomic_t *ptr, rt_atomic_t val)
+{
+    rt_atomic_t oldval;
+    do
+    {
+        oldval = __LDREXW(ptr);
+    } while ((__STREXW(oldval | val, ptr)) != 0U);
+    return oldval;
+}
+
+rt_atomic_t rt_hw_atomic_xor(volatile rt_atomic_t *ptr, rt_atomic_t val)
+{
+    rt_atomic_t oldval;
+    do
+    {
+        oldval = __LDREXW(ptr);
+    } while ((__STREXW(oldval ^ val, ptr)) != 0U);
+    return oldval;
+}
+
+rt_atomic_t rt_hw_atomic_exchange(volatile rt_atomic_t *ptr, rt_atomic_t val)
+{
+    rt_atomic_t oldval;
+    do
+    {
+        oldval = __LDREXW(ptr);
+    } while ((__STREXW(val, ptr)) != 0U);
+    return oldval;
+}
+
+void rt_hw_atomic_flag_clear(volatile rt_atomic_t *ptr)
+{
+    do
+    {
+        __LDREXW(ptr);
+    } while ((__STREXW(0, ptr)) != 0U);
+}
+
+rt_atomic_t rt_hw_atomic_flag_test_and_set(volatile rt_atomic_t *ptr)
+{
+    rt_atomic_t oldval;
+    do
+    {
+        oldval = __LDREXW(ptr);
+    } while ((__STREXW(1, ptr)) != 0U);
+    return oldval;
+}
+
+rt_atomic_t rt_hw_atomic_compare_exchange_strong(volatile rt_atomic_t *ptr, rt_atomic_t *old, rt_atomic_t new)
+{
+    rt_atomic_t result;
+    rt_atomic_t temp = *old;
+    do
+    {
+        result = __LDREXW(ptr);
+        if (result != temp)
+        {
+            *old = result;
+            __STREXW(result, ptr);
+            break;
+        }
+    } while ((__STREXW(new, ptr)) != 0U);
+    return (result == temp);
+}

rt-thread/libcpu/arm/common/div0.c

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+void __div0(void)
+{
+    while (1) ;
+}

rt-thread/libcpu/arm/common/divsi3.S

@@ -0,0 +1,401 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+/*  $NetBSD: divsi3.S,v 1.5 2005/02/26 22:58:56 perry Exp $ */
+
+/*
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * stack is aligned as there's a possibility of branching to L_overflow
+ * which makes a C call
+ */
+    .text
+    .align  0
+    .globl  __umodsi3
+    .type   __umodsi3 , function
+__umodsi3:
+    stmfd   sp!, {lr}
+    sub sp, sp, #4  /* align stack */
+    bl  .L_udivide
+    add sp, sp, #4  /* unalign stack */
+    mov r0, r1
+    ldmfd   sp!, {pc}
+
+    .text
+    .align  0
+    .globl  __modsi3
+    .type   __modsi3 , function
+__modsi3:
+    stmfd   sp!, {lr}
+    sub sp, sp, #4  /* align stack */
+    bl  .L_divide
+    add sp, sp, #4  /* unalign stack */
+    mov r0, r1
+    ldmfd   sp!, {pc}
+
+.L_overflow:
+    /* XXX should cause a fatal error */
+    mvn r0, #0
+    mov pc, lr
+
+    .text
+    .align  0
+    .globl  __udivsi3
+    .type   __udivsi3 , function
+__udivsi3:
+.L_udivide:             /* r0 = r0 / r1; r1 = r0 % r1 */
+    eor     r0, r1, r0
+    eor     r1, r0, r1
+    eor     r0, r1, r0
+                    /* r0 = r1 / r0; r1 = r1 % r0 */
+    cmp r0, #1
+    bcc .L_overflow
+    beq .L_divide_l0
+    mov ip, #0
+    movs    r1, r1
+    bpl .L_divide_l1
+    orr ip, ip, #0x20000000 /* ip bit 0x20000000 = -ve r1 */
+    movs    r1, r1, lsr #1
+    orrcs   ip, ip, #0x10000000 /* ip bit 0x10000000 = bit 0 of r1 */
+    b   .L_divide_l1
+
+.L_divide_l0:               /* r0 == 1 */
+    mov r0, r1
+    mov r1, #0
+    mov pc, lr
+
+    .text
+    .align  0
+    .globl  __divsi3
+    .type   __divsi3 , function
+__divsi3:
+.L_divide:              /* r0 = r0 / r1; r1 = r0 % r1 */
+    eor     r0, r1, r0
+    eor     r1, r0, r1
+    eor     r0, r1, r0
+                    /* r0 = r1 / r0; r1 = r1 % r0 */
+    cmp r0, #1
+    bcc .L_overflow
+    beq .L_divide_l0
+    ands    ip, r0, #0x80000000
+    rsbmi   r0, r0, #0
+    ands    r2, r1, #0x80000000
+    eor ip, ip, r2
+    rsbmi   r1, r1, #0
+    orr ip, r2, ip, lsr #1  /* ip bit 0x40000000 = -ve division */
+                    /* ip bit 0x80000000 = -ve remainder */
+
+.L_divide_l1:
+    mov r2, #1
+    mov r3, #0
+
+    /*
+     * If the highest bit of the dividend is set, we have to be
+     * careful when shifting the divisor. Test this.
+     */
+    movs    r1,r1
+    bpl .L_old_code
+
+    /*
+     * At this point, the highest bit of r1 is known to be set.
+     * We abuse this below in the tst instructions.
+     */
+    tst r1, r0 /*, lsl #0 */
+    bmi .L_divide_b1
+    tst r1, r0, lsl #1
+    bmi .L_divide_b2
+    tst r1, r0, lsl #2
+    bmi .L_divide_b3
+    tst r1, r0, lsl #3
+    bmi .L_divide_b4
+    tst r1, r0, lsl #4
+    bmi .L_divide_b5
+    tst r1, r0, lsl #5
+    bmi .L_divide_b6
+    tst r1, r0, lsl #6
+    bmi .L_divide_b7
+    tst r1, r0, lsl #7
+    bmi .L_divide_b8
+    tst r1, r0, lsl #8
+    bmi .L_divide_b9
+    tst r1, r0, lsl #9
+    bmi .L_divide_b10
+    tst r1, r0, lsl #10
+    bmi .L_divide_b11
+    tst r1, r0, lsl #11
+    bmi .L_divide_b12
+    tst r1, r0, lsl #12
+    bmi .L_divide_b13
+    tst r1, r0, lsl #13
+    bmi .L_divide_b14
+    tst r1, r0, lsl #14
+    bmi .L_divide_b15
+    tst r1, r0, lsl #15
+    bmi .L_divide_b16
+    tst r1, r0, lsl #16
+    bmi .L_divide_b17
+    tst r1, r0, lsl #17
+    bmi .L_divide_b18
+    tst r1, r0, lsl #18
+    bmi .L_divide_b19
+    tst r1, r0, lsl #19
+    bmi .L_divide_b20
+    tst r1, r0, lsl #20
+    bmi .L_divide_b21
+    tst r1, r0, lsl #21
+    bmi .L_divide_b22
+    tst r1, r0, lsl #22
+    bmi .L_divide_b23
+    tst r1, r0, lsl #23
+    bmi .L_divide_b24
+    tst r1, r0, lsl #24
+    bmi .L_divide_b25
+    tst r1, r0, lsl #25
+    bmi .L_divide_b26
+    tst r1, r0, lsl #26
+    bmi .L_divide_b27
+    tst r1, r0, lsl #27
+    bmi .L_divide_b28
+    tst r1, r0, lsl #28
+    bmi .L_divide_b29
+    tst r1, r0, lsl #29
+    bmi .L_divide_b30
+    tst r1, r0, lsl #30
+    bmi .L_divide_b31
+/*
+ * instead of:
+ *  tst r1, r0, lsl #31
+ *  bmi .L_divide_b32
+ */
+    b   .L_divide_b32
+
+.L_old_code:
+    cmp r1, r0
+    bcc .L_divide_b0
+    cmp r1, r0, lsl #1
+    bcc .L_divide_b1
+    cmp r1, r0, lsl #2
+    bcc .L_divide_b2
+    cmp r1, r0, lsl #3
+    bcc .L_divide_b3
+    cmp r1, r0, lsl #4
+    bcc .L_divide_b4
+    cmp r1, r0, lsl #5
+    bcc .L_divide_b5
+    cmp r1, r0, lsl #6
+    bcc .L_divide_b6
+    cmp r1, r0, lsl #7
+    bcc .L_divide_b7
+    cmp r1, r0, lsl #8
+    bcc .L_divide_b8
+    cmp r1, r0, lsl #9
+    bcc .L_divide_b9
+    cmp r1, r0, lsl #10
+    bcc .L_divide_b10
+    cmp r1, r0, lsl #11
+    bcc .L_divide_b11
+    cmp r1, r0, lsl #12
+    bcc .L_divide_b12
+    cmp r1, r0, lsl #13
+    bcc .L_divide_b13
+    cmp r1, r0, lsl #14
+    bcc .L_divide_b14
+    cmp r1, r0, lsl #15
+    bcc .L_divide_b15
+    cmp r1, r0, lsl #16
+    bcc .L_divide_b16
+    cmp r1, r0, lsl #17
+    bcc .L_divide_b17
+    cmp r1, r0, lsl #18
+    bcc .L_divide_b18
+    cmp r1, r0, lsl #19
+    bcc .L_divide_b19
+    cmp r1, r0, lsl #20
+    bcc .L_divide_b20
+    cmp r1, r0, lsl #21
+    bcc .L_divide_b21
+    cmp r1, r0, lsl #22
+    bcc .L_divide_b22
+    cmp r1, r0, lsl #23
+    bcc .L_divide_b23
+    cmp r1, r0, lsl #24
+    bcc .L_divide_b24
+    cmp r1, r0, lsl #25
+    bcc .L_divide_b25
+    cmp r1, r0, lsl #26
+    bcc .L_divide_b26
+    cmp r1, r0, lsl #27
+    bcc .L_divide_b27
+    cmp r1, r0, lsl #28
+    bcc .L_divide_b28
+    cmp r1, r0, lsl #29
+    bcc .L_divide_b29
+    cmp r1, r0, lsl #30
+    bcc .L_divide_b30
+.L_divide_b32:
+    cmp r1, r0, lsl #31
+    subhs   r1, r1,r0, lsl #31
+    addhs   r3, r3,r2, lsl #31
+.L_divide_b31:
+    cmp r1, r0, lsl #30
+    subhs   r1, r1,r0, lsl #30
+    addhs   r3, r3,r2, lsl #30
+.L_divide_b30:
+    cmp r1, r0, lsl #29
+    subhs   r1, r1,r0, lsl #29
+    addhs   r3, r3,r2, lsl #29
+.L_divide_b29:
+    cmp r1, r0, lsl #28
+    subhs   r1, r1,r0, lsl #28
+    addhs   r3, r3,r2, lsl #28
+.L_divide_b28:
+    cmp r1, r0, lsl #27
+    subhs   r1, r1,r0, lsl #27
+    addhs   r3, r3,r2, lsl #27
+.L_divide_b27:
+    cmp r1, r0, lsl #26
+    subhs   r1, r1,r0, lsl #26
+    addhs   r3, r3,r2, lsl #26
+.L_divide_b26:
+    cmp r1, r0, lsl #25
+    subhs   r1, r1,r0, lsl #25
+    addhs   r3, r3,r2, lsl #25
+.L_divide_b25:
+    cmp r1, r0, lsl #24
+    subhs   r1, r1,r0, lsl #24
+    addhs   r3, r3,r2, lsl #24
+.L_divide_b24:
+    cmp r1, r0, lsl #23
+    subhs   r1, r1,r0, lsl #23
+    addhs   r3, r3,r2, lsl #23
+.L_divide_b23:
+    cmp r1, r0, lsl #22
+    subhs   r1, r1,r0, lsl #22
+    addhs   r3, r3,r2, lsl #22
+.L_divide_b22:
+    cmp r1, r0, lsl #21
+    subhs   r1, r1,r0, lsl #21
+    addhs   r3, r3,r2, lsl #21
+.L_divide_b21:
+    cmp r1, r0, lsl #20
+    subhs   r1, r1,r0, lsl #20
+    addhs   r3, r3,r2, lsl #20
+.L_divide_b20:
+    cmp r1, r0, lsl #19
+    subhs   r1, r1,r0, lsl #19
+    addhs   r3, r3,r2, lsl #19
+.L_divide_b19:
+    cmp r1, r0, lsl #18
+    subhs   r1, r1,r0, lsl #18
+    addhs   r3, r3,r2, lsl #18
+.L_divide_b18:
+    cmp r1, r0, lsl #17
+    subhs   r1, r1,r0, lsl #17
+    addhs   r3, r3,r2, lsl #17
+.L_divide_b17:
+    cmp r1, r0, lsl #16
+    subhs   r1, r1,r0, lsl #16
+    addhs   r3, r3,r2, lsl #16
+.L_divide_b16:
+    cmp r1, r0, lsl #15
+    subhs   r1, r1,r0, lsl #15
+    addhs   r3, r3,r2, lsl #15
+.L_divide_b15:
+    cmp r1, r0, lsl #14
+    subhs   r1, r1,r0, lsl #14
+    addhs   r3, r3,r2, lsl #14
+.L_divide_b14:
+    cmp r1, r0, lsl #13
+    subhs   r1, r1,r0, lsl #13
+    addhs   r3, r3,r2, lsl #13
+.L_divide_b13:
+    cmp r1, r0, lsl #12
+    subhs   r1, r1,r0, lsl #12
+    addhs   r3, r3,r2, lsl #12
+.L_divide_b12:
+    cmp r1, r0, lsl #11
+    subhs   r1, r1,r0, lsl #11
+    addhs   r3, r3,r2, lsl #11
+.L_divide_b11:
+    cmp r1, r0, lsl #10
+    subhs   r1, r1,r0, lsl #10
+    addhs   r3, r3,r2, lsl #10
+.L_divide_b10:
+    cmp r1, r0, lsl #9
+    subhs   r1, r1,r0, lsl #9
+    addhs   r3, r3,r2, lsl #9
+.L_divide_b9:
+    cmp r1, r0, lsl #8
+    subhs   r1, r1,r0, lsl #8
+    addhs   r3, r3,r2, lsl #8
+.L_divide_b8:
+    cmp r1, r0, lsl #7
+    subhs   r1, r1,r0, lsl #7
+    addhs   r3, r3,r2, lsl #7
+.L_divide_b7:
+    cmp r1, r0, lsl #6
+    subhs   r1, r1,r0, lsl #6
+    addhs   r3, r3,r2, lsl #6
+.L_divide_b6:
+    cmp r1, r0, lsl #5
+    subhs   r1, r1,r0, lsl #5
+    addhs   r3, r3,r2, lsl #5
+.L_divide_b5:
+    cmp r1, r0, lsl #4
+    subhs   r1, r1,r0, lsl #4
+    addhs   r3, r3,r2, lsl #4
+.L_divide_b4:
+    cmp r1, r0, lsl #3
+    subhs   r1, r1,r0, lsl #3
+    addhs   r3, r3,r2, lsl #3
+.L_divide_b3:
+    cmp r1, r0, lsl #2
+    subhs   r1, r1,r0, lsl #2
+    addhs   r3, r3,r2, lsl #2
+.L_divide_b2:
+    cmp r1, r0, lsl #1
+    subhs   r1, r1,r0, lsl #1
+    addhs   r3, r3,r2, lsl #1
+.L_divide_b1:
+    cmp r1, r0
+    subhs   r1, r1, r0
+    addhs   r3, r3, r2
+.L_divide_b0:
+
+    tst ip, #0x20000000
+    bne .L_udivide_l1
+    mov r0, r3
+    cmp ip, #0
+    rsbmi   r1, r1, #0
+    movs    ip, ip, lsl #1
+    bicmi   r0, r0, #0x80000000 /* Fix incase we divided 0x80000000 */
+    rsbmi   r0, r0, #0
+    mov pc, lr
+
+.L_udivide_l1:
+    tst ip, #0x10000000
+    mov r1, r1, lsl #1
+    orrne   r1, r1, #1
+    mov r3, r3, lsl #1
+    cmp r1, r0
+    subhs   r1, r1, r0
+    addhs   r3, r3, r2
+    mov r0, r3
+    mov pc, lr

rt-thread/libcpu/arm/common/showmem.c

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2008-07-29     Bernard      first version from QiuYi implementation
+ */
+
+#include <rtthread.h>
+
+void rt_hw_show_memory(rt_uint32_t addr, rt_size_t size)
+{
+    unsigned int i = 0, j = 0;
+
+    RT_ASSERT(addr);
+
+    addr = addr & ~0xF;
+    size = 4 * ((size + 3) / 4);
+
+    while (i < size)
+    {
+        rt_kprintf("0x%08x: ", addr);
+
+        for (j = 0; j < 4; j++)
+        {
+            rt_kprintf("0x%08x  ", *(rt_uint32_t *)addr);
+
+            addr += 4;
+            i++;
+        }
+
+        rt_kprintf("\n");
+    }
+
+    return;
+}

rt-thread/libcpu/arm/cortex-m4/README.md

@@ -0,0 +1,53 @@
+## Independent Interrupts Management
+
+### Introduction
+Calling `rt_hw_interrupt_disable` in multiple places on `rt-thread` may cause interruption delays when the application requires accurate interrupt responses. This is because the system cannot generate any interrupts except abnormal interrupts after disabling interrupts. This is a common problem in the interrupt management of the operating system. The independent interrupt management module is designed to solve this problem.
+
+The independent interrupt management module is designed to solve the problem of interrupt delays caused by calling `rt_hw_interrupt_disable` in multiple places on `rt-thread`. The module is implemented by rewrite the `rt_hw_interrupt_disable` and `rt_hw_interrupt_enable` functions in the `libcpu` library. 
+
+
+### Usage
+- Add the following code to the project's `board.c` file.
+```
+#ifdef RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT
+#define RT_NVIC_PRO_BITS    __NVIC_PRIO_BITS
+
+rt_base_t rt_hw_interrupt_disable(void)
+{
+    rt_base_t level = __get_BASEPRI();
+    __set_BASEPRI(RT_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - RT_NVIC_PRO_BITS));
+
+    __ISB();
+    __DSB();
+
+    return level;
+}
+
+void rt_hw_interrupt_enable(rt_base_t level)
+{
+    __set_BASEPRI(level);
+}
+
+#endif /* RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT */
+```
+- Add the following configuration to the `Kconfig` file in the `board` directory.
+```
+    menuconfig RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT
+        bool "Enable independent interrupt management"
+        default n
+
+        if RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT
+            config RT_MAX_SYSCALL_INTERRUPT_PRIORITY
+                int "Set max syscall interrupt priority"
+                range 0 7
+                default 2
+        endif
+```
+- Select `RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT` to enable this feature.
+- Select `RT_MAX_SYSCALL_INTERRUPT_PRIORITY` to set the maximum priority of the interrupt that can be called by the system call. The default value is 2.
+
+### Description
+- The [basepri](https://developer.arm.com/documentation/107706/0100/Exceptions-and-interrupts-overview/Special-registers-for-exception-masking/BASEPRI) register is used in the functions to complete the interrupt management.
+- For example, if `RT_MAX_SYSCALL_INTERRUPT_PRIORITY` is set to 0x01, the system masking only interrupts with a priority of `0x01-0xFF`.
+- Interrupts with a priority of 0 are not managed by the system and can continue to respond to interrupts after `rt_hw_interrupt_disable` is called.
+- When using the [basepri](https://developer.arm.com/documentation/107706/0100/Exceptions-and-interrupts-overview/Special-registers-for-exception-masking/BASEPRI) register for independent interrupt management, note that interrupts with a priority value lower than `RT_MAX_SYSCALL_INTERRUPT_PRIORITY` cannot call any `system API`.

rt-thread/libcpu/arm/cortex-m4/SConscript

@@ -0,0 +1,26 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM in ['armcc', 'armclang']:
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM == 'armclang':
+    src += Glob('*_rvds.S')
+
+if rtconfig.PLATFORM in ['gcc', 'llvm-arm']:
+    src += Glob('*_init.S')
+    src += Glob('*_gcc.S')
+
+if rtconfig.PLATFORM in ['iccarm']:
+    src += Glob('*_iar.S')
+
+group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

rt-thread/libcpu/arm/cortex-m4/context_gcc.S

@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-10-11     Bernard      first version
+ * 2012-01-01     aozima       support context switch load/store FPU register.
+ * 2013-06-18     aozima       add restore MSP feature.
+ * 2013-06-23     aozima       support lazy stack optimized.
+ * 2018-07-24     aozima       enhancement hard fault exception handler.
+ * 2024-08-13     Evlers       allows rewrite to interrupt enable/disable api to support independent interrupts management
+ */
+
+/**
+ * @addtogroup cortex-m4
+ */
+/*@{*/
+
+.cpu cortex-m4
+.syntax unified
+.thumb
+.text
+
+.equ    SCB_VTOR,           0xE000ED08              /* Vector Table Offset Register */
+.equ    NVIC_INT_CTRL,      0xE000ED04              /* interrupt control state register */
+.equ    NVIC_SYSPRI2,       0xE000ED20              /* system priority register (2) */
+.equ    NVIC_PENDSV_PRI,    0xFFFF0000              /* PendSV and SysTick priority value (lowest) */
+.equ    NVIC_PENDSVSET,     0x10000000              /* value to trigger PendSV exception */
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.global rt_hw_interrupt_disable
+.weak rt_hw_interrupt_disable
+.type rt_hw_interrupt_disable, %function
+rt_hw_interrupt_disable:
+    MRS     r0, PRIMASK
+    CPSID   I
+    BX      LR
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.global rt_hw_interrupt_enable
+.weak rt_hw_interrupt_enable
+.type rt_hw_interrupt_enable, %function
+rt_hw_interrupt_enable:
+    MSR     PRIMASK, r0
+    BX      LR
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+.global rt_hw_context_switch_interrupt
+.type rt_hw_context_switch_interrupt, %function
+.global rt_hw_context_switch
+.type rt_hw_context_switch, %function
+
+rt_hw_context_switch_interrupt:
+rt_hw_context_switch:
+    /* set rt_thread_switch_interrupt_flag to 1 */
+    LDR     r2, =rt_thread_switch_interrupt_flag
+    LDR     r3, [r2]
+    CMP     r3, #1
+    BEQ     _reswitch
+    MOV     r3, #1
+    STR     r3, [r2]
+
+    LDR     r2, =rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
+    STR     r0, [r2]
+
+_reswitch:
+    LDR     r2, =rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
+    STR     r1, [r2]
+
+    LDR r0, =NVIC_INT_CTRL              /* trigger the PendSV exception (causes context switch) */
+    LDR r1, =NVIC_PENDSVSET
+    STR r1, [r0]
+    BX  LR
+
+/* r0 --> switch from thread stack
+ * r1 --> switch to thread stack
+ * psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
+ */
+.global PendSV_Handler
+.type PendSV_Handler, %function
+PendSV_Handler:
+    /* disable interrupt to protect context switch */
+    MRS r2, PRIMASK
+    CPSID   I
+
+    /* get rt_thread_switch_interrupt_flag */
+    LDR r0, =rt_thread_switch_interrupt_flag
+    LDR r1, [r0]
+    CBZ r1, pendsv_exit         /* pendsv already handled */
+
+    /* clear rt_thread_switch_interrupt_flag to 0 */
+    MOV r1, #0x00
+    STR r1, [r0]
+
+    LDR r0, =rt_interrupt_from_thread
+    LDR r1, [r0]
+    CBZ r1, switch_to_thread    /* skip register save at the first time */
+
+    MRS r1, psp                 /* get from thread stack pointer */
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    TST     lr, #0x10           /* if(!EXC_RETURN[4]) */
+    IT      EQ
+    VSTMDBEQ r1!, {d8 - d15}    /* push FPU register s16~s31 */
+#endif
+
+    STMFD   r1!, {r4 - r11}     /* push r4 - r11 register */
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    MOV     r4, #0x00           /* flag = 0 */
+
+    TST     lr, #0x10           /* if(!EXC_RETURN[4]) */
+    IT      EQ
+    MOVEQ   r4, #0x01           /* flag = 1 */
+
+    STMFD   r1!, {r4}           /* push flag */
+#endif
+
+    LDR r0, [r0]
+    STR r1, [r0]                /* update from thread stack pointer */
+
+switch_to_thread:
+    LDR r1, =rt_interrupt_to_thread
+    LDR r1, [r1]
+    LDR r1, [r1]                /* load thread stack pointer */
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    LDMFD   r1!, {r3}           /* pop flag */
+#endif
+
+    LDMFD   r1!, {r4 - r11}     /* pop r4 - r11 register */
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    CMP     r3,  #0             /* if(flag_r3 != 0) */
+    IT      NE
+    VLDMIANE  r1!, {d8 - d15}   /* pop FPU register s16~s31 */
+#endif
+
+    MSR psp, r1                 /* update stack pointer */
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    ORR     lr, lr, #0x10       /* lr |=  (1 << 4), clean FPCA. */
+    CMP     r3,  #0             /* if(flag_r3 != 0) */
+    IT      NE
+    BICNE   lr, lr, #0x10       /* lr &= ~(1 << 4), set FPCA. */
+#endif
+
+pendsv_exit:
+    /* restore interrupt */
+    MSR PRIMASK, r2
+
+    ORR lr, lr, #0x04
+    BX  lr
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+.global rt_hw_context_switch_to
+.type rt_hw_context_switch_to, %function
+rt_hw_context_switch_to:
+    LDR r1, =rt_interrupt_to_thread
+    STR r0, [r1]
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    /* CLEAR CONTROL.FPCA */
+    MRS     r2, CONTROL         /* read */
+    BIC     r2, #0x04           /* modify */
+    MSR     CONTROL, r2         /* write-back */
+#endif
+
+    /* set from thread to 0 */
+    LDR r1, =rt_interrupt_from_thread
+    MOV r0, #0x0
+    STR r0, [r1]
+
+    /* set interrupt flag to 1 */
+    LDR     r1, =rt_thread_switch_interrupt_flag
+    MOV     r0, #1
+    STR     r0, [r1]
+
+    /* set the PendSV and SysTick exception priority */
+    LDR r0, =NVIC_SYSPRI2
+    LDR r1, =NVIC_PENDSV_PRI
+    LDR.W   r2, [r0,#0x00]       /* read       */
+    ORR     r1,r1,r2             /* modify     */
+    STR     r1, [r0]             /* write-back */
+
+    LDR r0, =NVIC_INT_CTRL      /* trigger the PendSV exception (causes context switch) */
+    LDR r1, =NVIC_PENDSVSET
+    STR r1, [r0]
+
+    /* restore MSP */
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
+    /* enable interrupts at processor level */
+    CPSIE   F
+    CPSIE   I
+
+    /* clear the BASEPRI register to disable masking priority */
+    MOV     r0, #0x00
+    MSR     BASEPRI, r0
+
+    /* ensure PendSV exception taken place before subsequent operation */
+    DSB
+    ISB
+
+    /* never reach here! */
+
+/* compatible with old version */
+.global rt_hw_interrupt_thread_switch
+.type rt_hw_interrupt_thread_switch, %function
+rt_hw_interrupt_thread_switch:
+    BX  lr
+    NOP
+
+.global HardFault_Handler
+.type HardFault_Handler, %function
+HardFault_Handler:
+    /* get current context */
+    MRS     r0, msp                 /* get fault context from handler. */
+    TST     lr, #0x04               /* if(!EXC_RETURN[2]) */
+    BEQ     _get_sp_done
+    MRS     r0, psp                 /* get fault context from thread. */
+_get_sp_done:
+
+    STMFD   r0!, {r4 - r11}         /* push r4 - r11 register */
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    STMFD   r0!, {lr}               /* push dummy for flag */
+#endif
+    STMFD   r0!, {lr}               /* push exec_return register */
+
+    TST     lr, #0x04               /* if(!EXC_RETURN[2]) */
+    BEQ     _update_msp
+    MSR     psp, r0                 /* update stack pointer to PSP. */
+    B       _update_done
+_update_msp:
+    MSR     msp, r0                 /* update stack pointer to MSP. */
+_update_done:
+
+    PUSH    {LR}
+    BL      rt_hw_hard_fault_exception
+    POP     {LR}
+
+    ORR     lr, lr, #0x04
+    BX      lr

rt-thread/libcpu/arm/cortex-m4/context_iar.S

@@ -0,0 +1,264 @@
+;/*
+; * Copyright (c) 2006-2018, RT-Thread Development Team
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2009-01-17     Bernard      first version
+; * 2009-09-27     Bernard      add protect when contex switch occurs
+; * 2012-01-01     aozima       support context switch load/store FPU register.
+; * 2013-06-18     aozima       add restore MSP feature.
+; * 2013-06-23     aozima       support lazy stack optimized.
+; * 2018-07-24     aozima       enhancement hard fault exception handler.
+; * 2024-08-13     Evlers       allows rewrite to interrupt enable/disable api to support independent interrupts management
+; */
+
+;/**
+; * @addtogroup cortex-m4
+; */
+;/*@{*/
+
+SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
+NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
+NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
+NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
+
+    SECTION    .text:CODE(2)
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+    IMPORT rt_thread_switch_interrupt_flag
+    IMPORT rt_interrupt_from_thread
+    IMPORT rt_interrupt_to_thread
+
+;/*
+; * rt_base_t rt_hw_interrupt_disable();
+; */
+    PUBWEAK rt_hw_interrupt_disable
+    SECTION .text:CODE:REORDER:NOROOT(2)
+rt_hw_interrupt_disable:
+    MRS     r0, PRIMASK
+    CPSID   I
+    BX      LR
+
+;/*
+; * void rt_hw_interrupt_enable(rt_base_t level);
+; */
+    PUBWEAK  rt_hw_interrupt_enable
+    SECTION .text:CODE:REORDER:NOROOT(2)
+rt_hw_interrupt_enable:
+    MSR     PRIMASK, r0
+    BX      LR
+
+;/*
+; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; * r0 --> from
+; * r1 --> to
+; */
+    EXPORT rt_hw_context_switch_interrupt
+    EXPORT rt_hw_context_switch
+rt_hw_context_switch_interrupt:
+rt_hw_context_switch:
+    ; set rt_thread_switch_interrupt_flag to 1
+    LDR     r2, =rt_thread_switch_interrupt_flag
+    LDR     r3, [r2]
+    CMP     r3, #1
+    BEQ     _reswitch
+    MOV     r3, #1
+    STR     r3, [r2]
+
+    LDR     r2, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
+    STR     r0, [r2]
+
+_reswitch
+    LDR     r2, =rt_interrupt_to_thread     ; set rt_interrupt_to_thread
+    STR     r1, [r2]
+
+    LDR     r0, =NVIC_INT_CTRL              ; trigger the PendSV exception (causes context switch)
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+    BX      LR
+
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
+; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
+    EXPORT PendSV_Handler
+PendSV_Handler:
+
+    ; disable interrupt to protect context switch
+    MRS     r2, PRIMASK
+    CPSID   I
+
+    ; get rt_thread_switch_interrupt_flag
+    LDR     r0, =rt_thread_switch_interrupt_flag
+    LDR     r1, [r0]
+    CBZ     r1, pendsv_exit         ; pendsv already handled
+
+    ; clear rt_thread_switch_interrupt_flag to 0
+    MOV     r1, #0x00
+    STR     r1, [r0]
+
+    LDR     r0, =rt_interrupt_from_thread
+    LDR     r1, [r0]
+    CBZ     r1, switch_to_thread    ; skip register save at the first time
+
+    MRS     r1, psp                 ; get from thread stack pointer
+
+#if defined ( __ARMVFP__ )
+    TST     lr, #0x10               ; if(!EXC_RETURN[4])
+    BNE     skip_push_fpu
+    VSTMDB  r1!, {d8 - d15}         ; push FPU register s16~s31
+skip_push_fpu
+#endif
+
+    STMFD   r1!, {r4 - r11}         ; push r4 - r11 register
+
+#if defined ( __ARMVFP__ )
+    MOV     r4, #0x00               ; flag = 0
+    TST     lr, #0x10               ; if(!EXC_RETURN[4])
+    BNE     push_flag
+    MOV     r4, #0x01               ; flag = 1
+push_flag
+    ;STMFD   r1!, {r4}              ; push flag
+    SUB     r1, r1, #0x04
+    STR     r4, [r1]
+#endif
+
+    LDR     r0, [r0]
+    STR     r1, [r0]                ; update from thread stack pointer
+
+switch_to_thread
+    LDR     r1, =rt_interrupt_to_thread
+    LDR     r1, [r1]
+    LDR     r1, [r1]                ; load thread stack pointer
+
+#if defined ( __ARMVFP__ )
+    LDMFD   r1!, {r3}               ; pop flag
+#endif
+
+    LDMFD   r1!, {r4 - r11}         ; pop r4 - r11 register
+
+#if defined ( __ARMVFP__ )
+    CBZ     r3, skip_pop_fpu
+    VLDMIA  r1!, {d8 - d15}         ; pop FPU register s16~s31
+skip_pop_fpu
+#endif
+
+    MSR     psp, r1                 ; update stack pointer
+
+#if defined ( __ARMVFP__ )
+    ORR     lr, lr, #0x10           ; lr |=  (1 << 4), clean FPCA.
+    CBZ     r3, return_without_fpu  ; if(flag_r3 != 0)
+    BIC     lr, lr, #0x10           ; lr &= ~(1 << 4), set FPCA.
+return_without_fpu
+#endif
+
+pendsv_exit
+    ; restore interrupt
+    MSR     PRIMASK, r2
+
+    ORR     lr, lr, #0x04
+    BX      lr
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; */
+    EXPORT rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    LDR     r1, =rt_interrupt_to_thread
+    STR     r0, [r1]
+
+#if defined ( __ARMVFP__ )
+    ; CLEAR CONTROL.FPCA
+    MRS     r2, CONTROL             ; read
+    BIC     r2, r2, #0x04           ; modify
+    MSR     CONTROL, r2             ; write-back
+#endif
+
+    ; set from thread to 0
+    LDR     r1, =rt_interrupt_from_thread
+    MOV     r0, #0x0
+    STR     r0, [r1]
+
+    ; set interrupt flag to 1
+    LDR     r1, =rt_thread_switch_interrupt_flag
+    MOV     r0, #1
+    STR     r0, [r1]
+
+    ; set the PendSV and SysTick exception priority
+    LDR     r0, =NVIC_SYSPRI2
+    LDR     r1, =NVIC_PENDSV_PRI
+    LDR.W   r2, [r0,#0x00]       ; read
+    ORR     r1,r1,r2             ; modify
+    STR     r1, [r0]             ; write-back
+
+    LDR     r0, =NVIC_INT_CTRL      ; trigger the PendSV exception (causes context switch)
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+
+    ; restore MSP
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    NOP
+    MSR     msp, r0
+
+    ; enable interrupts at processor level
+    CPSIE   F
+    CPSIE   I
+
+    ; clear the BASEPRI register to disable masking priority
+    MOV     r0, #0x00
+    MSR     BASEPRI, r0
+
+    ; ensure PendSV exception taken place before subsequent operation
+    DSB
+    ISB
+
+    ; never reach here!
+
+; compatible with old version
+    EXPORT rt_hw_interrupt_thread_switch
+rt_hw_interrupt_thread_switch:
+    BX      lr
+
+    IMPORT rt_hw_hard_fault_exception
+    EXPORT HardFault_Handler
+HardFault_Handler:
+
+    ; get current context
+    MRS     r0, msp                 ; get fault context from handler.
+    TST     lr, #0x04               ; if(!EXC_RETURN[2])
+    BEQ     _get_sp_done
+    MRS     r0, psp                 ; get fault context from thread.
+_get_sp_done
+
+    STMFD   r0!, {r4 - r11}         ; push r4 - r11 register
+    ;STMFD   r0!, {lr}               ; push exec_return register
+#if defined ( __ARMVFP__ )
+    SUB     r0, r0, #0x04           ; push dummy for flag
+    STR     lr, [r0]
+#endif
+    SUB     r0, r0, #0x04
+    STR     lr, [r0]
+
+    TST     lr, #0x04               ; if(!EXC_RETURN[2])
+    BEQ     _update_msp
+    MSR     psp, r0                 ; update stack pointer to PSP.
+    B       _update_done
+_update_msp
+    MSR     msp, r0                 ; update stack pointer to MSP.
+_update_done
+
+    PUSH    {lr}
+    BL      rt_hw_hard_fault_exception
+    POP     {lr}
+
+    ORR     lr, lr, #0x04
+    BX      lr
+
+    END

rt-thread/libcpu/arm/cortex-m4/context_rvds.S

@@ -0,0 +1,260 @@
+;/*
+;* Copyright (c) 2006-2018, RT-Thread Development Team
+;*
+;* SPDX-License-Identifier: Apache-2.0
+;*
+; * Change Logs:
+; * Date           Author       Notes
+; * 2009-01-17     Bernard      first version.
+; * 2012-01-01     aozima       support context switch load/store FPU register.
+; * 2013-06-18     aozima       add restore MSP feature.
+; * 2013-06-23     aozima       support lazy stack optimized.
+; * 2018-07-24     aozima       enhancement hard fault exception handler.
+; * 2024-08-13     Evlers       allows rewrite to interrupt enable/disable api to support independent interrupts management
+; */
+
+;/**
+; * @addtogroup cortex-m4
+; */
+;/*@{*/
+
+SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
+NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
+NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
+NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
+NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
+
+    AREA |.text|, CODE, READONLY, ALIGN=2
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+    IMPORT rt_thread_switch_interrupt_flag
+    IMPORT rt_interrupt_from_thread
+    IMPORT rt_interrupt_to_thread
+
+;/*
+; * rt_base_t rt_hw_interrupt_disable();
+; */
+rt_hw_interrupt_disable    PROC
+    EXPORT  rt_hw_interrupt_disable [WEAK]
+    MRS     r0, PRIMASK
+    CPSID   I
+    BX      LR
+    ENDP
+
+;/*
+; * void rt_hw_interrupt_enable(rt_base_t level);
+; */
+rt_hw_interrupt_enable    PROC
+    EXPORT  rt_hw_interrupt_enable [WEAK]
+    MSR     PRIMASK, r0
+    BX      LR
+    ENDP
+
+;/*
+; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; * r0 --> from
+; * r1 --> to
+; */
+rt_hw_context_switch_interrupt
+    EXPORT rt_hw_context_switch_interrupt
+rt_hw_context_switch    PROC
+    EXPORT rt_hw_context_switch
+
+    ; set rt_thread_switch_interrupt_flag to 1
+    LDR     r2, =rt_thread_switch_interrupt_flag
+    LDR     r3, [r2]
+    CMP     r3, #1
+    BEQ     _reswitch
+    MOV     r3, #1
+    STR     r3, [r2]
+
+    LDR     r2, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
+    STR     r0, [r2]
+
+_reswitch
+    LDR     r2, =rt_interrupt_to_thread     ; set rt_interrupt_to_thread
+    STR     r1, [r2]
+
+    LDR     r0, =NVIC_INT_CTRL              ; trigger the PendSV exception (causes context switch)
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+    BX      LR
+    ENDP
+
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
+; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
+PendSV_Handler   PROC
+    EXPORT PendSV_Handler
+
+    ; disable interrupt to protect context switch
+    MRS     r2, PRIMASK
+    CPSID   I
+
+    ; get rt_thread_switch_interrupt_flag
+    LDR     r0, =rt_thread_switch_interrupt_flag
+    LDR     r1, [r0]
+    CBZ     r1, pendsv_exit         ; pendsv already handled
+
+    ; clear rt_thread_switch_interrupt_flag to 0
+    MOV     r1, #0x00
+    STR     r1, [r0]
+
+    LDR     r0, =rt_interrupt_from_thread
+    LDR     r1, [r0]
+    CBZ     r1, switch_to_thread    ; skip register save at the first time
+
+    MRS     r1, psp                 ; get from thread stack pointer
+
+    IF      {FPU} != "SoftVFP"
+    TST     lr, #0x10               ; if(!EXC_RETURN[4])
+    VSTMFDEQ  r1!, {d8 - d15}       ; push FPU register s16~s31
+    ENDIF
+
+    STMFD   r1!, {r4 - r11}         ; push r4 - r11 register
+
+    IF      {FPU} != "SoftVFP"
+    MOV     r4, #0x00               ; flag = 0
+
+    TST     lr, #0x10               ; if(!EXC_RETURN[4])
+    MOVEQ   r4, #0x01               ; flag = 1
+
+    STMFD   r1!, {r4}               ; push flag
+    ENDIF
+
+    LDR     r0, [r0]
+    STR     r1, [r0]                ; update from thread stack pointer
+
+switch_to_thread
+    LDR     r1, =rt_interrupt_to_thread
+    LDR     r1, [r1]
+    LDR     r1, [r1]                ; load thread stack pointer
+
+    IF      {FPU} != "SoftVFP"
+    LDMFD   r1!, {r3}               ; pop flag
+    ENDIF
+
+    LDMFD   r1!, {r4 - r11}         ; pop r4 - r11 register
+
+    IF      {FPU} != "SoftVFP"
+    CMP     r3,  #0                 ; if(flag_r3 != 0)
+    VLDMFDNE  r1!, {d8 - d15}       ; pop FPU register s16~s31
+    ENDIF
+
+    MSR     psp, r1                 ; update stack pointer
+
+    IF      {FPU} != "SoftVFP"
+    ORR     lr, lr, #0x10           ; lr |=  (1 << 4), clean FPCA.
+    CMP     r3,  #0                 ; if(flag_r3 != 0)
+    BICNE   lr, lr, #0x10           ; lr &= ~(1 << 4), set FPCA.
+    ENDIF
+
+pendsv_exit
+    ; restore interrupt
+    MSR     PRIMASK, r2
+
+    ORR     lr, lr, #0x04
+    BX      lr
+    ENDP
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; * this fucntion is used to perform the first thread switch
+; */
+rt_hw_context_switch_to    PROC
+    EXPORT rt_hw_context_switch_to
+    ; set to thread
+    LDR     r1, =rt_interrupt_to_thread
+    STR     r0, [r1]
+
+    IF      {FPU} != "SoftVFP"
+    ; CLEAR CONTROL.FPCA
+    MRS     r2, CONTROL             ; read
+    BIC     r2, #0x04               ; modify
+    MSR     CONTROL, r2             ; write-back
+    ENDIF
+
+    ; set from thread to 0
+    LDR     r1, =rt_interrupt_from_thread
+    MOV     r0, #0x0
+    STR     r0, [r1]
+
+    ; set interrupt flag to 1
+    LDR     r1, =rt_thread_switch_interrupt_flag
+    MOV     r0, #1
+    STR     r0, [r1]
+
+    ; set the PendSV and SysTick exception priority
+    LDR     r0, =NVIC_SYSPRI2
+    LDR     r1, =NVIC_PENDSV_PRI
+    LDR.W   r2, [r0,#0x00]       ; read
+    ORR     r1,r1,r2             ; modify
+    STR     r1, [r0]             ; write-back
+
+    ; trigger the PendSV exception (causes context switch)
+    LDR     r0, =NVIC_INT_CTRL
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+
+    ; restore MSP
+    LDR     r0, =SCB_VTOR
+    LDR     r0, [r0]
+    LDR     r0, [r0]
+    MSR     msp, r0
+
+    ; enable interrupts at processor level
+    CPSIE   F
+    CPSIE   I
+
+    ; clear the BASEPRI register to disable masking priority
+    MOV     r0, #0x00
+    MSR     BASEPRI, r0
+
+    ; ensure PendSV exception taken place before subsequent operation
+    DSB
+    ISB
+
+    ; never reach here!
+    ENDP
+
+; compatible with old version
+rt_hw_interrupt_thread_switch PROC
+    EXPORT rt_hw_interrupt_thread_switch
+    BX      lr
+    ENDP
+
+    IMPORT rt_hw_hard_fault_exception
+    EXPORT HardFault_Handler
+HardFault_Handler    PROC
+
+    ; get current context
+    TST     lr, #0x04               ; if(!EXC_RETURN[2])
+    ITE     EQ
+    MRSEQ   r0, msp                 ; [2]=0 ==> Z=1, get fault context from handler.
+    MRSNE   r0, psp                 ; [2]=1 ==> Z=0, get fault context from thread.
+
+    STMFD   r0!, {r4 - r11}         ; push r4 - r11 register
+    IF      {FPU} != "SoftVFP"
+    STMFD   r0!, {lr}               ; push dummy for flag
+    ENDIF
+    STMFD   r0!, {lr}               ; push exec_return register
+
+    TST     lr, #0x04               ; if(!EXC_RETURN[2])
+    ITE     EQ
+    MSREQ   msp, r0                 ; [2]=0 ==> Z=1, update stack pointer to MSP.
+    MSRNE   psp, r0                 ; [2]=1 ==> Z=0, update stack pointer to PSP.
+
+    PUSH    {lr}
+    BL      rt_hw_hard_fault_exception
+    POP     {lr}
+
+    ORR     lr, lr, #0x04
+    BX      lr
+    ENDP
+
+    ALIGN   4
+
+    END

rt-thread/libcpu/arm/cortex-m4/cpuport.c

@@ -0,0 +1,499 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-10-21     Bernard      the first version.
+ * 2011-10-27     aozima       update for cortex-M4 FPU.
+ * 2011-12-31     aozima       fixed stack align issues.
+ * 2012-01-01     aozima       support context switch load/store FPU register.
+ * 2012-12-11     lgnq         fixed the coding style.
+ * 2012-12-23     aozima       stack addr align to 8byte.
+ * 2012-12-29     Bernard      Add exception hook.
+ * 2013-06-23     aozima       support lazy stack optimized.
+ * 2018-07-24     aozima       enhancement hard fault exception handler.
+ * 2019-07-03     yangjie      add __rt_ffs() for armclang.
+ * 2022-06-12     jonas        fixed __rt_ffs() for armclang.
+ */
+
+#include <rtthread.h>
+
+#if               /* ARMCC */ (  (defined ( __CC_ARM ) && defined ( __TARGET_FPU_VFP ))    \
+                  /* Clang */ || (defined ( __clang__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) \
+                  /* IAR */   || (defined ( __ICCARM__ ) && defined ( __ARMVFP__ ))        \
+                  /* GNU */   || (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) )
+#define USE_FPU   1
+#else
+#define USE_FPU   0
+#endif
+
+/* exception and interrupt handler table */
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+/* exception hook */
+static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
+
+struct exception_stack_frame
+{
+    rt_uint32_t r0;
+    rt_uint32_t r1;
+    rt_uint32_t r2;
+    rt_uint32_t r3;
+    rt_uint32_t r12;
+    rt_uint32_t lr;
+    rt_uint32_t pc;
+    rt_uint32_t psr;
+};
+
+struct stack_frame
+{
+#if USE_FPU
+    rt_uint32_t flag;
+#endif /* USE_FPU */
+
+    /* r4 ~ r11 register */
+    rt_uint32_t r4;
+    rt_uint32_t r5;
+    rt_uint32_t r6;
+    rt_uint32_t r7;
+    rt_uint32_t r8;
+    rt_uint32_t r9;
+    rt_uint32_t r10;
+    rt_uint32_t r11;
+
+    struct exception_stack_frame exception_stack_frame;
+};
+
+struct exception_stack_frame_fpu
+{
+    rt_uint32_t r0;
+    rt_uint32_t r1;
+    rt_uint32_t r2;
+    rt_uint32_t r3;
+    rt_uint32_t r12;
+    rt_uint32_t lr;
+    rt_uint32_t pc;
+    rt_uint32_t psr;
+
+#if USE_FPU
+    /* FPU register */
+    rt_uint32_t S0;
+    rt_uint32_t S1;
+    rt_uint32_t S2;
+    rt_uint32_t S3;
+    rt_uint32_t S4;
+    rt_uint32_t S5;
+    rt_uint32_t S6;
+    rt_uint32_t S7;
+    rt_uint32_t S8;
+    rt_uint32_t S9;
+    rt_uint32_t S10;
+    rt_uint32_t S11;
+    rt_uint32_t S12;
+    rt_uint32_t S13;
+    rt_uint32_t S14;
+    rt_uint32_t S15;
+    rt_uint32_t FPSCR;
+    rt_uint32_t NO_NAME;
+#endif
+};
+
+struct stack_frame_fpu
+{
+    rt_uint32_t flag;
+
+    /* r4 ~ r11 register */
+    rt_uint32_t r4;
+    rt_uint32_t r5;
+    rt_uint32_t r6;
+    rt_uint32_t r7;
+    rt_uint32_t r8;
+    rt_uint32_t r9;
+    rt_uint32_t r10;
+    rt_uint32_t r11;
+
+#if USE_FPU
+    /* FPU register s16 ~ s31 */
+    rt_uint32_t s16;
+    rt_uint32_t s17;
+    rt_uint32_t s18;
+    rt_uint32_t s19;
+    rt_uint32_t s20;
+    rt_uint32_t s21;
+    rt_uint32_t s22;
+    rt_uint32_t s23;
+    rt_uint32_t s24;
+    rt_uint32_t s25;
+    rt_uint32_t s26;
+    rt_uint32_t s27;
+    rt_uint32_t s28;
+    rt_uint32_t s29;
+    rt_uint32_t s30;
+    rt_uint32_t s31;
+#endif
+
+    struct exception_stack_frame_fpu exception_stack_frame;
+};
+
+rt_uint8_t *rt_hw_stack_init(void       *tentry,
+                             void       *parameter,
+                             rt_uint8_t *stack_addr,
+                             void       *texit)
+{
+    struct stack_frame *stack_frame;
+    rt_uint8_t         *stk;
+    unsigned long       i;
+
+    stk  = stack_addr + sizeof(rt_uint32_t);
+    stk  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8);
+    stk -= sizeof(struct stack_frame);
+
+    stack_frame = (struct stack_frame *)stk;
+
+    /* init all register */
+    for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++)
+    {
+        ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef;
+    }
+
+    stack_frame->exception_stack_frame.r0  = (unsigned long)parameter; /* r0 : argument */
+    stack_frame->exception_stack_frame.r1  = 0;                        /* r1 */
+    stack_frame->exception_stack_frame.r2  = 0;                        /* r2 */
+    stack_frame->exception_stack_frame.r3  = 0;                        /* r3 */
+    stack_frame->exception_stack_frame.r12 = 0;                        /* r12 */
+    stack_frame->exception_stack_frame.lr  = (unsigned long)texit;     /* lr */
+    stack_frame->exception_stack_frame.pc  = (unsigned long)tentry;    /* entry point, pc */
+    stack_frame->exception_stack_frame.psr = 0x01000000L;              /* PSR */
+
+#if USE_FPU
+    stack_frame->flag = 0;
+#endif /* USE_FPU */
+
+    /* return task's current stack address */
+    return stk;
+}
+
+/**
+ * This function set the hook, which is invoked on fault exception handling.
+ *
+ * @param exception_handle the exception handling hook function.
+ */
+void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
+{
+    rt_exception_hook = exception_handle;
+}
+
+#define SCB_CFSR        (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */
+#define SCB_HFSR        (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
+#define SCB_MMAR        (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
+#define SCB_BFAR        (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
+#define SCB_AIRCR       (*(volatile unsigned long *)0xE000ED0C)  /* Reset control Address Register */
+#define SCB_RESET_VALUE 0x05FA0004                               /* Reset value, write to SCB_AIRCR can reset cpu */
+
+#define SCB_CFSR_MFSR   (*(volatile const unsigned char*)0xE000ED28)  /* Memory-management Fault Status Register */
+#define SCB_CFSR_BFSR   (*(volatile const unsigned char*)0xE000ED29)  /* Bus Fault Status Register */
+#define SCB_CFSR_UFSR   (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */
+
+#ifdef RT_USING_FINSH
+static void usage_fault_track(void)
+{
+    rt_kprintf("usage fault:\n");
+    rt_kprintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR);
+
+    if(SCB_CFSR_UFSR & (1<<0))
+    {
+        /* [0]:UNDEFINSTR */
+        rt_kprintf("UNDEFINSTR ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<1))
+    {
+        /* [1]:INVSTATE */
+        rt_kprintf("INVSTATE ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<2))
+    {
+        /* [2]:INVPC */
+        rt_kprintf("INVPC ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<3))
+    {
+        /* [3]:NOCP */
+        rt_kprintf("NOCP ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<8))
+    {
+        /* [8]:UNALIGNED */
+        rt_kprintf("UNALIGNED ");
+    }
+
+    if(SCB_CFSR_UFSR & (1<<9))
+    {
+        /* [9]:DIVBYZERO */
+        rt_kprintf("DIVBYZERO ");
+    }
+
+    rt_kprintf("\n");
+}
+
+static void bus_fault_track(void)
+{
+    rt_kprintf("bus fault:\n");
+    rt_kprintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR);
+
+    if(SCB_CFSR_BFSR & (1<<0))
+    {
+        /* [0]:IBUSERR */
+        rt_kprintf("IBUSERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<1))
+    {
+        /* [1]:PRECISERR */
+        rt_kprintf("PRECISERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<2))
+    {
+        /* [2]:IMPRECISERR */
+        rt_kprintf("IMPRECISERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<3))
+    {
+        /* [3]:UNSTKERR */
+        rt_kprintf("UNSTKERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<4))
+    {
+        /* [4]:STKERR */
+        rt_kprintf("STKERR ");
+    }
+
+    if(SCB_CFSR_BFSR & (1<<7))
+    {
+        rt_kprintf("SCB->BFAR:%08X\n", SCB_BFAR);
+    }
+    else
+    {
+        rt_kprintf("\n");
+    }
+}
+
+static void mem_manage_fault_track(void)
+{
+    rt_kprintf("mem manage fault:\n");
+    rt_kprintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR);
+
+    if(SCB_CFSR_MFSR & (1<<0))
+    {
+        /* [0]:IACCVIOL */
+        rt_kprintf("IACCVIOL ");
+    }
+
+    if(SCB_CFSR_MFSR & (1<<1))
+    {
+        /* [1]:DACCVIOL */
+        rt_kprintf("DACCVIOL ");
+    }
+
+    if(SCB_CFSR_MFSR & (1<<3))
+    {
+        /* [3]:MUNSTKERR */
+        rt_kprintf("MUNSTKERR ");
+    }
+
+    if(SCB_CFSR_MFSR & (1<<4))
+    {
+        /* [4]:MSTKERR */
+        rt_kprintf("MSTKERR ");
+    }
+
+    if(SCB_CFSR_MFSR & (1<<7))
+    {
+        /* [7]:MMARVALID */
+        rt_kprintf("SCB->MMAR:%08X\n", SCB_MMAR);
+    }
+    else
+    {
+        rt_kprintf("\n");
+    }
+}
+
+static void hard_fault_track(void)
+{
+    if(SCB_HFSR & (1UL<<1))
+    {
+        /* [1]:VECTBL, Indicates hard fault is caused by failed vector fetch. */
+        rt_kprintf("failed vector fetch\n");
+    }
+
+    if(SCB_HFSR & (1UL<<30))
+    {
+        /* [30]:FORCED, Indicates hard fault is taken because of bus fault,
+                        memory management fault, or usage fault. */
+        if(SCB_CFSR_BFSR)
+        {
+            bus_fault_track();
+        }
+
+        if(SCB_CFSR_MFSR)
+        {
+            mem_manage_fault_track();
+        }
+
+        if(SCB_CFSR_UFSR)
+        {
+            usage_fault_track();
+        }
+    }
+
+    if(SCB_HFSR & (1UL<<31))
+    {
+        /* [31]:DEBUGEVT, Indicates hard fault is triggered by debug event. */
+        rt_kprintf("debug event\n");
+    }
+}
+#endif /* RT_USING_FINSH */
+
+struct exception_info
+{
+    rt_uint32_t exc_return;
+    struct stack_frame stack_frame;
+};
+
+void rt_hw_hard_fault_exception(struct exception_info *exception_info)
+{
+#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
+    extern long list_thread(void);
+#endif
+    struct exception_stack_frame *exception_stack = &exception_info->stack_frame.exception_stack_frame;
+    struct stack_frame *context = &exception_info->stack_frame;
+
+    if (rt_exception_hook != RT_NULL)
+    {
+        rt_err_t result;
+
+        result = rt_exception_hook(exception_stack);
+        if (result == RT_EOK) return;
+    }
+
+    rt_kprintf("psr: 0x%08x\n", context->exception_stack_frame.psr);
+
+    rt_kprintf("r00: 0x%08x\n", context->exception_stack_frame.r0);
+    rt_kprintf("r01: 0x%08x\n", context->exception_stack_frame.r1);
+    rt_kprintf("r02: 0x%08x\n", context->exception_stack_frame.r2);
+    rt_kprintf("r03: 0x%08x\n", context->exception_stack_frame.r3);
+    rt_kprintf("r04: 0x%08x\n", context->r4);
+    rt_kprintf("r05: 0x%08x\n", context->r5);
+    rt_kprintf("r06: 0x%08x\n", context->r6);
+    rt_kprintf("r07: 0x%08x\n", context->r7);
+    rt_kprintf("r08: 0x%08x\n", context->r8);
+    rt_kprintf("r09: 0x%08x\n", context->r9);
+    rt_kprintf("r10: 0x%08x\n", context->r10);
+    rt_kprintf("r11: 0x%08x\n", context->r11);
+    rt_kprintf("r12: 0x%08x\n", context->exception_stack_frame.r12);
+    rt_kprintf(" lr: 0x%08x\n", context->exception_stack_frame.lr);
+    rt_kprintf(" pc: 0x%08x\n", context->exception_stack_frame.pc);
+
+    if (exception_info->exc_return & (1 << 2))
+    {
+        rt_kprintf("hard fault on thread: %s\r\n\r\n", rt_thread_self()->parent.name);
+
+#if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
+        list_thread();
+#endif
+    }
+    else
+    {
+        rt_kprintf("hard fault on handler\r\n\r\n");
+    }
+
+    if ( (exception_info->exc_return & 0x10) == 0)
+    {
+        rt_kprintf("FPU active!\r\n");
+    }
+
+#ifdef RT_USING_FINSH
+    hard_fault_track();
+#endif /* RT_USING_FINSH */
+
+    while (1);
+}
+
+/**
+ * reset CPU
+ */
+void rt_hw_cpu_reset(void)
+{
+    SCB_AIRCR = SCB_RESET_VALUE;
+}
+
+#ifdef RT_USING_CPU_FFS
+/**
+ * This function finds the first bit set (beginning with the least significant bit)
+ * in value and return the index of that bit.
+ *
+ * Bits are numbered starting at 1 (the least significant bit).  A return value of
+ * zero from any of these functions means that the argument was zero.
+ *
+ * @return return the index of the first bit set. If value is 0, then this function
+ * shall return 0.
+ */
+#if defined(__CC_ARM)
+__asm int __rt_ffs(int value)
+{
+    CMP     r0, #0x00
+    BEQ     exit
+
+    RBIT    r0, r0
+    CLZ     r0, r0
+    ADDS    r0, r0, #0x01
+
+exit
+    BX      lr
+}
+#elif defined(__clang__)
+int __rt_ffs(int value)
+{
+    __asm volatile(
+        "CMP     %1, #0x00            \n"
+        "BEQ     1f                   \n"
+
+        "RBIT    %1, %1               \n"
+        "CLZ     %0, %1               \n"
+        "ADDS    %0, %0, #0x01        \n"
+
+        "1:                           \n"
+
+        : "=r"(value)
+        : "r"(value)
+    );
+    return value;
+}
+#elif defined(__IAR_SYSTEMS_ICC__)
+int __rt_ffs(int value)
+{
+    if (value == 0) return value;
+
+    asm("RBIT %0, %1" : "=r"(value) : "r"(value));
+    asm("CLZ  %0, %1" : "=r"(value) : "r"(value));
+    asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value));
+
+    return value;
+}
+#elif defined(__GNUC__)
+int __rt_ffs(int value)
+{
+    return __builtin_ffs(value);
+}
+#endif
+
+#endif

rt-thread/libcpu/arm/cortex-m4/cpuport.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+#ifndef  CPUPORT_H__
+#define  CPUPORT_H__
+
+#ifdef RT_USING_SMP
+typedef union {
+    unsigned long slock;
+    struct __arch_tickets {
+        unsigned short owner;
+        unsigned short next;
+    } tickets;
+} rt_hw_spinlock_t;
+#endif
+
+#endif  /*CPUPORT_H__*/