fix sn74lv4052a

apps/boot/boot.uvprojx

@@ -16,7 +16,7 @@
         <TargetCommonOption>
           <Device>STM32F405RGTx</Device>
           <Vendor>STMicroelectronics</Vendor>
-          <PackID>Keil.STM32F4xx_DFP.2.17.1</PackID>
+          <PackID>Keil.STM32F4xx_DFP.3.1.0</PackID>
           <PackURL>https://www.keil.com/pack/</PackURL>
           <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>

apps/chrg/applications/bsp/chrg_clk.c

@@ -10,6 +10,8 @@
 #include <rtdbg.h>
 
 struct chrg_clk_t chrgclk = {
+	.name = TMR_NAME_CLOCK,
+	.timer_fd = RT_NULL,
 	.cnt = 0,
 };
 
@@ -20,26 +22,26 @@ static void chrg_clk_callback (void *args)
 	pCLK->cnt++;
 
 	if (pCLK->cnt % 60 == 0) {
-		rt_kprintf("R : %d mins\r\n", pCLK->cnt/60);
+		//rt_kprintf("R : %d mins\r\n", pCLK->cnt/60);
 	}
 
-	//rt_kprintf("\r\n");
+
 }
 
 static int chrg_clk_init (void)
 {
 	rt_err_t ret = RT_EOK;
-	rt_timer_t timer_fd;
+	struct chrg_clk_t *pCLK = &chrgclk;
 
-	timer_fd = rt_timer_create("clk", chrg_clk_callback, 
-		&chrgclk, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
-	if (timer_fd == RT_NULL) {
-		//rt_kprintf("create clk.\r\n");
+	pCLK->timer_fd = rt_timer_create(pCLK->name, chrg_clk_callback, 
+		pCLK, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
+	if (pCLK->timer_fd == RT_NULL) {
+		LOG_E("create '%s' failed.", pCLK->name);
 		return -1;
 	} else {
-		ret = rt_timer_start(timer_fd);
+		ret = rt_timer_start(pCLK->timer_fd);
 		if (ret != RT_EOK) {
-			rt_kprintf("start clk failed.\r\n");
+			LOG_E("start '%s' failed.", pCLK->name);
 			return ret;
 		}
 	}
@@ -50,3 +52,25 @@ static int chrg_clk_init (void)
 INIT_APP_EXPORT(chrg_clk_init);
 
 
+int uptime (void)
+{
+	struct chrg_clk_t *pCLK = &chrgclk;
+
+	if (pCLK != RT_NULL) {
+		int day = pCLK->cnt/86400;
+		int hour = (pCLK->cnt%86400)/3600;
+		int minute = ((pCLK->cnt%86400)%3600)/60;
+		int second = ((pCLK->cnt%86400)%3600)%60;
+		rt_tick_t tick = rt_tick_get();
+
+		rt_kprintf("up %d days, %02d:%02d:%02d.%03d \r\n", 
+			day, hour, minute, second, tick%1000);
+	}
+
+	return 0;
+}
+
+MSH_CMD_EXPORT(uptime, System running time.);
+
+
+

apps/chrg/applications/bsp/chrg_clk.h

@@ -1,8 +1,11 @@
 #ifndef __CHRG_CLK_H__
 #define __CHRG_CLK_H__
 
+#define TMR_NAME_CLOCK	"tmr.clk"
 
 struct chrg_clk_t {
+	const char		*name;
+	rt_timer_t		timer_fd;
 	rt_uint32_t		cnt;
 	
 };

apps/chrg/applications/bsp/chrg_switch.c

@@ -2,6 +2,15 @@
 
 #include "chrg_switch.h"
 
+
+/* sn74lv4052a
+INH B A CHANNELS
+L L L 1Y0, 2Y0
+L L H 1Y1, 2Y1
+L H L 1Y2, 2Y2
+L H H 1Y3, 2Y3
+H X X None
+*/
 int chrg_switch_ch (rt_base_t inA, rt_base_t inB, eIDX_CH ch)
 {
 	rt_uint8_t a,b;
@@ -13,13 +22,13 @@ int chrg_switch_ch (rt_base_t inA, rt_base_t inB, eIDX_CH ch)
 	break;
 
 	case IDX_CH_1:
-		a = PIN_LOW;
-		b = PIN_HIGH;
+		a = PIN_HIGH;
+		b = PIN_LOW;
 	break;
 
 	case IDX_CH_2:
-		a = PIN_HIGH;
-		b = PIN_LOW;
+		a = PIN_LOW;
+		b = PIN_HIGH;
 	break;
 
 	case IDX_CH_3:

apps/chrg/applications/thread/chrg_north.c

@@ -124,6 +124,7 @@ static int chrg_north_init (void)
 INIT_APP_EXPORT(chrg_north_init);
 
 
+#if 1
 static int north_send(rt_uint8_t argc, char **argv)
 {
 	return chrg_north_send("1234567890abcdef", 16);
@@ -131,6 +132,6 @@ static int north_send(rt_uint8_t argc, char **argv)
 
 
 MSH_CMD_EXPORT(north_send, north send test);
-
+#endif
 
 

apps/chrg/chrg.uvprojx

@@ -16,7 +16,7 @@
         <TargetCommonOption>
           <Device>STM32F405RG</Device>
           <Vendor>STMicroelectronics</Vendor>
-          <PackID>Keil.STM32F4xx_DFP.2.17.1</PackID>
+          <PackID>Keil.STM32F4xx_DFP.3.1.0</PackID>
           <PackURL>https://www.keil.com/pack/</PackURL>
           <Cpu>IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
           <FlashUtilSpec></FlashUtilSpec>