diff --git a/apps/chrg/.config b/apps/chrg/.config index dbb2d03..419b33b 100644 --- a/apps/chrg/.config +++ b/apps/chrg/.config @@ -242,7 +242,12 @@ CONFIG_RT_USING_SERIAL_V1=y CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_SERIAL_BYPASS is not set -# CONFIG_RT_USING_CAN is not set +CONFIG_RT_USING_CAN=y +# CONFIG_RT_CAN_USING_HDR is not set +# CONFIG_RT_CAN_USING_CANFD is not set +CONFIG_RT_CANMSG_BOX_SZ=16 +CONFIG_RT_CANSND_BOX_NUM=1 +CONFIG_RT_CANSND_MSG_TIMEOUT=100 # CONFIG_RT_USING_CPUTIME is not set CONFIG_RT_USING_I2C=y # CONFIG_RT_I2C_DEBUG is not set @@ -1497,7 +1502,8 @@ CONFIG_BSP_USING_I2C1=y CONFIG_BSP_USING_I2C2=y CONFIG_BSP_USING_I2C3=y CONFIG_BSP_USING_I2C4=y -# CONFIG_BSP_USING_CAN is not set +CONFIG_BSP_USING_CAN=y +CONFIG_BSP_USING_CAN1=y # CONFIG_BSP_USING_RNG is not set # CONFIG_BSP_USING_UDID is not set # end of On-chip Peripheral Drivers diff --git a/apps/chrg/applications/chrg_can.c b/apps/chrg/applications/chrg_can.c new file mode 100644 index 0000000..9b2d91b --- /dev/null +++ b/apps/chrg/applications/chrg_can.c @@ -0,0 +1,102 @@ + +#include +#include + +#include "chrg_can.h" + + +struct chrg_can_t chrgcan[TOTAL_CAN] = { + [IDX_CAN_1] = { + .dev = RT_NULL, + .name = DEV_NAME_CAN, + .index = IDX_CAN_1, + } +}; + +static rt_err_t chrg_can1_rx_callback(rt_device_t dev, rt_size_t size) +{ + + rt_sem_release(&chrgcan[IDX_CAN_1].rx_sem); + + return RT_EOK; +} + +static void chrg_can_rx_thread (void *data) +{ + int i = 0; + struct rt_can_msg rxmsg = {0}; + struct chrg_can_t *pCAN = (struct chrg_can_t *)data; + + if (RT_NULL == pCAN) { + return ; + } + + if (IDX_CAN_1 == pCAN->index) { + rt_device_set_rx_indicate(pCAN->dev, chrg_can1_rx_callback); + } else { + return ; + } + + + while (1) { + //rxmsg.hdr = -1; // 直接从 uselist 链表读取数据 + + rt_sem_take(&pCAN->rx_sem, RT_WAITING_FOREVER); + + rt_device_read(pCAN->dev, 0, &rxmsg, sizeof(rxmsg)); + + rt_kprintf("ID : %02x ", rxmsg.id); + for (i = 0; i < 8; i++) { + rt_kprintf("%02X ", rxmsg.data[i]); + } + rt_kprintf("\r\n", rxmsg.id); + } + + +} + + + + +static int chrg_can_init (void) +{ + int i = 0; + rt_err_t ret = 0; + rt_thread_t tid; + + struct chrg_can_t *pCAN = RT_NULL; + + for (i = 0; i < TOTAL_CAN; i++) { + pCAN = &chrgcan[i]; + + pCAN->dev = rt_device_find(pCAN->name); + if (RT_NULL == pCAN->dev) { + rt_kprintf("dev '%s' not found.\r\n", pCAN->name); + + continue; + } + + rt_sem_init(&pCAN->rx_sem, pCAN->name, 0, RT_IPC_FLAG_FIFO); + + ret = rt_device_open(pCAN->dev, RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_INT_RX); + if (RT_EOK != ret) { + rt_kprintf("open '%s' failed.\r\n", pCAN->name); + continue; + } + + tid = rt_thread_create(pCAN->name, chrg_can_rx_thread, pCAN, 1024, 25, 10); + if (tid != RT_NULL) { + rt_thread_startup(tid); + } else { + rt_kprintf("create thread '%s' failed.\r\n", pCAN->name); + return -RT_ERROR; + } + + } + + return RT_EOK; +} + +INIT_APP_EXPORT(chrg_can_init); + + diff --git a/apps/chrg/applications/chrg_can.h b/apps/chrg/applications/chrg_can.h new file mode 100644 index 0000000..14a17ce --- /dev/null +++ b/apps/chrg/applications/chrg_can.h @@ -0,0 +1,28 @@ +#ifndef __CHRG_CAN_H__ +#define __CHRG_CAN_H__ + +#include +#include + +#define DEV_NAME_CAN "can1" + +typedef enum { + IDX_CAN_1 = 0, + + TOTAL_CAN +} eIDX_CAN; + +struct chrg_can_t { + rt_device_t dev; + struct rt_semaphore rx_sem; + + const char *name; + eIDX_CAN index; + +}; + +extern struct chrg_can_t chrgcan[TOTAL_CAN]; + + +#endif + diff --git a/apps/chrg/applications/chrg_i2c.c b/apps/chrg/applications/chrg_i2c.c new file mode 100644 index 0000000..1cc33ba --- /dev/null +++ b/apps/chrg/applications/chrg_i2c.c @@ -0,0 +1,98 @@ +#include +#include + +#include "chrg_i2c.h" + + +struct chrg_i2c_t chrgi2c[TOTAL_I2C] = { + [IDX_I2C_1] = { + .dev = RT_NULL, + .name = DEV_NAME_I2C1, + .slave = SLAVE_PCF8574_ADDR, + .index = IDX_I2C_1, + }, + [IDX_I2C_2] = { + .dev = RT_NULL, + .name = DEV_NAME_I2C2, + .slave = SLAVE_PCF8574_ADDR, + .index = IDX_I2C_2, + }, + [IDX_I2C_3] = { + .dev = RT_NULL, + .name = DEV_NAME_I2C3, + .slave = SLAVE_PCF8574_ADDR, + .index = IDX_I2C_3, + }, + [IDX_I2C_4] = { + .dev = RT_NULL, + .name = DEV_NAME_I2C4, + .slave = SLAVE_PCF8574_ADDR, + .index = IDX_I2C_4, + } +}; + + + + +rt_uint8_t i2c_read_byte(struct chrg_i2c_t *pI2C, rt_uint8_t addr) +{ + rt_uint8_t data = 0; + rt_uint8_t buffer[2] = {0}; + struct rt_i2c_msg msg; + + buffer[0] = addr; + + msg.addr = pI2C->slave; + msg.flags = RT_I2C_WR; + msg.buf = buffer; + msg.len = 1; + rt_i2c_transfer(pI2C->dev, &msg, 1); + + msg.flags = RT_I2C_RD; + msg.buf = &data; + rt_i2c_transfer(pI2C->dev, &msg, 1); + + return data; +} + +rt_err_t i2c_write_byte(struct chrg_i2c_t *pI2C, rt_uint8_t addr, rt_uint8_t data) +{ + rt_uint8_t buffer[2] = {0}; + struct rt_i2c_msg msg; + + buffer[0] = addr; + buffer[1] = data; + + msg.addr = pI2C->slave; + msg.flags = RT_I2C_WR; + msg.buf = buffer; + msg.len = 2; + + if (rt_i2c_transfer(pI2C->dev, &msg, 1) != 1) { + return RT_ERROR; + } + + return RT_EOK; +} + + +static int chrg_i2c_init (void) +{ + struct chrg_i2c_t *pI2C = RT_NULL; + int i = 0; + + for (i = 0; i < TOTAL_I2C; i++) { + pI2C = &chrgi2c[i]; + pI2C->dev = (struct rt_i2c_bus_device *)rt_device_find(pI2C->name); + if (RT_NULL == pI2C->dev) { + rt_kprintf("dev '%s' not found.\r\n", pI2C->name); + continue; + } + } + + return RT_EOK; +} + + +INIT_ENV_EXPORT(chrg_i2c_init); + diff --git a/apps/chrg/applications/chrg_i2c.h b/apps/chrg/applications/chrg_i2c.h new file mode 100644 index 0000000..f3aa668 --- /dev/null +++ b/apps/chrg/applications/chrg_i2c.h @@ -0,0 +1,37 @@ +#ifndef __CHRG_I2C_H__ +#define __CHRG_I2C_H__ + +#include +#include + +#define SLAVE_PCF8574_ADDR 0x40 + +#define DEV_NAME_I2C1 "i2c1" +#define DEV_NAME_I2C2 "i2c2" +#define DEV_NAME_I2C3 "i2c3" +#define DEV_NAME_I2C4 "i2c4" + +typedef enum { + IDX_I2C_1 = 0, + IDX_I2C_2 = 1, + IDX_I2C_3 = 2, + IDX_I2C_4 = 3, + + TOTAL_I2C +} eIDX_I2C; + + +struct chrg_i2c_t { + struct rt_i2c_bus_device *dev; + const char *name; + rt_uint8_t slave; // slave chip addr + eIDX_I2C index; + +}; + +extern struct chrg_i2c_t chrgi2c[TOTAL_I2C]; + + + +#endif + diff --git a/apps/chrg/applications/chrg_tty.c b/apps/chrg/applications/chrg_tty.c new file mode 100644 index 0000000..c42f7e1 --- /dev/null +++ b/apps/chrg/applications/chrg_tty.c @@ -0,0 +1,211 @@ + +#include +#include + +#include "chrg_tty.h" + +struct chrg_tty_t chrgtty[TOTAL_TTY] = { + [IDX_TTY_RS485] = { + .dev = RT_NULL, + .name = DEV_NAME_RS485, + .index = IDX_TTY_RS485, + }, + [IDX_TTY_LCD] = { + .dev = RT_NULL, + .name = DEV_NAME_LCD, + .index = IDX_TTY_LCD, + }, + [IDX_TTY_NORTH] = { + .dev = RT_NULL, + .name = DEV_NAME_NORTH, + .index = IDX_TTY_NORTH, + }, + [IDX_TTY_SOUTH] = { + .dev = RT_NULL, + .name = DEV_NAME_SOUTH, + .index = IDX_TTY_SOUTH, + } +}; + + +static rt_err_t chrg_rs485_tty_input (rt_device_t dev, rt_size_t size) +{ + rt_err_t ret = RT_EOK; + struct chrg_tty_t *pTTY = &chrgtty[IDX_TTY_RS485]; + + pTTY->msg.dev = dev; + pTTY->msg.size = size; + + ret = rt_mq_send(&pTTY->mq_rx, &pTTY->msg, sizeof(struct rx_msg_t)); + if (ret == -RT_EFULL) { + rt_kprintf("msg queue is full!\r\n"); + } + + return ret; +} + +static rt_err_t chrg_lcd_tty_input (rt_device_t dev, rt_size_t size) +{ + rt_err_t ret = RT_EOK; + struct chrg_tty_t *pTTY = &chrgtty[IDX_TTY_LCD]; + + pTTY->msg.dev = dev; + pTTY->msg.size = size; + + ret = rt_mq_send(&pTTY->mq_rx, &pTTY->msg, sizeof(struct rx_msg_t)); + if (ret == -RT_EFULL) { + rt_kprintf("msg queue is full!\r\n"); + } + + return ret; +} + +static rt_err_t chrg_north_tty_input (rt_device_t dev, rt_size_t size) +{ + rt_err_t ret = RT_EOK; + struct chrg_tty_t *pTTY = &chrgtty[IDX_TTY_NORTH]; + + pTTY->msg.dev = dev; + pTTY->msg.size = size; + + ret = rt_mq_send(&pTTY->mq_rx, &pTTY->msg, sizeof(struct rx_msg_t)); + if (ret == -RT_EFULL) { + rt_kprintf("msg queue is full!\r\n"); + } + + return ret; +} + +static rt_err_t chrg_south_tty_input (rt_device_t dev, rt_size_t size) +{ + rt_err_t ret = RT_EOK; + struct chrg_tty_t *pTTY = &chrgtty[IDX_TTY_SOUTH]; + + pTTY->msg.dev = dev; + pTTY->msg.size = size; + + ret = rt_mq_send(&pTTY->mq_rx, &pTTY->msg, sizeof(struct rx_msg_t)); + if (ret == -RT_EFULL) { + rt_kprintf("msg queue is full!\r\n"); + } + + return ret; +} + +static void chrg_tty_recv_entry (void *data) +{ + struct chrg_tty_t *pTTY = (struct chrg_tty_t *)data; + + rt_err_t ret = RT_EOK; + rt_int32_t rx_len = 0; + rt_uint8_t rx_raw[RT_SERIAL_RB_BUFSZ]; + + while (1) { + rt_memset(&pTTY->msg, 0, sizeof(struct rx_msg_t)); + + ret = rt_mq_recv(&pTTY->mq_rx, &pTTY->msg, sizeof(struct rx_msg_t), RT_WAITING_FOREVER); + if (ret == RT_EOK) { + rt_memset(rx_raw, 0, RT_SERIAL_RB_BUFSZ); + rx_len = rt_device_read(pTTY->msg.dev, 0, rx_raw, pTTY->msg.size); + if (rx_len > 0) { + + } + } + + } +} + +rt_err_t chrg_tty_thread (struct chrg_tty_t *pTTY) +{ + rt_err_t ret = RT_EOK; + rt_thread_t tid_tty; + + struct serial_configure cfg = { + .baud_rate = BAUD_RATE_115200, + .data_bits = DATA_BITS_8, + .stop_bits = STOP_BITS_1, + .parity = PARITY_NONE, + .bit_order = BIT_ORDER_LSB, + .invert = NRZ_NORMAL, + .bufsz = RT_SERIAL_RB_BUFSZ, + .flowcontrol = RT_SERIAL_FLOWCONTROL_NONE, + }; + + if (RT_NULL == pTTY->dev) { + rt_kprintf("dev is null.\r\n"); + return RT_ERROR; + } + + rt_mq_init(&pTTY->mq_rx, pTTY->name, pTTY->pool_msg, + sizeof(struct rx_msg_t), sizeof(pTTY->pool_msg), RT_IPC_FLAG_FIFO); + + ret = rt_device_open(pTTY->dev, RT_DEVICE_OFLAG_RDWR|RT_DEVICE_FLAG_INT_RX); + if (ret != RT_EOK) { + rt_kprintf("open '%s' failed.\r\n", pTTY->name); + return ret; + } + + ret = rt_device_control(pTTY->dev, RT_DEVICE_CTRL_CONFIG, &cfg); + if (ret != RT_EOK) { + rt_kprintf("control '%s' failed.\r\n", pTTY->name); + return ret; + } + + switch (pTTY->index) { + case IDX_TTY_RS485: + rt_device_set_rx_indicate(pTTY->dev, chrg_rs485_tty_input); + break; + case IDX_TTY_LCD: + rt_device_set_rx_indicate(pTTY->dev, chrg_lcd_tty_input); + break; + case IDX_TTY_NORTH: + rt_device_set_rx_indicate(pTTY->dev, chrg_north_tty_input); + break; + case IDX_TTY_SOUTH: + rt_device_set_rx_indicate(pTTY->dev, chrg_south_tty_input); + break; + default: + return RT_ERROR; + } + + tid_tty = rt_thread_create(pTTY->name, chrg_tty_recv_entry, + pTTY, 4096, RT_MAIN_THREAD_PRIORITY+2, 20); + + if (tid_tty != RT_NULL) { + rt_thread_startup(tid_tty); + } else { + rt_kprintf("create thread '%s' failed.\r\n", pTTY->name); + return -RT_ERROR; + } + + return RT_EOK; +} + +static int chrg_tty_init (void) +{ + struct chrg_tty_t *pTTY = RT_NULL; + int i = 0; + + for (i = 0; i < TOTAL_TTY; i++) { + if (IDX_TTY_RS485 == i) { + continue; + } + + pTTY = &chrgtty[i]; + + pTTY->dev = rt_device_find(pTTY->name); + if (RT_NULL == pTTY->dev) { + rt_kprintf("dev '%s' not found.\r\n", pTTY->name); + return RT_ERROR; + } + + chrg_tty_thread(pTTY); + } + + return RT_EOK; +} + +INIT_APP_EXPORT(chrg_tty_init); + + + diff --git a/apps/chrg/applications/chrg_tty.h b/apps/chrg/applications/chrg_tty.h new file mode 100644 index 0000000..281ee60 --- /dev/null +++ b/apps/chrg/applications/chrg_tty.h @@ -0,0 +1,43 @@ +#ifndef __CHRG_TTY_H__ +#define __CHRG_TTY_H__ + +#include +#include + +#define DEV_NAME_RS485 "uart1" +#define DEV_NAME_LCD "uart2" +#define DEV_NAME_NORTH "uart3" +#define DEV_NAME_SOUTH "uart6" + +typedef enum { + IDX_TTY_RS485 = 0, + IDX_TTY_LCD = 1, + IDX_TTY_NORTH = 2, + IDX_TTY_SOUTH = 3, + + TOTAL_TTY +} eIDX_TTY; + +struct rx_msg_t { + rt_device_t dev; + rt_size_t size; +}; + +struct chrg_tty_t { + rt_device_t dev; + const char *name; + + eIDX_TTY index; + rt_uint32_t len_rx; + rt_uint8_t buf_rx[RT_SERIAL_RB_BUFSZ]; + + struct rt_messagequeue mq_rx; + struct rx_msg_t msg; + rt_uint8_t pool_msg[1024]; +}; + +extern struct chrg_tty_t chrgtty[TOTAL_TTY]; + + +#endif + diff --git a/apps/chrg/applications/switch_north.c b/apps/chrg/applications/switch_north.c new file mode 100644 index 0000000..af21f94 --- /dev/null +++ b/apps/chrg/applications/switch_north.c @@ -0,0 +1,46 @@ + + +#include "switch_north.h" + +int switch_north_channel(eIDX_SW_NOR idx) +{ + if (idx >= TOTAL_SW_NOR) { + return -1; + } + + switch(idx) { + case IDX_SW_NOR_0: + rt_pin_write(PIN_SW_NORTH_A, PIN_LOW); + rt_pin_write(PIN_SW_NORTH_B, PIN_LOW); + break; + case IDX_SW_NOR_1: + rt_pin_write(PIN_SW_NORTH_A, PIN_LOW); + rt_pin_write(PIN_SW_NORTH_B, PIN_HIGH); + break; + case IDX_SW_NOR_2: + rt_pin_write(PIN_SW_NORTH_A, PIN_HIGH); + rt_pin_write(PIN_SW_NORTH_B, PIN_LOW); + break; + case IDX_SW_NOR_3: + rt_pin_write(PIN_SW_NORTH_A, PIN_HIGH); + rt_pin_write(PIN_SW_NORTH_B, PIN_HIGH); + break; + default: + return -1; + } + + return 0; +} + +static int switch_north_pins_init (void) +{ + rt_pin_mode(PIN_SW_NORTH_A, PIN_MODE_OUTPUT); + rt_pin_mode(PIN_SW_NORTH_B, PIN_MODE_OUTPUT); + + return 0; +} + +INIT_ENV_EXPORT(switch_north_pins_init); + + + diff --git a/apps/chrg/applications/switch_north.h b/apps/chrg/applications/switch_north.h new file mode 100644 index 0000000..fc7cf93 --- /dev/null +++ b/apps/chrg/applications/switch_north.h @@ -0,0 +1,22 @@ +#ifndef __SWITCH_NORTH_H__ +#define __SWITCH_NORTH_H__ + +#include "drv_gpio.h" + +// U14 switch +#define PIN_SW_NORTH_A GET_PIN(B, 0) +#define PIN_SW_NORTH_B GET_PIN(B, 1) + +typedef enum { + IDX_SW_NOR_0 = 0, // to J3 + IDX_SW_NOR_1 = 1, // to J4 + IDX_SW_NOR_2 = 2, // to J9 + IDX_SW_NOR_3 = 3, // to J10 + + TOTAL_SW_NOR +} eIDX_SW_NOR; + + +#endif + + diff --git a/apps/chrg/applications/switch_south.c b/apps/chrg/applications/switch_south.c new file mode 100644 index 0000000..fb17b4c --- /dev/null +++ b/apps/chrg/applications/switch_south.c @@ -0,0 +1,101 @@ + + +#include "switch_south.h" + +int switch_south_lv1_channel(eIDX_SW_SOU_LV1 idx) +{ + if (idx >= TOTAL_SW_SOU_LV1) { + return -1; + } + + switch(idx) { + case IDX_SW_SOU_LV1_0: + rt_pin_write(PIN_SW_SOUTH_LV1_A, PIN_LOW); + rt_pin_write(PIN_SW_SOUTH_LV1_B, PIN_LOW); + break; + case IDX_SW_SOU_LV1_1: + rt_pin_write(PIN_SW_SOUTH_LV1_A, PIN_LOW); + rt_pin_write(PIN_SW_SOUTH_LV1_B, PIN_HIGH); + break; + default: + return -1; + } + + return 0; +} + +int switch_south_lv2_1_channel(eIDX_SW_SOU_LV2_1 idx) +{ + if (idx >= TOTAL_SW_SOU_LV2_1) { + return -1; + } + + switch(idx) { + case IDX_SW_SOU_LV2_1_0: + rt_pin_write(PIN_SW_SOUTH_LV2_A1, PIN_LOW); + rt_pin_write(PIN_SW_SOUTH_LV2_B1, PIN_LOW); + break; + case IDX_SW_SOU_LV2_1_1: + rt_pin_write(PIN_SW_SOUTH_LV2_A1, PIN_LOW); + rt_pin_write(PIN_SW_SOUTH_LV2_B1, PIN_HIGH); + break; + case IDX_SW_SOU_LV2_1_2: + rt_pin_write(PIN_SW_SOUTH_LV2_A1, PIN_HIGH); + rt_pin_write(PIN_SW_SOUTH_LV2_B1, PIN_LOW); + break; + case IDX_SW_SOU_LV2_1_3: + rt_pin_write(PIN_SW_SOUTH_LV2_A1, PIN_HIGH); + rt_pin_write(PIN_SW_SOUTH_LV2_B1, PIN_HIGH); + break; + default: + return -1; + } + + return 0; +} + +int switch_south_lv2_2_channel(eIDX_SW_SOU_LV2_2 idx) +{ + if (idx >= TOTAL_SW_SOU_LV2_2) { + return -1; + } + + switch(idx) { + case IDX_SW_SOU_LV2_2_0: + rt_pin_write(PIN_SW_SOUTH_LV2_A2, PIN_LOW); + rt_pin_write(PIN_SW_SOUTH_LV2_B2, PIN_LOW); + break; + case IDX_SW_SOU_LV2_2_1: + rt_pin_write(PIN_SW_SOUTH_LV2_A2, PIN_LOW); + rt_pin_write(PIN_SW_SOUTH_LV2_B2, PIN_HIGH); + break; + case IDX_SW_SOU_LV2_2_2: + rt_pin_write(PIN_SW_SOUTH_LV2_A2, PIN_HIGH); + rt_pin_write(PIN_SW_SOUTH_LV2_B2, PIN_LOW); + break; + case IDX_SW_SOU_LV2_2_3: + rt_pin_write(PIN_SW_SOUTH_LV2_A2, PIN_HIGH); + rt_pin_write(PIN_SW_SOUTH_LV2_B2, PIN_HIGH); + break; + default: + return -1; + } + + return 0; +} + +static int switch_south_pins_init (void) +{ + rt_pin_mode(PIN_SW_SOUTH_LV1_A, PIN_MODE_OUTPUT); + rt_pin_mode(PIN_SW_SOUTH_LV1_B, PIN_MODE_OUTPUT); + rt_pin_mode(PIN_SW_SOUTH_LV2_A1, PIN_MODE_OUTPUT); + rt_pin_mode(PIN_SW_SOUTH_LV2_B1, PIN_MODE_OUTPUT); + rt_pin_mode(PIN_SW_SOUTH_LV2_A2, PIN_MODE_OUTPUT); + rt_pin_mode(PIN_SW_SOUTH_LV2_B2, PIN_MODE_OUTPUT); + + return 0; +} + +INIT_ENV_EXPORT(switch_south_pins_init); + + diff --git a/apps/chrg/applications/switch_south.h b/apps/chrg/applications/switch_south.h new file mode 100644 index 0000000..b440ca2 --- /dev/null +++ b/apps/chrg/applications/switch_south.h @@ -0,0 +1,49 @@ +#ifndef __SWITCH_SOUTH_H__ +#define __SWITCH_SOUTH_H__ + +#include "drv_gpio.h" + +// U23 switch +#define PIN_SW_SOUTH_LV1_A GET_PIN(C, 8) +#define PIN_SW_SOUTH_LV1_B GET_PIN(C, 9) + +typedef enum { + IDX_SW_SOU_LV1_0 = 0, // to U24 + IDX_SW_SOU_LV1_1 = 1, // to U25 + + TOTAL_SW_SOU_LV1 +} eIDX_SW_SOU_LV1; + +// U24 switch +#define PIN_SW_SOUTH_LV2_A1 GET_PIN(A, 15) +#define PIN_SW_SOUTH_LV2_B1 GET_PIN(C, 10) + +typedef enum { + IDX_SW_SOU_LV2_1_0 = 0, // to J12 + IDX_SW_SOU_LV2_1_1 = 1, // to J13 + IDX_SW_SOU_LV2_1_2 = 2, // to J14 + IDX_SW_SOU_LV2_1_3 = 3, // to J15 + + TOTAL_SW_SOU_LV2_1 +} eIDX_SW_SOU_LV2_1; + +// U25 switch +#define PIN_SW_SOUTH_LV2_A2 GET_PIN(C, 11) +#define PIN_SW_SOUTH_LV2_B2 GET_PIN(C, 12) + +typedef enum { + IDX_SW_SOU_LV2_2_0 = 0, // to J16 + IDX_SW_SOU_LV2_2_1 = 1, // to J17 + IDX_SW_SOU_LV2_2_2 = 2, // to J18 + IDX_SW_SOU_LV2_2_3 = 3, // to J19 + + TOTAL_SW_SOU_LV2_2 +} eIDX_SW_SOU_LV2_2; + + + + + +#endif + + diff --git a/apps/chrg/applications/tmr_clk.c b/apps/chrg/applications/tmr_clk.c index 4ce17ad..8829044 100644 --- a/apps/chrg/applications/tmr_clk.c +++ b/apps/chrg/applications/tmr_clk.c @@ -30,12 +30,12 @@ static int tmr_clk_init (void) timer_fd = rt_timer_create("tmr_clk", tmr_clk_callback, &tmrclk, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC); if (timer_fd == RT_NULL) { - //LOG_E("create tmr_clk"); + //rt_kprintf("create tmr_clk.\r\n"); return -1; } else { ret = rt_timer_start(timer_fd); if (ret != RT_EOK) { - //LOG_E("start tmr_clk"); + rt_kprintf("start tmr_clk failed.\r\n"); return ret; } } diff --git a/apps/chrg/applications/tmr_pin.c b/apps/chrg/applications/tmr_pin.c index a3f684c..0b66c2c 100644 --- a/apps/chrg/applications/tmr_pin.c +++ b/apps/chrg/applications/tmr_pin.c @@ -165,7 +165,7 @@ static rt_int32_t tmr_pin_timer_start (ePIN_IDX index) pPIN, pPIN->tmr_millis_on, RT_TIMER_FLAG_ONE_SHOT); if (pPIN->tmr_fd == RT_NULL) { - //LOG_E("tmr '%s'", pPIN->tmr_name); + rt_kprintf("tmr create '%s' failed.\r\n", pPIN->tmr_name); return -1; } @@ -227,8 +227,6 @@ static int tmr_pins_init (void) rt_pin_write(pPIN->pin_base, pPIN->pin_value); } - //LOG_I("I : set '%s'(%d) mode %d", pPIN->pin_name, pPIN->pin_base, pPIN->pin_mode); - tmr_pin_timer_start((ePIN_IDX)i); } diff --git a/apps/chrg/applications/usart2.c b/apps/chrg/applications/usart2.c deleted file mode 100644 index 794e7f5..0000000 --- a/apps/chrg/applications/usart2.c +++ /dev/null @@ -1,49 +0,0 @@ -#include -#include - -static rt_device_t serial_usart2; - -rt_err_t usart2_rx_irq(rt_device_t dev, rt_size_t size) -{ - rt_kprintf("rx_irq\r\n"); - - return RT_EOK; -} - -static int usart2_open(void) -{ - rt_err_t ret; - - serial_usart2 = rt_device_find("uart2"); - if (RT_NULL == serial_usart2) { - rt_kprintf("can't find usart2.\r\n"); - return RT_ERROR; - } - - ret = rt_device_open(serial_usart2, RT_DEVICE_OFLAG_RDWR|RT_DEVICE_FLAG_INT_RX); - if (RT_EOK != ret) { - rt_kprintf("open usart2 failed.\r\n"); - return RT_ERROR; - } - - struct serial_configure uart2_set_parg={ \ - BAUD_RATE_115200, /* 115200 bits/s */ \ - DATA_BITS_8, /* 8 databits */ \ - STOP_BITS_1, /* 1 stopbit */ \ - PARITY_NONE, /* No parity */ \ - BIT_ORDER_LSB, /* LSB first sent */ \ - NRZ_NORMAL, /* Normal mode */ \ - RT_SERIAL_RB_BUFSZ, /* Buffer size */ \ - 0 \ - }; - - rt_device_control(serial_usart2, RT_DEVICE_CTRL_CONFIG, &uart2_set_parg); - - rt_device_set_rx_indicate(serial_usart2, usart2_rx_irq); - - return RT_EOK; -} - -INIT_APP_EXPORT(usart2_open); - - diff --git a/apps/chrg/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h b/apps/chrg/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h index 15f9b6a..93b1074 100644 --- a/apps/chrg/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h +++ b/apps/chrg/board/CubeMX_Config/Inc/stm32f4xx_hal_conf.h @@ -51,7 +51,7 @@ /* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_CAN_MODULE_ENABLED */ +#define HAL_CAN_MODULE_ENABLED /* #define HAL_CRC_MODULE_ENABLED */ /* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_DAC_MODULE_ENABLED */ diff --git a/apps/chrg/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c b/apps/chrg/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c index 1c68c34..3f63ddb 100644 --- a/apps/chrg/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c +++ b/apps/chrg/board/CubeMX_Config/Src/stm32f4xx_hal_msp.c @@ -79,21 +79,28 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF7_USART3; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - } else if(huart->Instance==UART4) { + } else if(huart->Instance==UART5) { /* Peripheral clock enable */ - __HAL_RCC_UART4_CLK_ENABLE(); + __HAL_RCC_UART5_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); - /**UART2 GPIO Configuration - PC10 ------> UART4_TX - PC11 ------> UART4_RX + /**UART5 GPIO Configuration + PC12 ------> UART5_TX + PD2 ------> UART5_RX */ - GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; + GPIO_InitStruct.Pin = GPIO_PIN_12; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF8_UART4; + GPIO_InitStruct.Alternate = GPIO_AF8_UART5; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_UART5; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); } else if(huart->Instance==USART6) { /* Peripheral clock enable */ __HAL_RCC_USART6_CLK_ENABLE(); @@ -151,15 +158,16 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) PB11 ------> USART3_RX */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11); - } else if(huart->Instance==UART4) { + } else if(huart->Instance==UART5) { /* Peripheral clock disable */ - __HAL_RCC_UART4_CLK_DISABLE(); + __HAL_RCC_UART5_CLK_DISABLE(); - /**UART4 GPIO Configuration - PC10 ------> UART4_TX - PC11 ------> UART4_RX + /**UART5 GPIO Configuration + PC12 ------> UART5_TX + PD2 ------> UART5_RX */ - HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11); + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12); + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); } else if(huart->Instance==USART6) { /* Peripheral clock disable */ __HAL_RCC_USART6_CLK_DISABLE(); @@ -174,8 +182,55 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) } -/* USER CODE BEGIN 1 */ +/** +* @brief CAN MSP Initialization +* This function configures the hardware resources used in this example +* @param hcan: CAN handle pointer +* @retval None +*/ +void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hcan->Instance==CAN1) { + /* Peripheral clock enable */ + __HAL_RCC_CAN1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**CAN1 GPIO Configuration + PA11 ------> CAN1_RX + PA12 ------> CAN1_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_CAN1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + } + +} + +/** +* @brief CAN MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hcan: CAN handle pointer +* @retval None +*/ +void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +{ + if(hcan->Instance==CAN1){ + /* Peripheral clock disable */ + __HAL_RCC_CAN1_CLK_DISABLE(); + + /**CAN1 GPIO Configuration + PA11 ------> CAN1_RX + PA12 ------> CAN1_TX + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); + } + +} + + -/* USER CODE END 1 */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/apps/chrg/project.uvprojx b/apps/chrg/project.uvprojx index aee827b..5842e97 100644 --- a/apps/chrg/project.uvprojx +++ b/apps/chrg/project.uvprojx @@ -337,9 +337,9 @@ 0 - RT_USING_ARMLIBC, RT_USING_LIBC, __RTTHREAD__, __STDC_LIMIT_MACROS, __CLK_TCK=RT_TICK_PER_SECOND, STM32F405xx, USE_HAL_DRIVER + USE_HAL_DRIVER, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_ARMLIBC, STM32F405xx, RT_USING_LIBC, __RTTHREAD__, __STDC_LIMIT_MACROS - ..\..\libs\freemodbus\modbus\include;..\..\rt-thread\include;..\..\rt-thread\components\libc\posix\ipc;..\..\rt-thread\components\drivers\include;..\..\libs\freemodbus\modbus\tcp;..\..\rt-thread\bsp\stm32\libraries\HAL_Drivers;..\..\rt-thread\components\drivers\smp_call;..\..\libs\stm32f4\STM32F4_HAL\Inc;..\..\rt-thread\components\libc\compilers\common\include;..\..\libs\freemodbus\modbus\rtu;..\..\rt-thread\bsp\stm32\libraries\HAL_Drivers\drivers\config;..\..\rt-thread\components\drivers\include;..\..\rt-thread\components\drivers\include;..\..\rt-thread\components\drivers\include;..\..\rt-thread\libcpu\arm\common;..\..\libs\stm32f4\STM32F4_HAL\Inc\Legacy;board;..\..\rt-thread\components\libc\posix\io\eventfd;.;..\..\rt-thread\bsp\stm32\libraries\HAL_Drivers\drivers;..\..\rt-thread\components\libc\compilers\common\extension\fcntl\octal;..\..\rt-thread\components\drivers\include;..\..\libs\freemodbus\modbus\ascii;..\..\rt-thread\components\libc\posix\io\epoll;..\..\rt-thread\components\drivers\include;..\..\rt-thread\components\libc\compilers\common\extension;..\..\rt-thread\components\drivers\phy;board\CubeMX_Config\Inc;..\..\libs\stm32f4\STM32F4_CMSIS\Include;..\..\rt-thread\libcpu\arm\cortex-m4;..\..\libs\cmsis-core\Include;..\..\rt-thread\components\finsh;applications;..\..\rt-thread\components\libc\posix\io\poll;..\..\libs\freemodbus\port + ..\..\rt-thread\components\drivers\include;.;..\..\libs\freemodbus\modbus\include;..\..\rt-thread\bsp\stm32\libraries\HAL_Drivers;..\..\rt-thread\components\drivers\include;..\..\rt-thread\bsp\stm32\libraries\HAL_Drivers\drivers;..\..\rt-thread\components\drivers\include;..\..\rt-thread\components\libc\posix\ipc;..\..\rt-thread\include;..\..\rt-thread\components\finsh;..\..\rt-thread\components\libc\posix\io\epoll;..\..\rt-thread\components\libc\compilers\common\extension\fcntl\octal;..\..\rt-thread\libcpu\arm\cortex-m4;board\CubeMX_Config\Inc;..\..\rt-thread\components\drivers\include;..\..\libs\freemodbus\modbus\tcp;..\..\libs\stm32f4\STM32F4_HAL\Inc\Legacy;..\..\libs\freemodbus\modbus\ascii;..\..\libs\stm32f4\STM32F4_CMSIS\Include;..\..\rt-thread\components\drivers\smp_call;..\..\rt-thread\components\libc\posix\io\poll;..\..\rt-thread\components\libc\compilers\common\extension;..\..\rt-thread\components\drivers\include;..\..\libs\freemodbus\modbus\rtu;..\..\rt-thread\components\drivers\phy;..\..\rt-thread\bsp\stm32\libraries\HAL_Drivers\drivers\config;..\..\rt-thread\components\libc\compilers\common\include;..\..\libs\freemodbus\port;..\..\libs\cmsis-core\Include;..\..\rt-thread\components\drivers\include;..\..\rt-thread\components\drivers\include;..\..\rt-thread\components\libc\posix\io\eventfd;..\..\libs\stm32f4\STM32F4_HAL\Inc;applications;..\..\rt-thread\libcpu\arm\common;board @@ -393,16 +393,36 @@ 1 applications\tmr_clk.c - - usart2.c - 1 - applications\usart2.c - main.c 1 applications\main.c + + chrg_i2c.c + 1 + applications\chrg_i2c.c + + + switch_north.c + 1 + applications\switch_north.c + + + switch_south.c + 1 + applications\switch_south.c + + + chrg_tty.c + 1 + applications\chrg_tty.c + + + chrg_can.c + 1 + applications\chrg_can.c + @@ -453,6 +473,62 @@ DeviceDrivers + + dev_can.c + 1 + ..\..\rt-thread\components\drivers\can\dev_can.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + device.c 1 @@ -1308,6 +1384,11 @@ 1 board\board.c + + drv_can.c + 1 + ..\..\rt-thread\bsp\stm32\libraries\HAL_Drivers\drivers\drv_can.c + drv_gpio.c 1 @@ -1359,14 +1440,24 @@ FreeModbus - mbfuncholding.c + mbfuncdiag.c 1 - ..\..\libs\freemodbus\modbus\functions\mbfuncholding.c + ..\..\libs\freemodbus\modbus\functions\mbfuncdiag.c - sample_mb_slave.c + mbrtu.c 1 - ..\..\libs\freemodbus\samples\sample_mb_slave.c + ..\..\libs\freemodbus\modbus\rtu\mbrtu.c + + + mbfuncholding_m.c + 1 + ..\..\libs\freemodbus\modbus\functions\mbfuncholding_m.c + + + portevent_m.c + 1 + ..\..\libs\freemodbus\port\portevent_m.c mbfuncinput.c @@ -1374,9 +1465,9 @@ ..\..\libs\freemodbus\modbus\functions\mbfuncinput.c - portserial.c + mbfuncinput_m.c 1 - ..\..\libs\freemodbus\port\portserial.c + ..\..\libs\freemodbus\modbus\functions\mbfuncinput_m.c porttcp.c @@ -1389,9 +1480,9 @@ ..\..\libs\freemodbus\modbus\rtu\mbrtu_m.c - port.c + portserial.c 1 - ..\..\libs\freemodbus\port\port.c + ..\..\libs\freemodbus\port\portserial.c user_mb_app_m.c @@ -1399,24 +1490,44 @@ ..\..\libs\freemodbus\port\user_mb_app_m.c - sample_mb_master.c + mbfunccoils.c 1 - ..\..\libs\freemodbus\samples\sample_mb_master.c + ..\..\libs\freemodbus\modbus\functions\mbfunccoils.c - mbfuncholding_m.c + porttimer_m.c 1 - ..\..\libs\freemodbus\modbus\functions\mbfuncholding_m.c + ..\..\libs\freemodbus\port\porttimer_m.c - mbrtu.c + mbfuncother.c 1 - ..\..\libs\freemodbus\modbus\rtu\mbrtu.c + ..\..\libs\freemodbus\modbus\functions\mbfuncother.c - mbfuncinput_m.c + mbfuncdisc_m.c 1 - ..\..\libs\freemodbus\modbus\functions\mbfuncinput_m.c + ..\..\libs\freemodbus\modbus\functions\mbfuncdisc_m.c + + + port.c + 1 + ..\..\libs\freemodbus\port\port.c + + + portserial_m.c + 1 + ..\..\libs\freemodbus\port\portserial_m.c + + + mbfuncholding.c + 1 + ..\..\libs\freemodbus\modbus\functions\mbfuncholding.c + + + mbfunccoils_m.c + 1 + ..\..\libs\freemodbus\modbus\functions\mbfunccoils_m.c mb.c @@ -1429,24 +1540,9 @@ ..\..\libs\freemodbus\modbus\functions\mbfuncdisc.c - mbfunccoils_m.c + mbcrc.c 1 - ..\..\libs\freemodbus\modbus\functions\mbfunccoils_m.c - - - mbfuncdisc_m.c - 1 - ..\..\libs\freemodbus\modbus\functions\mbfuncdisc_m.c - - - porttimer_m.c - 1 - ..\..\libs\freemodbus\port\porttimer_m.c - - - mbutils.c - 1 - ..\..\libs\freemodbus\modbus\functions\mbutils.c + ..\..\libs\freemodbus\modbus\rtu\mbcrc.c porttimer.c @@ -1454,50 +1550,35 @@ ..\..\libs\freemodbus\port\porttimer.c - portserial_m.c + mb_m.c 1 - ..\..\libs\freemodbus\port\portserial_m.c - - - mbfunccoils.c - 1 - ..\..\libs\freemodbus\modbus\functions\mbfunccoils.c - - - mbfuncother.c - 1 - ..\..\libs\freemodbus\modbus\functions\mbfuncother.c - - - mbcrc.c - 1 - ..\..\libs\freemodbus\modbus\rtu\mbcrc.c - - - mbfuncdiag.c - 1 - ..\..\libs\freemodbus\modbus\functions\mbfuncdiag.c + ..\..\libs\freemodbus\modbus\mb_m.c user_mb_app.c 1 ..\..\libs\freemodbus\port\user_mb_app.c + + sample_mb_slave.c + 1 + ..\..\libs\freemodbus\samples\sample_mb_slave.c + + + sample_mb_master.c + 1 + ..\..\libs\freemodbus\samples\sample_mb_master.c + + + mbutils.c + 1 + ..\..\libs\freemodbus\modbus\functions\mbutils.c + portevent.c 1 ..\..\libs\freemodbus\port\portevent.c - - mb_m.c - 1 - ..\..\libs\freemodbus\modbus\mb_m.c - - - portevent_m.c - 1 - ..\..\libs\freemodbus\port\portevent_m.c - @@ -2349,14 +2430,9 @@ klibc - kerrno.c + kstring.c 1 - ..\..\rt-thread\src\klibc\kerrno.c - - - rt_vsscanf.c - 1 - ..\..\rt-thread\src\klibc\rt_vsscanf.c + ..\..\rt-thread\src\klibc\kstring.c kstdio.c @@ -2369,9 +2445,14 @@ ..\..\rt-thread\src\klibc\rt_vsnprintf_tiny.c - kstring.c + rt_vsscanf.c 1 - ..\..\rt-thread\src\klibc\kstring.c + ..\..\rt-thread\src\klibc\rt_vsscanf.c + + + kerrno.c + 1 + ..\..\rt-thread\src\klibc\kerrno.c @@ -2408,85 +2489,50 @@ STM32F4-CMSIS - - startup_stm32f405xx.s - 2 - ..\..\libs\stm32f4\STM32F4_CMSIS\Source\Templates\arm\startup_stm32f405xx.s - system_stm32f4xx.c 1 ..\..\libs\stm32f4\STM32F4_CMSIS\Source\Templates\system_stm32f4xx.c + + startup_stm32f405xx.s + 2 + ..\..\libs\stm32f4\STM32F4_CMSIS\Source\Templates\arm\startup_stm32f405xx.s + STM32F4-HAL - stm32f4xx_hal_crc.c + stm32f4xx_hal_can.c 1 - ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_crc.c - - - stm32f4xx_hal_i2c_ex.c - 1 - ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_i2c_ex.c - - - stm32f4xx_hal_cortex.c - 1 - ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_cortex.c - - - stm32f4xx_hal_i2c.c - 1 - ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_i2c.c - - - stm32f4xx_hal_gpio.c - 1 - ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_gpio.c - - - stm32f4xx_hal_pwr_ex.c - 1 - ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_pwr_ex.c - - - stm32f4xx_hal_dma.c - 1 - ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_dma.c + ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_can.c stm32f4xx_hal_rcc_ex.c 1 ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_rcc_ex.c + + stm32f4xx_hal_usart.c + 1 + ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_usart.c + + + stm32f4xx_hal_gpio.c + 1 + ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_gpio.c + stm32f4xx_hal_pwr.c 1 ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_pwr.c - stm32f4xx_hal_rng.c + stm32f4xx_hal_cortex.c 1 - ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_rng.c - - - stm32f4xx_hal_uart.c - 1 - ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_uart.c - - - stm32f4xx_hal_rcc.c - 1 - ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_rcc.c - - - stm32f4xx_hal_usart.c - 1 - ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_usart.c + ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_cortex.c stm32f4xx_hal_dma_ex.c @@ -2494,14 +2540,34 @@ ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_dma_ex.c - stm32f4xx_hal.c + stm32f4xx_hal_pwr_ex.c 1 - ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal.c + ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_pwr_ex.c - stm32f4xx_hal_cec.c + stm32f4xx_hal_rng.c 1 - ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_cec.c + ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_rng.c + + + stm32f4xx_hal_i2c_ex.c + 1 + ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_i2c_ex.c + + + stm32f4xx_hal_uart.c + 1 + ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_uart.c + + + stm32f4xx_hal_dma.c + 1 + ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_dma.c + + + stm32f4xx_hal_i2c.c + 1 + ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_i2c.c stm32f4xx_hal_cryp_ex.c @@ -2513,6 +2579,26 @@ 1 ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_cryp.c + + stm32f4xx_hal_crc.c + 1 + ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_crc.c + + + stm32f4xx_hal_cec.c + 1 + ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_cec.c + + + stm32f4xx_hal.c + 1 + ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal.c + + + stm32f4xx_hal_rcc.c + 1 + ..\..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_rcc.c + diff --git a/apps/chrg/rtconfig.h b/apps/chrg/rtconfig.h index 4018b14..d5df29f 100644 --- a/apps/chrg/rtconfig.h +++ b/apps/chrg/rtconfig.h @@ -149,6 +149,10 @@ #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_CAN +#define RT_CANMSG_BOX_SZ 16 +#define RT_CANSND_BOX_NUM 1 +#define RT_CANSND_MSG_TIMEOUT 100 #define RT_USING_I2C #define RT_USING_I2C_BITOPS #define RT_USING_PIN @@ -470,6 +474,8 @@ #define BSP_USING_I2C2 #define BSP_USING_I2C3 #define BSP_USING_I2C4 +#define BSP_USING_CAN +#define BSP_USING_CAN1 /* end of On-chip Peripheral Drivers */ /* Board extended module Drivers */