add fal wdt tmr

This commit is contained in:
wmano
2025-08-27 23:16:25 +08:00
parent f9e7fa9956
commit fa4d12b6e0
20 changed files with 1059 additions and 804 deletions
+19 -22
View File
@@ -18,37 +18,34 @@
#if defined(STM32F405xx)
#define NAME_CHIP "STM32F405xx"
#define SIZE_ONCHIP_FLASH (1024 * 1024ul) // 片上 flash 总容量
#elif defined(STM32F411xE)
#define NAME_CHIP "STM32F411xE"
#define SIZE_ONCHIP_FLASH (512 * 1024ul)
#elif defined(STM32F401xC)
#define NAME_CHIP "STM32F401xC"
#define SIZE_ONCHIP_FLASH (256 * 1024ul)
#else
#error "no chip size defined"
#endif
#define SIZE_PART_BOOTLOADER (32 * 1024ul) // bootloader 占用空间(需要大于本程序bin大小)
#define SIZE_PART_PARAMETERS (32 * 1024ul) // 参数 占用空间
#define SIZE_PART_APPLICATION (SIZE_ONCHIP_FLASH/4) // app 占用空间 不少于1/4
#define SIZE_PART_DOWNLOAD (SIZE_PART_APPLICATION) // download 占用空间(不用时0)
#define SIZE_PART_FACTORY (SIZE_PART_APPLICATION) // factory 占用空间(不用时0)
#define SIZE_PART_BOOTLOADER (64 * 1024ul) // bootloader 占用空间(需要大于本程序bin大小)
#define SIZE_PART_PARAMETERS (64 * 1024ul) // 参数 占用空间
#define SIZE_PART_LOG (128 * 1024ul) // 日志 占用空间
#define SIZE_PART_APPLICATION (SIZE_ONCHIP_FLASH/4) // app 占用空间
#define SIZE_PART_DOWNLOAD (SIZE_PART_APPLICATION) // download 占用空间
#define SIZE_PART_FACTORY (SIZE_PART_APPLICATION) // factory 占用空间
#define BASE_ONCHIP_FLASH (FLASH_BASE) // on chip flash 首地址
#define OFFSET_ONCHIP_FLASH_END (BASE_ONCHIP_FLASH + SIZE_ONCHIP_FLASH)
/*
chipsize (256KB/512KB/1024KB) eg: 1024KB
32KB - bootloader = 0x00000 + 32*1024
32KB - parameter = 0x08000 + 32*1024
chipsize/2-64KB - application = 0x10000 + 448*1024
chipsize/4 - download = 0x80000 + 256*1024
chipsize/4 - factory = 0xC0000 + 256*1024
chipsize eg: 1024KB
64KB - bootloader = 0x00000 + 64*1024
64KB - parameter = 0x10000 + 64*1024
128KB - log = 0x20000 + 128*1024
256KB - application = 0x40000 + 256*1024
256KB - download = 0x80000 + 256*1024
256KB - factory = 0xC0000 + 256*1024
*/
#define BASE_BOOTLOADER (BASE_ONCHIP_FLASH)
#define BASE_PARAMETERS (BASE_BOOTLOADER + SIZE_PART_BOOTLOADER) // 参数分区起始地址
#define BASE_APPLICATION (BASE_ONCHIP_FLASH + SIZE_PART_BOOTLOADER+SIZE_PART_PARAMETERS) // app 分区起始地址
#define BASE_DOWNLOAD (BASE_ONCHIP_FLASH + SIZE_ONCHIP_FLASH/2) // download 分区起始地址
#define BASE_FACTORY (BASE_DOWNLOAD + SIZE_PART_DOWNLOAD) // factory 分区起始地址
#define BASE_BOOTLOADER (BASE_ONCHIP_FLASH)
#define BASE_PARAMETERS (BASE_BOOTLOADER + SIZE_PART_BOOTLOADER) // 参数分区起始地址
#define BASE_LOG (BASE_PARAMETERS + SIZE_PART_PARAMETERS)
#define BASE_APPLICATION (BASE_ONCHIP_FLASH + SIZE_PART_BOOTLOADER+SIZE_PART_PARAMETERS+SIZE_PART_LOG) // app 分区起始地址
#define BASE_DOWNLOAD (BASE_ONCHIP_FLASH + SIZE_ONCHIP_FLASH/2) // download 分区起始地址
#define BASE_FACTORY (BASE_DOWNLOAD + SIZE_PART_DOWNLOAD) // factory 分区起始地址
/* 片上分区数量选项
* app: 可运行的固件区域
+25 -4
View File
@@ -224,7 +224,10 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y
# CONFIG_RT_USING_DFS is not set
# end of DFS: device virtual file system
# CONFIG_RT_USING_FAL is not set
CONFIG_RT_USING_FAL=y
# CONFIG_FAL_USING_DEBUG is not set
CONFIG_FAL_PART_HAS_TABLE_CFG=y
# CONFIG_FAL_USING_SFUD_PORT is not set
#
# Device Drivers
@@ -267,10 +270,12 @@ CONFIG_RT_USING_I2C_BITOPS=y
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
CONFIG_RT_USING_WDT=y
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
@@ -281,7 +286,7 @@ CONFIG_RT_USING_I2C_BITOPS=y
# CONFIG_RT_USING_VIRTIO is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_KTIME is not set
# CONFIG_RT_USING_HWTIMER is not set
CONFIG_RT_USING_HWTIMER=y
# CONFIG_RT_USING_CHERRYUSB is not set
# end of Device Drivers
@@ -1504,6 +1509,22 @@ CONFIG_BSP_USING_I2C3=y
CONFIG_BSP_USING_I2C4=y
CONFIG_BSP_USING_CAN=y
CONFIG_BSP_USING_CAN1=y
# CONFIG_BSP_USING_ADC is not set
CONFIG_BSP_USING_ONCHIP_RTC=y
CONFIG_BSP_RTC_USING_LSE=y
# CONFIG_BSP_RTC_USING_LSI is not set
CONFIG_BSP_USING_WDT=y
# CONFIG_BSP_USING_USBD is not set
# CONFIG_BSP_USING_USBH is not set
CONFIG_BSP_USING_ON_CHIP_FLASH=y
CONFIG_BSP_USING_TIM=y
# CONFIG_BSP_USING_TIM1 is not set
CONFIG_BSP_USING_TIM2=y
# CONFIG_BSP_USING_TIM3 is not set
# CONFIG_BSP_USING_TIM4 is not set
# CONFIG_BSP_USING_TIM5 is not set
# CONFIG_BSP_USING_TIM6 is not set
# CONFIG_BSP_USING_TIM7 is not set
# CONFIG_BSP_USING_RNG is not set
# CONFIG_BSP_USING_UDID is not set
# end of On-chip Peripheral Drivers
+30
View File
@@ -0,0 +1,30 @@
#include <rtthread.h>
#include "fal.h"
#define LOG_TAG "etc2.fal"
#define DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL DBG_LOG
#define DBG_COLOR
#include <rtdbg.h>
static int chrg_fal_init (void)
{
rt_int32_t ret = 0;
ret = fal_init();
if (ret <= 0) {
LOG_E("fal init failed.");
return ret;
}
return 0;
}
INIT_ENV_EXPORT(chrg_fal_init);
+177
View File
@@ -0,0 +1,177 @@
#include <string.h>
#include "chrg_tmr.h"
#define LOG_TAG "chrg.tmr"
#define DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL DBG_LOG
#define DBG_COLOR
#include <rtdbg.h>
struct chrg_tmr_t chrgtmr[TOTAL_TMRS] = {
[IDX_TMR_1S] = {
.index = IDX_TMR_1S,
.dev = RT_NULL,
.name = DEV_NAME_HWTIMER_1S,
.mode = HWTIMER_MODE_PERIOD,
.timeout = 1000000, // 10ms
}
};
static rt_err_t chrg_tmr_1s_callback(rt_device_t dev, rt_size_t size)
{
rt_kprintf(".");
return RT_EOK;
}
int chrg_tmr_init (eIDX_TMR index)
{
rt_err_t ret = RT_EOK;
rt_uint32_t freq = 1000000;
if (index >= TOTAL_TMRS) {
return -1;
}
struct chrg_tmr_t *pTMR = &chrgtmr[index];
pTMR->dev = rt_device_find(pTMR->name);
if (RT_NULL == pTMR->dev) {
LOG_E("dev '%s' not found.", pTMR->name);
return -1;
}
ret = rt_device_open(pTMR->dev, RT_DEVICE_OFLAG_RDWR);
if (RT_EOK != ret) {
LOG_E("open dev '%s' failed. %d", pTMR->name, ret);
return ret;
}
ret = rt_device_control(pTMR->dev, HWTIMER_CTRL_FREQ_SET, &freq);
if (RT_EOK != ret) {
LOG_E("set '%s' freq failed. %d", pTMR->name, ret);
return ret;
}
ret = rt_device_control(pTMR->dev, HWTIMER_CTRL_MODE_SET, &pTMR->mode);
if (RT_EOK != ret) {
LOG_E("set '%s' mode failed. %d", pTMR->name, ret);
return ret;
}
switch (pTMR->index) {
case IDX_TMR_1S:
ret = rt_device_set_rx_indicate(pTMR->dev, chrg_tmr_1s_callback);
break;
default:
return -1;
}
return ret;
}
rt_err_t chrg_tmr_start (eIDX_TMR index, uint32_t timeo)
{
rt_err_t ret = RT_EOK;
if (index >= TOTAL_TMRS) {
return RT_EINVAL;
}
struct chrg_tmr_t *pTMR = &chrgtmr[index];
if (RT_NULL == pTMR->dev) {
LOG_E("dev '%s' not opened.", pTMR->name);
return 0;
}
pTMR->timeout.sec = timeo/1000000;
pTMR->timeout.usec = timeo%1000000;
if (rt_device_write(pTMR->dev, 0, &pTMR->timeout, sizeof(rt_hwtimerval_t)) != sizeof(rt_hwtimerval_t)) {
rt_kprintf("set '%s' timeout failed.\r\n", pTMR->name);
return ret;
}
return ret;
}
rt_err_t chrg_tmr_stop (eIDX_TMR index)
{
rt_err_t ret = RT_EOK;
if (index >= TOTAL_TMRS) {
return RT_EINVAL;
}
struct chrg_tmr_t *pTMR = &chrgtmr[index];
if (RT_NULL == pTMR->dev) {
LOG_E("dev '%s' not opened.", pTMR->name);
return 0;
}
ret = rt_device_control(pTMR->dev, HWTIMER_CTRL_STOP, RT_NULL);
if (RT_EOK != ret) {
LOG_E("set '%s' stop failed. %d", pTMR->name, ret);
return ret;
}
return ret;
}
void chrg_tmr_release (eIDX_TMR index)
{
if (index >= TOTAL_TMRS) {
return ;
}
struct chrg_tmr_t *pTMR = &chrgtmr[index];
if (RT_NULL != pTMR->dev) {
rt_device_close(pTMR->dev);
pTMR->dev = RT_NULL;
}
}
int chrg_tmrs_init (void)
{
int i = 0;
for (i = 0; i < TOTAL_TMRS; i++) {
chrg_tmr_init((eIDX_TMR)i);
}
return 0;
}
INIT_ENV_EXPORT(chrg_tmrs_init);
#if 1
static int sec_tmr(int argc, char **argv)
{
if (argc != 2) {
rt_kprintf("sec_tmr <start|stop>\r\n");
return RT_ERROR;
}
if (strcmp(argv[1], "start") == 0) {
chrg_tmr_start(IDX_TMR_1S, 1000000);
} else if (strcmp(argv[1], "stop") == 0) {
chrg_tmr_stop(IDX_TMR_1S);
} else {
rt_kprintf("sec_tmr start|stop\r\n");
}
return 0;
}
MSH_CMD_EXPORT(sec_tmr, second timer);
#endif
+39
View File
@@ -0,0 +1,39 @@
#ifndef __CHRG_TMR_H__
#define __CHRG_TMR_H__
#include <rtthread.h>
#include <rtdevice.h>
#define DEV_NAME_HWTIMER_1S "timer2"
typedef enum {
IDX_TMR_1S = 0, // 1s 周期
TOTAL_TMRS
} eIDX_TMR;
struct chrg_tmr_t {
rt_device_t dev;
const char *name;
rt_hwtimer_mode_t mode; // 执行模式 周期/单次
rt_hwtimerval_t timeout; // 周期 us
eIDX_TMR index; // 定时器编号
};
extern struct chrg_tmr_t chrgtmr[TOTAL_TMRS];
extern rt_err_t chrg_tmr_start (eIDX_TMR index, uint32_t timeo);
extern rt_err_t chrg_tmr_stop (eIDX_TMR index);
extern void chrg_tmr_release (eIDX_TMR index);
#endif
+48
View File
@@ -0,0 +1,48 @@
#include <rtthread.h>
#include <rtdevice.h>
#include "chrg_wdt.h"
struct chrg_wdt_t chrgwdt = {
.dev = RT_NULL,
.name = DEV_NAME_WATCHDOG,
.feed = 3,
};
void chrg_wdt_feed (void)
{
rt_device_control(chrgwdt.dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, RT_NULL);
}
static int chrg_wdt_init (void)
{
rt_err_t ret;
struct chrg_wdt_t *pWDT = &chrgwdt;
pWDT->dev = rt_device_find(pWDT->name);
if (RT_NULL == pWDT->dev) {
rt_kprintf("dev '%s' not found.\r\n", pWDT->name);
return RT_ERROR;
}
ret = rt_device_control(chrgwdt.dev, RT_DEVICE_CTRL_WDT_SET_TIMEOUT, &pWDT->feed);
if (RT_EOK != ret) {
rt_kprintf("dev '%s' control failed.\r\n", pWDT->name);
return ret;
}
ret = rt_device_control(chrgwdt.dev, RT_DEVICE_CTRL_WDT_START, RT_NULL);
if (RT_EOK != ret) {
rt_kprintf("dev '%s' start failed.\r\n", pWDT->name);
return ret;
}
//rt_thread_idle_sethook(chrg_wdt_feed);
return RT_EOK;
}
INIT_APP_EXPORT(chrg_wdt_init);
+24
View File
@@ -0,0 +1,24 @@
#ifndef __CHRG_WDT_H__
#define __CHRG_WDT_H__
#include <rtthread.h>
#include <rtdevice.h>
#define DEV_NAME_WATCHDOG "wdt"
struct chrg_wdt_t {
rt_device_t dev;
const char *name;
rt_uint32_t feed;
};
extern struct chrg_wdt_t chrgwdt;
extern void chrg_wdt_feed (void);
#endif
+3 -1
View File
@@ -6,6 +6,7 @@
#include "shell.h"
#include "main.h"
#include "chrg_wdt.h"
void show_app_version (void)
{
@@ -25,7 +26,8 @@ int main(void)
#endif
while (1) {
rt_thread_mdelay(500);
rt_thread_mdelay(1000);
chrg_wdt_feed();
}
}
@@ -66,15 +66,15 @@
/* #define HAL_HASH_MODULE_ENABLED */
/* #define HAL_I2C_MODULE_ENABLED */
/* #define HAL_I2S_MODULE_ENABLED */
/* #define HAL_IWDG_MODULE_ENABLED */
#define HAL_IWDG_MODULE_ENABLED
/* #define HAL_LTDC_MODULE_ENABLED */
/* #define HAL_RNG_MODULE_ENABLED */
/* #define HAL_RTC_MODULE_ENABLED */
#define HAL_RTC_MODULE_ENABLED
/* #define HAL_SAI_MODULE_ENABLED */
/* #define HAL_SD_MODULE_ENABLED */
/* #define HAL_MMC_MODULE_ENABLED */
/* #define HAL_SPI_MODULE_ENABLED */
/* #define HAL_TIM_MODULE_ENABLED */
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
/* #define HAL_USART_MODULE_ENABLED */
/* #define HAL_IRDA_MODULE_ENABLED */
+97
View File
@@ -260,6 +260,103 @@ menu "On-chip Peripheral Drivers"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC1
bool "Enable ADC1"
default n
endif
menuconfig BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
default n
if BSP_USING_ONCHIP_RTC
choice
prompt "Select clock source"
default BSP_RTC_USING_LSE
config BSP_RTC_USING_LSE
bool "RTC USING LSE"
config BSP_RTC_USING_LSI
bool "RTC USING LSI"
endchoice
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_USBD
bool "Enable USB Device"
select RT_USING_USB_DEVICE
default n
menuconfig BSP_USING_USBH
bool "Enable USB Host"
select RT_USING_USB_HOST
default n
if BSP_USING_USBH
menuconfig RT_USBH_MSTORAGE
bool "Enable Udisk Drivers"
default n
if RT_USBH_MSTORAGE
config UDISK_MOUNTPOINT
string "Udisk mount dir"
default "/"
endif
endif
config BSP_USING_FMC
bool
default n
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
menuconfig BSP_USING_TIM
bool "Enable timer"
default n
select RT_USING_HWTIMER
if BSP_USING_TIM
config BSP_USING_TIM1
bool "Enable TIM1"
default n
config BSP_USING_TIM2
bool "Enable TIM2"
default n
config BSP_USING_TIM3
bool "Enable TIM3"
default n
config BSP_USING_TIM4
bool "Enable TIM4"
default n
config BSP_USING_TIM5
bool "Enable TIM5"
default n
config BSP_USING_TIM6
bool "Enable TIM6"
default n
config BSP_USING_TIM7
bool "Enable TIM7"
default n
endif
source "$(RTT_DIR)/bsp/stm32/libraries/HAL_Drivers/drivers/Kconfig"
endmenu
+22
View File
@@ -0,0 +1,22 @@
import os
from building import *
objs = []
cwd = GetCurrentDir()
# add general drivers
src = []
path = [cwd]
#if GetDepend(['BSP_USING_SDCARD']):
# src += Glob('sdcard_port.c')
CPPDEFINES = ['STM32F405xx']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
group = group + SConscript(os.path.join(item, 'SConscript'))
Return('group')
+51
View File
@@ -0,0 +1,51 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-07-13 Dozingfiretruck first version
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtthread.h>
#include <board.h>
#define FLASH_SIZE_GRANULARITY_16K (4 * 16 * 1024)
#define FLASH_SIZE_GRANULARITY_64K (64 * 1024)
#define FLASH_SIZE_GRANULARITY_128K (7 * 128 * 1024)
#define STM32_FLASH_START_ADRESS_16K STM32_FLASH_START_ADRESS
#define STM32_FLASH_START_ADRESS_64K (STM32_FLASH_START_ADRESS_16K + FLASH_SIZE_GRANULARITY_16K)
#define STM32_FLASH_START_ADRESS_128K (STM32_FLASH_START_ADRESS_64K + FLASH_SIZE_GRANULARITY_64K)
extern const struct fal_flash_dev stm32_onchip_flash_16k;
extern const struct fal_flash_dev stm32_onchip_flash_64k;
extern const struct fal_flash_dev stm32_onchip_flash_128k;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&stm32_onchip_flash_16k, \
&stm32_onchip_flash_64k, \
&stm32_onchip_flash_128k, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WROD, "boot", "onchip_flash_16k", 0 , FLASH_SIZE_GRANULARITY_16K , 0}, \
{FAL_PART_MAGIC_WROD, "param", "onchip_flash_64k", 0 , FLASH_SIZE_GRANULARITY_64K , 0}, \
{FAL_PART_MAGIC_WROD, "log", "onchip_flash_128k", 0 , 128*1024 , 0}, \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash_128k", 128*1024 , 2*128*1024, 0}, \
{FAL_PART_MAGIC_WROD, "download", "onchip_flash_128k", 3*128*1024 , 2*128*1024, 0}, \
{FAL_PART_MAGIC_WROD, "factory", "onchip_flash_128k", 5*128*1024 , 2*128*1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */
+490 -213
View File
File diff suppressed because it is too large Load Diff
+11
View File
@@ -137,6 +137,8 @@
/* DFS: device virtual file system */
/* end of DFS: device virtual file system */
#define RT_USING_FAL
#define FAL_PART_HAS_TABLE_CFG
/* Device Drivers */
@@ -155,7 +157,10 @@
#define RT_CANSND_MSG_TIMEOUT 100
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_RTC
#define RT_USING_WDT
#define RT_USING_PIN
#define RT_USING_HWTIMER
/* end of Device Drivers */
/* C/C++ and POSIX layer */
@@ -476,6 +481,12 @@
#define BSP_USING_I2C4
#define BSP_USING_CAN
#define BSP_USING_CAN1
#define BSP_USING_ONCHIP_RTC
#define BSP_RTC_USING_LSE
#define BSP_USING_WDT
#define BSP_USING_ON_CHIP_FLASH
#define BSP_USING_TIM
#define BSP_USING_TIM2
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
+1 -1
View File
@@ -274,7 +274,7 @@
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x8010000</StartAddress>
<StartAddress>0x8040000</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
+19 -19
View File
@@ -276,7 +276,7 @@
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x8000</Size>
<Size>0x10000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
@@ -339,7 +339,7 @@
<MiscControls></MiscControls>
<Define>USE_HAL_DRIVER,STM32F405xx</Define>
<Undefine></Undefine>
<IncludePath>..\lib\stm32f4\STM32F4_HAL\Inc;..\lib\stm32f4\STM32F4_HAL\Inc\Legacy;..\lib\stm32f4\STM32F4_CMSIS\Include;..\lib\cmsis-core\Include;..\apps\boot\include;..\apps\boot\bsp</IncludePath>
<IncludePath>..\libs\stm32f4\STM32F4_HAL\Inc;..\libs\stm32f4\STM32F4_HAL\Inc\Legacy;..\libs\stm32f4\STM32F4_CMSIS\Include;..\libs\cmsis-core\Include;..\apps\boot\include;..\apps\boot\bsp</IncludePath>
</VariousControls>
</Cads>
<Aads>
@@ -421,7 +421,7 @@
<File>
<FileName>startup_stm32f405xx.s</FileName>
<FileType>2</FileType>
<FilePath>..\lib\stm32f4\STm32F4_CMSIS\Source\Templates\arm\startup_stm32f405xx.s</FilePath>
<FilePath>..\libs\stm32f4\STm32F4_CMSIS\Source\Templates\arm\startup_stm32f405xx.s</FilePath>
</File>
</Files>
</Group>
@@ -556,82 +556,82 @@
<File>
<FileName>stm32f4xx_hal.c</FileName>
<FileType>1</FileType>
<FilePath>..\lib\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal.c</FilePath>
<FilePath>..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_cortex.c</FileName>
<FileType>1</FileType>
<FilePath>..\lib\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_cortex.c</FilePath>
<FilePath>..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_cortex.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_dma.c</FileName>
<FileType>1</FileType>
<FilePath>..\lib\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_dma.c</FilePath>
<FilePath>..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_dma.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_dma_ex.c</FileName>
<FileType>1</FileType>
<FilePath>..\lib\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_dma_ex.c</FilePath>
<FilePath>..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_dma_ex.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_exti.c</FileName>
<FileType>1</FileType>
<FilePath>..\lib\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_exti.c</FilePath>
<FilePath>..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_exti.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_flash.c</FileName>
<FileType>1</FileType>
<FilePath>..\lib\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_flash.c</FilePath>
<FilePath>..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_flash.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_flash_ex.c</FileName>
<FileType>1</FileType>
<FilePath>..\lib\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_flash_ex.c</FilePath>
<FilePath>..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_flash_ex.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_flash_ramfunc.c</FileName>
<FileType>1</FileType>
<FilePath>..\lib\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_flash_ramfunc.c</FilePath>
<FilePath>..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_flash_ramfunc.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\lib\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_gpio.c</FilePath>
<FilePath>..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_gpio.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_pwr.c</FileName>
<FileType>1</FileType>
<FilePath>..\lib\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_pwr.c</FilePath>
<FilePath>..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_pwr.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_pwr_ex.c</FileName>
<FileType>1</FileType>
<FilePath>..\lib\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_pwr_ex.c</FilePath>
<FilePath>..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_pwr_ex.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_rcc.c</FileName>
<FileType>1</FileType>
<FilePath>..\lib\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_rcc.c</FilePath>
<FilePath>..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_rcc.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_rcc_ex.c</FileName>
<FileType>1</FileType>
<FilePath>..\lib\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_rcc_ex.c</FilePath>
<FilePath>..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_rcc_ex.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_tim.c</FileName>
<FileType>1</FileType>
<FilePath>..\lib\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_tim.c</FilePath>
<FilePath>..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_tim.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_tim_ex.c</FileName>
<FileType>1</FileType>
<FilePath>..\lib\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_tim_ex.c</FilePath>
<FilePath>..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_tim_ex.c</FilePath>
</File>
<File>
<FileName>stm32f4xx_hal_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\lib\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_uart.c</FilePath>
<FilePath>..\libs\stm32f4\STM32F4_HAL\Src\stm32f4xx_hal_uart.c</FilePath>
</File>
</Files>
</Group>
@@ -1,275 +0,0 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
* 2020-03-05 redoc support stm32f103vg
*
*/
#include <rtconfig.h>
#include <rtdef.h>
#ifdef BSP_USING_ON_CHIP_FLASH
#include "drv_config.h"
#include "drv_flash.h"
#include <board.h>
#if defined(RT_USING_FAL)
#include "fal.h"
#endif
//#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#include <drv_log.h>
/**
* @brief Gets the page of a given address
* @param Addr: Address of the FLASH Memory
* @retval The page of a given address
*/
static uint32_t GetPage(uint32_t addr)
{
uint32_t page = 0;
page = RT_ALIGN_DOWN(addr, FLASH_PAGE_SIZE);
return page;
}
/**
* Read data from flash.
* @note This operation's units is word.
*
* @param addr flash address
* @param buf buffer to store read data
* @param size read bytes size
*
* @return result
*/
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
{
size_t i;
if ((addr + size) > STM32_FLASH_END_ADDRESS)
{
LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
for (i = 0; i < size; i++, buf++, addr++)
{
*buf = *(rt_uint8_t *) addr;
}
return size;
}
/**
* Write data to flash.
* @note This operation's units is word.
* @note This operation must after erase. @see flash_erase.
*
* @param addr flash address
* @param buf the write data buffer
* @param size write bytes size
*
* @return result
*/
int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
{
rt_err_t result = RT_EOK;
rt_uint32_t end_addr = addr + size;
if (addr % 4 != 0)
{
LOG_E("write addr must be 4-byte alignment");
return -RT_EINVAL;
}
if ((end_addr) > STM32_FLASH_END_ADDRESS)
{
LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
HAL_FLASH_Unlock();
while (addr < end_addr)
{
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, addr, *((rt_uint32_t *)buf)) == HAL_OK)
{
if (*(rt_uint32_t *)addr != *(rt_uint32_t *)buf)
{
result = -RT_ERROR;
break;
}
addr += 4;
buf += 4;
}
else
{
result = -RT_ERROR;
break;
}
}
HAL_FLASH_Lock();
if (result != RT_EOK)
{
return result;
}
return size;
}
/**
* Erase data on flash with bank.
* @note This operation is irreversible.
* @note This operation's units is different which on many chips.
*
* @param bank flash bank
* @param addr flash address
* @param size erase bytes size
*
* @return result
*/
int stm32_flash_erase_bank(uint32_t bank, rt_uint32_t addr, size_t size)
{
rt_err_t result = RT_EOK;
uint32_t PAGEError = 0;
/*Variable used for Erase procedure*/
FLASH_EraseInitTypeDef EraseInitStruct;
if ((addr + size) > STM32_FLASH_END_ADDRESS)
{
LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
return -RT_EINVAL;
}
HAL_FLASH_Unlock();
/* Fill EraseInit structure*/
EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
EraseInitStruct.PageAddress = GetPage(addr);
EraseInitStruct.NbPages = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;
EraseInitStruct.Banks = bank;
if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
{
result = -RT_ERROR;
goto __exit;
}
__exit:
HAL_FLASH_Lock();
if (result != RT_EOK)
{
return result;
}
LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
return size;
}
/**
* Erase data on flash .
* @note This operation is irreversible.
* @note This operation's units is different which on many chips.
*
* @param addr flash address
* @param size erase bytes size
*
* @return result
*/
int stm32_flash_erase(rt_uint32_t addr, size_t size)
{
#if defined(FLASH_BANK2_END)
rt_err_t result = RT_EOK;
rt_uint32_t addr_bank1 = 0;
rt_uint32_t size_bank1 = 0;
rt_uint32_t addr_bank2 = 0;
rt_uint32_t size_bank2 = 0;
if((addr + size) <= FLASH_BANK1_END)
{
addr_bank1 = addr;
size_bank1 = size;
size_bank2 = 0;
}
else if(addr > FLASH_BANK1_END)
{
size_bank1 = 0;
addr_bank2 = addr;
size_bank2 = size;
}
else
{
addr_bank1 = addr;
size_bank1 = FLASH_BANK1_END + 1 - addr_bank1;
addr_bank2 = FLASH_BANK1_END + 1;
size_bank2 = addr + size - (FLASH_BANK1_END + 1);
}
if(size_bank1)
{
LOG_D("bank1: addr (0x%p), size %d", (void *)addr_bank1, size_bank1);
if(size_bank1 != stm32_flash_erase_bank(FLASH_BANK_1, addr_bank1, size_bank1))
{
result = -RT_ERROR;
goto __exit;
}
}
if(size_bank2)
{
LOG_D("bank2: addr (0x%p), size %d", (void *)addr_bank2, size_bank2);
if(size_bank2 != stm32_flash_erase_bank(FLASH_BANK_2, addr_bank2, size_bank2))
{
result = -RT_ERROR;
goto __exit;
}
}
__exit:
if(result != RT_EOK)
{
return result;
}
return size_bank1 + size_bank2;
#else
return stm32_flash_erase_bank(FLASH_BANK_1, addr, size);
#endif
}
#if defined(RT_USING_FAL)
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_erase(long offset, size_t size);
const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} };
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
{
return stm32_flash_read(stm32_onchip_flash.addr + offset, buf, size);
}
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
{
return stm32_flash_write(stm32_onchip_flash.addr + offset, buf, size);
}
static int fal_flash_erase(long offset, size_t size)
{
return stm32_flash_erase(stm32_onchip_flash.addr + offset, size);
}
#endif
#endif /* BSP_USING_ON_CHIP_FLASH */
@@ -388,7 +388,6 @@ const struct fal_flash_dev stm32_onchip_flash_16k =
fal_flash_erase_16k,
},
8,
{},
};
const struct fal_flash_dev stm32_onchip_flash_64k =
{
@@ -403,7 +402,6 @@ const struct fal_flash_dev stm32_onchip_flash_64k =
fal_flash_erase_64k,
},
8,
{},
};
const struct fal_flash_dev stm32_onchip_flash_128k =
{
@@ -418,7 +416,6 @@ const struct fal_flash_dev stm32_onchip_flash_128k =
fal_flash_erase_128k,
},
8,
{},
};
static int fal_flash_read_16k(long offset, rt_uint8_t *buf, size_t size)
@@ -1,263 +0,0 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
* 2019-3-2 jinsheng add Macro judgment
* 2020-1-6 duminmin support single bank mode
* 2020-5-17 yufanyufan77 support support H7
* 2021-3-3 zhuyf233 fix some bugs
*/
#include <rtconfig.h>
#include <rtdef.h>
#ifdef BSP_USING_ON_CHIP_FLASH
#include "drv_config.h"
#include "drv_flash.h"
#include <board.h>
#if defined(RT_USING_FAL)
#include "fal.h"
#endif
//#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#include <drv_log.h>
/**
* Read data from flash.
* @note This operation's units is word.
*
* @param addr flash address
* @param buf buffer to store read data
* @param size read bytes size
*
* @retval The length of bytes that have been read
*/
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
{
size_t i;
if ((addr + size - 1) > FLASH_END)
{
LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_ERROR;
}
for (i = 0; i < size; i++, buf++, addr++)
{
*buf = *(rt_uint8_t *) addr;
}
return size;
}
/**
* Write data to flash.
* @note This operation's units is word.
* @note This operation must after erase. @see flash_erase.
*
* @param addr flash address
* @param buf the write data buffer
* @param size write bytes size
*
* @return The length of bytes that have been written
*/
int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
{
rt_err_t result = RT_EOK;
rt_uint32_t end_addr = addr + size - 1, write_addr;
rt_uint32_t write_granularity = FLASH_NB_32BITWORD_IN_FLASHWORD * 4;
rt_uint32_t write_size = write_granularity;
rt_uint8_t write_buffer[32] = {0};
if ((end_addr) > FLASH_END)
{
LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
if(addr % 32 != 0)
{
LOG_E("write addr must be 32-byte alignment");
return -RT_EINVAL;
}
if (size < 1)
{
return -RT_EINVAL;
}
HAL_FLASH_Unlock();
write_addr = (uint32_t)buf;
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR);
while (addr < end_addr)
{
if(end_addr - addr + 1 < write_granularity)
{
write_size = end_addr - addr + 1;
for(size_t i = 0; i < write_size; i++)
{
write_buffer[i] = *((uint8_t *)(write_addr + i));
}
write_addr = (uint32_t)((rt_uint32_t *)write_buffer);
}
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, addr, write_addr) == HAL_OK)
{
for(rt_uint8_t i = 0; i < write_size; i++)
{
if (*(rt_uint8_t *)(addr + i) != *(rt_uint8_t *)(write_addr + i))
{
result = -RT_ERROR;
goto __exit;
}
}
addr += write_granularity;
write_addr += write_granularity;
}
else
{
result = -RT_ERROR;
goto __exit;
}
}
__exit:
HAL_FLASH_Lock();
if (result != RT_EOK)
{
return result;
}
return size;
}
/**
* Erase data on flash.
* @note This operation is irreversible.
* @note This operation's units is different which on many chips.
*
* @param addr flash address
* @param size erase bytes size
*
* @return result
*/
int stm32_flash_erase(rt_uint32_t addr, size_t size)
{
rt_err_t result = RT_EOK;
rt_uint32_t SECTORError = 0;
if ((addr + size - 1) > FLASH_END)
{
LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
return -RT_EINVAL;
}
rt_uint32_t addr_bank1 = 0;
rt_uint32_t size_bank1 = 0;
#ifdef FLASH_BANK_2
rt_uint32_t addr_bank2 = 0;
rt_uint32_t size_bank2 = 0;
#endif
if((addr + size) < FLASH_BANK2_BASE)
{
addr_bank1 = addr;
size_bank1 = size;
#ifdef FLASH_BANK_2
size_bank2 = 0;
#endif
}
else if(addr >= FLASH_BANK2_BASE)
{
size_bank1 = 0;
#ifdef FLASH_BANK_2
addr_bank2 = addr;
size_bank2 = size;
#endif
}
else
{
addr_bank1 = addr;
size_bank1 = FLASH_BANK2_BASE - addr_bank1;
#ifdef FLASH_BANK_2
addr_bank2 = FLASH_BANK2_BASE;
size_bank2 = addr + size - FLASH_BANK2_BASE;
#endif
}
/*Variable used for Erase procedure*/
FLASH_EraseInitTypeDef EraseInitStruct;
/* Unlock the Flash to enable the flash control register access */
HAL_FLASH_Unlock();
EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS;
EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3;
SCB_DisableDCache();
if(size_bank1)
{
EraseInitStruct.Sector = (addr_bank1 - FLASH_BANK1_BASE) / FLASH_SECTOR_SIZE;
EraseInitStruct.NbSectors = (addr_bank1 + size_bank1 -1 - FLASH_BANK1_BASE) / FLASH_SECTOR_SIZE - EraseInitStruct.Sector + 1;
EraseInitStruct.Banks = FLASH_BANK_1;
if (HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError) != HAL_OK)
{
result = -RT_ERROR;
goto __exit;
}
}
#ifdef FLASH_BANK_2
if(size_bank2)
{
EraseInitStruct.Sector = (addr_bank2 - FLASH_BANK2_BASE) / FLASH_SECTOR_SIZE;
EraseInitStruct.NbSectors = (addr_bank2 + size_bank2 -1 - FLASH_BANK2_BASE) / FLASH_SECTOR_SIZE - EraseInitStruct.Sector + 1;
EraseInitStruct.Banks = FLASH_BANK_2;
if (HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError) != HAL_OK)
{
result = -RT_ERROR;
goto __exit;
}
}
#endif
__exit:
SCB_EnableDCache();
HAL_FLASH_Lock();
if (result != RT_EOK)
{
return result;
}
LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
return size;
}
#if defined(RT_USING_FAL)
static int fal_flash_read_128k(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_write_128k(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_erase_128k(long offset, size_t size);
const struct fal_flash_dev stm32_onchip_flash_128k = { "onchip_flash_128k", STM32_FLASH_START_ADRESS, FLASH_SIZE_GRANULARITY_128K, (128 * 1024), {NULL, fal_flash_read_128k, fal_flash_write_128k, fal_flash_erase_128k} };
static int fal_flash_read_128k(long offset, rt_uint8_t *buf, size_t size)
{
return stm32_flash_read(stm32_onchip_flash_128k.addr + offset, buf, size);
}
static int fal_flash_write_128k(long offset, const rt_uint8_t *buf, size_t size)
{
return stm32_flash_write(stm32_onchip_flash_128k.addr + offset, buf, size);
}
static int fal_flash_erase_128k(long offset, size_t size)
{
return stm32_flash_erase(stm32_onchip_flash_128k.addr + offset, size);
}
#endif
#endif /* BSP_USING_ON_CHIP_FLASH */