diff --git a/apps/chrg/applications/thread/chrg_comm.c b/apps/chrg/applications/thread/chrg_comm.c
index 4cb1a8f..5e400b7 100644
--- a/apps/chrg/applications/thread/chrg_comm.c
+++ b/apps/chrg/applications/thread/chrg_comm.c
@@ -1,7 +1,7 @@
 /****************************************************************************
 文件名称   : chrg_comm.c
 完成日期   : 
-当前版本号 : V1.1.8
+当前版本号 : V1.1.9
 主要功能   : 实现对外通讯协议 MODBUS 服务端，以独立线程等待处理响应请求数据。
 版本历史   : 创建原始版本
 说明      : 
@@ -27,7 +27,7 @@
 #include "stm32f4xx_hal.h"
 
 #define HOLD_REG_FIRMWARE_VERSION 0x0300U /* 协议板固件版本，只读 */
-#define CHRG_FIRMWARE_VERSION     0x0118U /* 当前协议板版本：V1.1.8 */
+#define CHRG_FIRMWARE_VERSION     0x0119U /* 当前协议板版本：V1.1.9 */
 
 rt_uint8_t ucDiscInBuf[(TOTAL_DISC_REGS+BITS_UCHAR-1)/BITS_UCHAR];
 rt_uint8_t ucCoilBuf[(TOTAL_COIL_REGS+BITS_UCHAR-1)/BITS_UCHAR];
@@ -607,7 +607,7 @@ eMBException funcReadHoldingRegister (rt_uint8_t *reqFrame, rt_uint16_t reqLen,
 
 	/*
 	 * 协议板版本号使用独立的只读地址0x0300，不占用现有通道保持寄存器空间。
-	 * 当前版本V1.1.8编码为0x0118，Modbus响应按高字节在前返回01 18。
+	 * 当前版本V1.1.9编码为0x0119，Modbus响应按高字节在前返回01 19。
 	 * 该特殊地址只支持一次读取一个寄存器，避免与普通连续寄存器混用。
 	 */
 	if (regAddress == HOLD_REG_FIRMWARE_VERSION) {
diff --git a/apps/chrg/applications/thread/chrg_comm.h b/apps/chrg/applications/thread/chrg_comm.h
index 7b292e6..9f294a6 100644
--- a/apps/chrg/applications/thread/chrg_comm.h
+++ b/apps/chrg/applications/thread/chrg_comm.h
@@ -1,7 +1,7 @@
 /****************************************************************************
 文件名称   : chrg_comm.h
 完成日期   : 
-当前版本号 : V1.1.8
+当前版本号 : V1.1.9
 主要功能   : 实现对外通讯协议 MODBUS 服务端，以独立线程等待处理响应请求数据。
 版本历史   : 创建原始版本
 说明      : 
diff --git a/apps/chrg/applications/thread/chrg_north.c b/apps/chrg/applications/thread/chrg_north.c
index b4a66d0..d520023 100644
--- a/apps/chrg/applications/thread/chrg_north.c
+++ b/apps/chrg/applications/thread/chrg_north.c
@@ -1,7 +1,7 @@
 /****************************************************************************
 文件名称   : chrg_north.c
 完成日期   : 
-当前版本号 : V1.1.8
+当前版本号 : V1.1.9
 主要功能   : 实现北向通信交互，包括接收命令解析，发送请求命令，切换通路。以独立线程处理。
 版本历史   : 创建原始版本
 说明      : 
diff --git a/apps/chrg/applications/thread/chrg_roll_nor.c b/apps/chrg/applications/thread/chrg_roll_nor.c
index b944c52..b99b523 100644
--- a/apps/chrg/applications/thread/chrg_roll_nor.c
+++ b/apps/chrg/applications/thread/chrg_roll_nor.c
@@ -1,7 +1,7 @@
 /****************************************************************************
 文件名称   : chrg_roll_nor.c
 完成日期   : 
-当前版本号 : V1.1.8
+当前版本号 : V1.1.9
 主要功能   : 实现北向通信轮巡请求命令。以独立线程处理。
 版本历史   : 创建原始版本
 说明      : 
diff --git a/apps/chrg/applications/thread/chrg_roll_nor.h b/apps/chrg/applications/thread/chrg_roll_nor.h
index c2cca5c..5e638a3 100644
--- a/apps/chrg/applications/thread/chrg_roll_nor.h
+++ b/apps/chrg/applications/thread/chrg_roll_nor.h
@@ -1,7 +1,7 @@
 /****************************************************************************
 文件名称   : chrg_roll_nor.h
 完成日期   : 
-当前版本号 : V1.1.8
+当前版本号 : V1.1.9
 主要功能   : 实现北向通信轮巡请求命令。以独立线程处理。
 版本历史   : 创建原始版本
 说明      : 
diff --git a/apps/chrg/applications/utils/chrg_source.c b/apps/chrg/applications/utils/chrg_source.c
index f50d3a7..01626a3 100644
--- a/apps/chrg/applications/utils/chrg_source.c
+++ b/apps/chrg/applications/utils/chrg_source.c
@@ -1,7 +1,7 @@
 /****************************************************************************
 文件名称   : chrg_source.c
 完成日期   : 
-当前版本号 : V1.1.8
+当前版本号 : V1.1.9
 主要功能   : 北向数据source请求数据填充及发送。
 版本历史   : 创建原始版本
 说明      : 
diff --git a/apps/chrg/applications/utils/chrg_source.h b/apps/chrg/applications/utils/chrg_source.h
index 75b6377..3ddb1a8 100644
--- a/apps/chrg/applications/utils/chrg_source.h
+++ b/apps/chrg/applications/utils/chrg_source.h
@@ -1,7 +1,7 @@
 /****************************************************************************
 文件名称   : chrg_source.c
 完成日期   : 
-当前版本号 : V1.1.8
+当前版本号 : V1.1.9
 主要功能   : 北向数据source请求数据填充及发送，命令字定义。
 版本历史   : 创建原始版本
 说明      : 
diff --git a/docs/Allegro.jrl b/docs/Allegro.jrl
new file mode 100644
index 0000000..84b204a
--- /dev/null
+++ b/docs/Allegro.jrl
@@ -0,0 +1,669 @@
+\t (00:00:05) Allegro 17.2 S079 Windows SPB 64-bit Edition
+\t (00:00:05)     Journal start - Tue Aug 25 19:43:26 2026
+\t (00:00:05)         Host=DESKTOP-5RA9F3K User=Adminuser Pid=39932 CPUs=20
+\t (00:00:05) CmdLine= D:\Cadence\SPB_17.2\tools\bin\Allegro.exe D:\HC-PMP-SW\Power_ControlPannel\MP_Control_sw_405\MP_SW_Chrg\chrg\docs\HC_DFCD_Protocol_V3_0.brd
+\t (00:00:05) 
+   (00:00:05) Loading axlcore.cxt 
+\t (00:00:06) Opening existing design...
+\i (00:00:06) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged HC_DFCD_Protocol_V3_0
+\d (00:00:06) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd
+\i (00:00:06) trapsize 8975
+\i (00:00:06) trapsize 9251
+\i (00:00:06) trapsize 9375
+\i (00:00:07) trapsize 8018
+\i (00:00:07) trapsize 8018
+\i (00:00:07) generaledit 
+\i (00:00:10) zoom out 1 
+\i (00:00:10) setwindow pcb
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+\i (00:00:10) zoom out 1 
+\i (00:00:10) setwindow pcb
+\i (00:00:10) zoom out 201.4873 63.2786
+\i (00:00:10) trapsize 32073
+\i (00:00:10) zoom out 1 
+\i (00:00:10) setwindow pcb
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+\i (00:00:22) zoom in 1 
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+\i (00:00:35) trapsize 353
+\i (00:00:36) zoom out 1 
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+\i (00:00:36) trapsize 707
+\i (00:00:36) zoom in 1 
+\i (00:00:36) setwindow pcb
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+\i (00:00:36) trapsize 353
+\i (00:00:37) zoom in 1 
+\i (00:00:37) setwindow pcb
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+\i (00:00:37) trapsize 177
+\i (00:00:37) zoom out 1 
+\i (00:00:37) setwindow pcb
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+\i (00:00:37) trapsize 353
+\i (00:00:37) zoom out 1 
+\i (00:00:37) setwindow pcb
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+\i (00:00:37) trapsize 707
+\i (00:00:37) zoom out 1 
+\i (00:00:37) setwindow pcb
+\i (00:00:37) zoom out 29.6741 45.0756
+\i (00:00:37) trapsize 1413
+\i (00:00:37) zoom out 1 
+\i (00:00:37) setwindow pcb
+\i (00:00:37) zoom out 29.6740 45.0756
+\i (00:00:37) trapsize 2827
+\i (00:00:38) zoom out 1 
+\i (00:00:38) setwindow pcb
+\i (00:00:38) zoom out 29.6741 45.5278
+\i (00:00:38) trapsize 5653
+\i (00:00:38) zoom in 1 
+\i (00:00:38) setwindow pcb
+\i (00:00:38) zoom in 29.6741 45.5277
+\i (00:00:38) trapsize 2827
+\i (00:00:38) zoom in 1 
+\i (00:00:38) setwindow pcb
+\i (00:00:38) zoom in 29.6741 45.3016
+\i (00:00:38) trapsize 1413
+\i (00:00:38) zoom in 1 
+\i (00:00:38) setwindow pcb
+\i (00:00:38) zoom in 29.7024 45.6973
+\i (00:00:38) trapsize 707
+\i (00:00:39) zoom in 1 
+\i (00:00:39) setwindow pcb
+\i (00:00:39) zoom in 29.5187 45.9376
+\i (00:00:39) trapsize 353
+\i (00:00:39) zoom in 1 
+\i (00:00:39) setwindow pcb
+\i (00:00:39) zoom in 29.5328 45.9023
+\i (00:00:39) trapsize 177
+\i (00:00:39) zoom out 1 
+\i (00:00:39) setwindow pcb
+\i (00:00:39) zoom out 29.6671 45.7186
+\i (00:00:39) trapsize 353
+\i (00:00:40) zoom out 1 
+\i (00:00:40) setwindow pcb
+\i (00:00:40) zoom out 29.9426 44.7011
+\i (00:00:40) trapsize 707
+\i (00:00:41) zoom out 1 
+\i (00:00:41) setwindow pcb
+\i (00:00:41) zoom out 29.6317 43.7825
+\i (00:00:41) trapsize 1413
+\i (00:00:41) zoom out 1 
+\i (00:00:41) setwindow pcb
+\i (00:00:41) zoom out 30.3384 42.8214
+\i (00:00:41) trapsize 2827
+\i (00:00:41) zoom out 1 
+\i (00:00:41) setwindow pcb
+\i (00:00:41) zoom out 30.1688 42.7083
+\i (00:00:41) trapsize 5653
+\i (00:00:41) zoom out 1 
+\i (00:00:41) setwindow pcb
+\i (00:00:41) zoom out 30.1689 42.7083
+\i (00:00:41) trapsize 11306
+\i (00:00:42) zoom out 1 
+\i (00:00:42) setwindow pcb
+\i (00:00:42) zoom out 26.0987 42.4822
+\i (00:00:42) trapsize 22612
+\i (00:00:42) zoom out 1 
+\i (00:00:42) setwindow pcb
+\i (00:00:42) zoom out 54.2149 41.5778
+\i (00:00:42) trapsize 45224
+\i (00:00:42) zoom out 1 
+\i (00:00:42) setwindow pcb
+\i (00:00:42) zoom out 208.4298 45.1957
+\i (00:00:42) trapsize 90449
+\i (00:00:42) zoom in 1 
+\i (00:00:42) setwindow pcb
+\i (00:00:42) zoom in 10.3473 3.5893
+\i (00:00:42) trapsize 45224
+\i (00:00:42) zoom in 1 
+\i (00:00:42) setwindow pcb
+\i (00:00:42) zoom in 10.3474 3.5893
+\i (00:00:42) trapsize 22612
+\i (00:00:42) zoom in 1 
+\i (00:00:42) setwindow pcb
+\i (00:00:42) zoom in 10.3474 3.5893
+\i (00:00:42) trapsize 11306
+\i (00:00:43) zoom in 1 
+\i (00:00:43) setwindow pcb
+\i (00:00:43) zoom in 10.3474 3.5894
+\i (00:00:43) trapsize 5653
+\i (00:00:43) zoom in 1 
+\i (00:00:43) setwindow pcb
+\i (00:00:43) zoom in 10.3474 3.5894
+\i (00:00:43) trapsize 2827
+\i (00:00:44) zoom out 1 
+\i (00:00:44) setwindow pcb
+\i (00:00:44) zoom out 12.0434 18.1178
+\i (00:00:44) trapsize 5653
+\i (00:00:44) zoom out 1 
+\i (00:00:44) setwindow pcb
+\i (00:00:44) zoom out 12.0433 18.0046
+\i (00:00:44) trapsize 11306
+\i (00:00:44) zoom in 1 
+\i (00:00:44) setwindow pcb
+\i (00:00:44) zoom in 19.0531 53.5058
+\i (00:00:44) trapsize 5653
+\i (00:00:45) zoom in 1 
+\i (00:00:45) setwindow pcb
+\i (00:00:45) zoom in 27.1935 45.5915
+\i (00:00:45) trapsize 2827
+\i (00:00:45) zoom in 1 
+\i (00:00:45) setwindow pcb
+\i (00:00:45) zoom in 27.1935 45.5916
+\i (00:00:45) trapsize 1413
+\i (00:00:46) zoom in 1 
+\i (00:00:46) setwindow pcb
+\i (00:00:46) zoom in 28.7481 45.3089
+\i (00:00:46) trapsize 707
+\i (00:03:01) zoom out 1 
+\i (00:03:01) setwindow pcb
+\i (00:03:01) zoom out 30.9669 43.6271
+\i (00:03:01) trapsize 1413
+\i (00:03:01) zoom out 1 
+\i (00:03:01) setwindow pcb
+\i (00:03:01) zoom out 30.6561 43.0619
+\i (00:03:01) trapsize 2827
+\i (00:03:01) zoom out 1 
+\i (00:03:01) setwindow pcb
+\i (00:03:01) zoom out 30.0342 41.6486
+\i (00:03:01) trapsize 5653
+\i (00:03:02) zoom in 1 
+\i (00:03:02) setwindow pcb
+\i (00:03:02) zoom in 14.8840 27.2898
+\i (00:03:02) trapsize 2827
+\i (00:03:02) zoom in 1 
+\i (00:03:02) setwindow pcb
+\i (00:03:02) zoom in 14.8840 27.2898
+\i (00:03:02) trapsize 1413
+\i (00:03:03) zoom out 1 
+\i (00:03:03) setwindow pcb
+\i (00:03:03) zoom out 15.1667 26.6680
+\i (00:03:03) trapsize 2827
+\i (00:03:03) zoom out 1 
+\i (00:03:03) setwindow pcb
+\i (00:03:03) zoom out 17.1452 27.7987
+\i (00:03:03) trapsize 5653
+\i (00:03:03) zoom out 1 
+\i (00:03:03) setwindow pcb
+\i (00:03:03) zoom out 17.1451 27.7986
+\i (00:03:03) trapsize 11306
+\i (00:03:06) zoom in 1 
+\i (00:03:06) setwindow pcb
+\i (00:03:06) zoom in 15.3362 29.1554
+\i (00:03:06) trapsize 5653
+\i (00:03:06) zoom in 1 
+\i (00:03:06) setwindow pcb
+\i (00:03:06) zoom in 15.5624 28.4770
+\i (00:03:06) trapsize 2827
+\i (00:03:06) zoom in 1 
+\i (00:03:06) setwindow pcb
+\i (00:03:06) zoom in 18.1062 28.3075
+\i (00:03:06) trapsize 1413
+\i (00:03:06) zoom in 1 
+\i (00:03:06) setwindow pcb
+\i (00:03:06) zoom in 18.2476 28.4489
+\i (00:03:06) trapsize 707
+\i (00:03:07) zoom out 1 
+\i (00:03:07) setwindow pcb
+\i (00:03:07) zoom out 18.9684 29.2686
+\i (00:03:07) trapsize 1413
+\i (00:03:07) zoom out 1 
+\i (00:03:07) setwindow pcb
+\i (00:03:07) zoom out 18.9684 29.2686
+\i (00:03:07) trapsize 2827
+\i (00:03:07) zoom out 1 
+\i (00:03:07) setwindow pcb
+\i (00:03:07) zoom out 21.1731 31.2472
+\i (00:03:07) trapsize 5653
+\i (00:03:08) zoom in 1 
+\i (00:03:08) setwindow pcb
+\i (00:03:08) zoom in 22.6430 41.1966
+\i (00:03:08) trapsize 2827
+\i (00:03:08) zoom in 1 
+\i (00:03:08) setwindow pcb
+\i (00:03:08) zoom in 24.7347 41.9315
+\i (00:03:08) trapsize 1413
+\i (00:03:09) zoom in 1 
+\i (00:03:09) setwindow pcb
+\i (00:03:09) zoom in 26.5154 42.4403
+\i (00:03:09) trapsize 707
+\i (00:03:09) zoom in 1 
+\i (00:03:09) setwindow pcb
+\i (00:03:09) zoom in 28.7202 42.9632
+\i (00:03:09) trapsize 353
+\i (00:03:10) zoom in 1 
+\i (00:03:10) setwindow pcb
+\i (00:03:10) zoom in 29.7448 42.5816
+\i (00:03:10) trapsize 177
+\i (00:03:10) zoom out 1 
+\i (00:03:10) setwindow pcb
+\i (00:03:10) zoom out 29.7130 42.5569
+\i (00:03:10) trapsize 353
+\i (00:03:17) zoom in 1 
+\i (00:03:17) setwindow pcb
+\i (00:03:17) zoom in 29.8615 43.1151
+\i (00:03:17) trapsize 177
+\i (00:03:17) zoom in 1 
+\i (00:03:17) setwindow pcb
+\i (00:03:17) zoom in 29.8615 43.1151
+\i (00:03:17) trapsize 88
+\i (00:03:17) zoom in 1 
+\i (00:03:17) setwindow pcb
+\i (00:03:17) zoom in 29.8615 43.1151
+\i (00:03:17) trapsize 44
+\i (00:03:17) zoom in 1 
+\i (00:03:17) setwindow pcb
+\i (00:03:17) zoom in 29.8615 43.1151
+\i (00:03:17) trapsize 22
+\i (00:03:17) zoom out 1 
+\i (00:03:17) setwindow pcb
+\i (00:03:17) zoom out 29.8606 43.1151
+\i (00:03:17) trapsize 44
+\i (00:03:17) zoom out 1 
+\i (00:03:17) setwindow pcb
+\i (00:03:17) zoom out 29.8526 43.1151
+\i (00:03:17) trapsize 88
+\i (00:03:17) zoom out 1 
+\i (00:03:17) setwindow pcb
+\i (00:03:17) zoom out 29.8525 43.1151
+\i (00:03:17) trapsize 177
+\i (00:03:17) zoom in 1 
+\i (00:03:17) setwindow pcb
+\i (00:03:17) zoom in 29.8525 43.1151
+\i (00:03:17) trapsize 88
+\i (00:03:17) zoom out 1 
+\i (00:03:17) setwindow pcb
+\i (00:03:17) zoom out 29.8525 43.1151
+\i (00:03:17) trapsize 177
+\i (00:03:18) zoom out 1 
+\i (00:03:18) setwindow pcb
+\i (00:03:18) zoom out 29.5840 43.1469
+\i (00:03:18) trapsize 353
+\i (00:03:18) zoom out 1 
+\i (00:03:18) setwindow pcb
+\i (00:03:18) zoom out 29.5841 43.1468
+\i (00:03:18) trapsize 707
+\i (00:03:19) zoom out 1 
+\i (00:03:19) setwindow pcb
+\i (00:03:19) zoom out 29.5841 43.1468
+\i (00:03:19) trapsize 1413
+\i (00:03:19) zoom in 1 
+\i (00:03:19) setwindow pcb
+\i (00:03:19) zoom in 29.0188 48.5735
+\i (00:03:19) trapsize 707
+\i (00:03:20) zoom in 1 
+\i (00:03:20) setwindow pcb
+\i (00:03:20) zoom in 29.1036 48.5736
+\i (00:03:20) trapsize 353
+\i (00:03:20) zoom out 1 
+\i (00:03:20) setwindow pcb
+\i (00:03:20) zoom out 29.8244 48.1284
+\i (00:03:20) trapsize 707
+\i (00:03:20) zoom out 1 
+\i (00:03:20) setwindow pcb
+\i (00:03:20) zoom out 29.8102 48.1002
+\i (00:03:20) trapsize 1413
+\i (00:03:20) zoom out 1 
+\i (00:03:20) setwindow pcb
+\i (00:03:20) zoom out 29.7820 47.9871
+\i (00:03:20) trapsize 2826
+\i (00:03:20) zoom out 1 
+\i (00:03:20) setwindow pcb
+\i (00:03:20) zoom out 25.5425 39.1688
+\i (00:03:20) trapsize 5653
+\i (00:03:20) zoom out 1 
+\i (00:03:20) setwindow pcb
+\i (00:03:20) zoom out 25.5424 38.2643
+\i (00:03:20) trapsize 11306
+\i (00:03:21) zoom in 1 
+\i (00:03:21) setwindow pcb
+\i (00:03:21) zoom in 14.8648 24.0193
+\i (00:03:21) trapsize 5653
+\i (00:03:21) zoom in 1 
+\i (00:03:21) setwindow pcb
+\i (00:03:21) zoom in 14.8648 24.0193
+\i (00:03:21) trapsize 2826
+\i (00:03:22) zoom in 1 
+\i (00:03:22) setwindow pcb
+\i (00:03:22) zoom in 13.3385 30.3504
+\i (00:03:22) trapsize 1413
+\i (00:03:22) zoom in 1 
+\i (00:03:22) setwindow pcb
+\i (00:03:22) zoom in 13.5929 30.4918
+\i (00:03:22) trapsize 707
+\i (00:03:22) zoom out 1 
+\i (00:03:22) setwindow pcb
+\i (00:03:22) zoom out 14.0169 31.5235
+\i (00:03:22) trapsize 1413
+\i (00:03:22) zoom out 1 
+\i (00:03:22) setwindow pcb
+\i (00:03:22) zoom out 14.0170 31.4952
+\i (00:03:22) trapsize 2826
+\i (00:03:22) zoom out 1 
+\i (00:03:22) setwindow pcb
+\i (00:03:22) zoom out 14.1865 30.8734
+\i (00:03:22) trapsize 5653
+\i (00:03:22) zoom out 1 
+\i (00:03:22) setwindow pcb
+\i (00:03:22) zoom out 14.4126 30.5342
+\i (00:03:22) trapsize 11306
+\i (00:03:23) zoom in 1 
+\i (00:03:23) setwindow pcb
+\i (00:03:23) zoom in 19.3871 42.0659
+\i (00:03:23) trapsize 5653
+\i (00:03:23) zoom in 1 
+\i (00:03:23) setwindow pcb
+\i (00:03:23) zoom in 19.1610 41.3876
+\i (00:03:23) trapsize 2826
+\i (00:03:24) zoom in 1 
+\i (00:03:24) setwindow pcb
+\i (00:03:24) zoom in 19.7263 38.7308
+\i (00:03:24) trapsize 1413
+\i (00:03:29) zoom out 1 
+\i (00:03:29) setwindow 
\ No newline at end of file
diff --git a/docs/HC_DFCD_Protocol_V3_0.brd b/docs/HC_DFCD_Protocol_V3_0.brd
new file mode 100644
index 0000000..8cd4f63
Binary files /dev/null and b/docs/HC_DFCD_Protocol_V3_0.brd differ
diff --git a/docs/HC_DFCD_Protocol_V3_0.brd.lck b/docs/HC_DFCD_Protocol_V3_0.brd.lck
new file mode 100644
index 0000000..242cccd
--- /dev/null
+++ b/docs/HC_DFCD_Protocol_V3_0.brd.lck
@@ -0,0 +1,6 @@
+# Allegro advisory lock file
+DATE=Tue Aug 25 19:43:27 2026
+USER=Adminuser
+HOST=DESKTOP-5RA9F3K
+PROGRAM=Allegro
+PID=39932
diff --git a/docs/修改日志.md b/docs/修改日志.md
index e6c1851..9aa269c 100644
--- a/docs/修改日志.md
+++ b/docs/修改日志.md
@@ -1,5 +1,12 @@
 # 修改日志
 
+## V1.1.9 - 2026-08-25
+
+### Source 复位后的初始化流程
+- 从其他协议切换到 PD 时复位加入断开CC，D+D-，GND逻辑，等断开后再复位，再初始化
+- 新增 `SOURCE_WORK_INIT_WAIT`，复位回码后重新执行 Source 初始化，并等待南向初始化批次完成。
+- 加入了读取版本号
+
 ## V1.1.8 - 2026-08-24
 
 ### 修改主题