From 1fe2ca7658e068e78a3fc4b29f9ddc3de96c052f Mon Sep 17 00:00:00 2001 From: wrh Date: Thu, 17 Sep 2026 11:19:23 +0800 Subject: [PATCH] =?UTF-8?q?fix:=20=E4=BF=AE=E5=A4=8D=E5=88=9D=E5=A7=8B?= =?UTF-8?q?=E5=8C=96=E6=89=B9=E6=AC=A1=E7=8A=B6=E6=80=81=E8=A2=AB=E5=8E=BB?= =?UTF-8?q?=E9=87=8D=E8=B7=B3=E8=BF=87=E7=9A=84=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1. apps/chrg/applications/utils/chrg_sink.c：更新初始化流程注释，调整状态判断条件，避免初始化批次被永久跳过 2. apps/chrg/applications/thread/chrg_comm.c：新增备份并恢复测试相关状态变量的逻辑，修复参数同步时状态丢失问题 3. docs/Allegro.jrl、docs/allegro.jrl,1：更新Cadence Allegro操作日志文件内容 --- apps/chrg/applications/thread/chrg_comm.c | 5 + docs/Allegro.jrl | 70 +++-------- docs/allegro.jrl,1 | 142 +++++++--------------- 3 files changed, 66 insertions(+), 151 deletions(-) diff --git a/apps/chrg/applications/thread/chrg_comm.c b/apps/chrg/applications/thread/chrg_comm.c index 14387f8..f8412ae 100644 --- a/apps/chrg/applications/thread/chrg_comm.c +++ b/apps/chrg/applications/thread/chrg_comm.c @@ -2646,6 +2646,11 @@ static eMBException chrg_comm_apply_sink_effect(rt_uint8_t ch, rt_uint16_t old_loadc = pReal->sink.loadc; rt_uint8_t old_on_work = pReal->sink.On_work; rt_uint8_t old_work_mode = pReal->sink.work_mode; + rt_uint8_t old_sub = pReal->sub; + rt_uint8_t old_test_mode_old = pReal->sink.test.test_mode_old; + rt_uint8_t old_test_run_flag = pReal->sink.test.run_flag; + rt_uint8_t old_test_work_step = pReal->sink.test.work_step; + rt_uint8_t old_test_stop_step = pReal->sink.test.stop_step; rt_bool_t old_test_or_load_active; rt_uint16_t sink_work = pShadow->sink.Now_State; chrg_param_diff_t diff_info; diff --git a/docs/Allegro.jrl b/docs/Allegro.jrl index 18239d2..76642e2 100644 --- a/docs/Allegro.jrl +++ b/docs/Allegro.jrl @@ -1,55 +1,15 @@ -\t (00:00:06) allegro 17.2 S079 Windows SPB 64-bit Edition -\t (00:00:06) Journal start - Tue Sep 15 20:16:48 2026 -\t (00:00:06) Host=DESKTOP-5RA9F3K User=Adminuser Pid=8232 CPUs=20 -\t (00:00:06) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe -\t (00:00:06) - (00:00:06) Loading axlcore.cxt -\t (00:00:07) Starting new design... -\i (00:00:09) trapsize 29310 -\i (00:00:10) generaledit -\i (00:00:18) xhilite -\i (00:00:18) xname_flush -\i (00:00:18) done -\i (00:00:19) generaledit -\i (00:00:33) xhilite -\i (00:00:34) xname_flush -\i (00:00:34) done -\i (00:00:34) generaledit -\i (00:20:00) exit -\e (00:20:00) Do you want to save the changes you made to unnamed.brd? -\i (12:51:55) fillin no -\t (12:51:56) Journal end - Wed Sep 16 09:08:37 2026 - -\i (00:00:13) generaledit -\i (00:00:14) zoom out 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom out 17.5318 56.5185 -\i (00:00:14) trapsize 5515 -\i (00:00:14) zoom out 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom out 21.9438 59.0553 -\i (00:00:14) trapsize 11030 -\i (00:00:14) zoom out 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom out 64.3442 57.9524 -\i (00:00:14) trapsize 22060 -\i (00:00:17) open -\i (00:00:20) fillin "menu_cancel" -\i (00:00:20) generaledit -\i (00:00:20) zoom in 1 -\i (00:00:20) setwindow pcb -\i (00:00:20) zoom in 19.5632 59.7117 -\i (00:00:20) trapsize 11030 -\i (00:00:20) zoom in 1 -\i (00:00:20) setwindow pcb -\i (00:00:20) zoom in 11.6217 57.0646 -\i (00:00:20) trapsize 5515 -\i (00:00:22) open -\i (00:00:26) fillin "menu_cancel" -\i (00:00:26) generaledit -\i (00:00:26) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "Start Page" -\i (00:00:28) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged HC_DFCD_Protocol_V3_0 -\i (00:00:28) opencd D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/south/HC_DFCD_Source_Eload_V1_1/PCB/HC_DFCD_Source_Eload_V1_1.brd -\t (00:00:28) Opening existing design... -\i (00:00:29) trapsize 283 -\t (00:00:29) Journal end - Tue Sep 15 20:17:15 2026 +\t (00:00:05) allegro 17.2 S079 Windows SPB 64-bit Edition +\t (00:00:05) Journal start - Wed Sep 16 22:17:09 2026 +\t (00:00:05) Host=DESKTOP-5RA9F3K User=Adminuser Pid=19892 CPUs=20 +\t (00:00:05) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe +\t (00:00:05) + (00:00:05) Loading axlcore.cxt +\t (00:00:06) Starting new design... +\i (00:00:06) trapsize 29310 +\i (00:00:07) generaledit +\i (00:00:08) trapsize 1230 +\i (00:00:08) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed +\i (00:00:08) opencd D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/south/HC_DFCD_Source_Eload_V1_1/PCB/HC_DFCD_Source_Eload_V1_1.brd +\t (00:00:08) Opening existing design... +\i (00:00:08) trapsize 283 +\t (00:00:08) Journal end - Wed Sep 16 22:17:12 2026 diff --git a/docs/allegro.jrl,1 b/docs/allegro.jrl,1 index b4d3f7f..18239d2 100644 --- a/docs/allegro.jrl,1 +++ b/docs/allegro.jrl,1 @@ -1,105 +1,55 @@ \t (00:00:06) allegro 17.2 S079 Windows SPB 64-bit Edition -\t (00:00:06) Journal start - Fri Sep 11 15:37:07 2026 -\t (00:00:06) Host=DESKTOP-5RA9F3K User=Adminuser Pid=13160 CPUs=20 +\t (00:00:06) Journal start - Tue Sep 15 20:16:48 2026 +\t (00:00:06) Host=DESKTOP-5RA9F3K User=Adminuser Pid=8232 CPUs=20 \t (00:00:06) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe \t (00:00:06) (00:00:06) Loading axlcore.cxt -\t (00:00:06) Starting new design... -\i (00:00:07) trapsize 29310 -\i (00:00:08) generaledit -\i (00:00:11) open -\i (00:00:12) fillin "HC_DFCD_Protocol_V3_0.brd" -\i (00:00:12) trapsize 1230 -\i (00:00:12) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed -\t (00:00:12) Opening existing design... -\i (00:00:12) trapsize 2757 -\d (00:00:12) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd +\t (00:00:07) Starting new design... +\i (00:00:09) trapsize 29310 +\i (00:00:10) generaledit +\i (00:00:18) xhilite +\i (00:00:18) xname_flush +\i (00:00:18) done +\i (00:00:19) generaledit +\i (00:00:33) xhilite +\i (00:00:34) xname_flush +\i (00:00:34) done +\i (00:00:34) generaledit +\i (00:20:00) exit +\e (00:20:00) Do you want to save the changes you made to unnamed.brd? +\i (12:51:55) fillin no +\t (12:51:56) Journal end - Wed Sep 16 09:08:37 2026 + \i (00:00:13) generaledit -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 27.8998 58.3935 -\i (00:00:13) trapsize 5515 -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 27.7896 58.0627 -\i (00:00:13) trapsize 11030 -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 96.9925 57.6215 -\i (00:00:13) trapsize 22060 -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 299.2792 77.8006 -\i (00:00:13) trapsize 44119 -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 710.9119 236.1887 -\i (00:00:13) trapsize 88239 -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 1546.5306 547.6707 -\i (00:00:13) trapsize 176477 -\i (00:00:14) zoom in 1 +\i (00:00:14) zoom out 1 \i (00:00:14) setwindow pcb -\i (00:00:14) zoom in 101.1838 -64.7046 -\i (00:00:14) trapsize 88239 -\i (00:00:14) zoom in 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom in 99.4190 -62.9398 -\i (00:00:14) trapsize 44119 -\i (00:00:14) zoom in 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom in 92.3600 -31.1739 -\i (00:00:14) trapsize 22060 -\i (00:00:14) zoom in 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom in 92.3600 -30.7327 -\i (00:00:14) trapsize 11030 -\i (00:00:14) zoom in 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom in 92.3600 -30.5121 +\i (00:00:14) zoom out 17.5318 56.5185 \i (00:00:14) trapsize 5515 -\i (00:00:15) drag_start grid 110.6695 -6.4671 -\i (00:00:15) drag_stop 188.9811 -20.1441 -\i (00:00:15) zoom out 1 -\i (00:00:15) setwindow pcb -\i (00:00:15) zoom out 102.1765 2.3567 -\i (00:00:15) trapsize 11030 -\i (00:00:15) zoom out 1 -\i (00:00:15) setwindow pcb -\i (00:00:15) zoom out 102.3972 1.6950 -\i (00:00:15) trapsize 22060 -\i (00:00:15) zoom out 1 -\i (00:00:15) setwindow pcb -\i (00:00:15) zoom out 104.6031 47.3583 -\i (00:00:15) trapsize 44119 -\i (00:00:16) zoom in 1 -\i (00:00:16) setwindow pcb -\i (00:00:16) zoom in -19.8131 37.6521 -\i (00:00:16) trapsize 22060 -\i (00:00:16) zoom in 1 -\i (00:00:16) setwindow pcb -\i (00:00:16) zoom in -5.2538 42.5053 -\i (00:00:16) trapsize 11030 -\i (00:00:16) zoom in 1 -\i (00:00:16) setwindow pcb -\i (00:00:16) zoom in -5.2537 42.7259 -\i (00:00:16) trapsize 5515 -\i (00:00:17) zoom in 1 -\i (00:00:17) setwindow pcb -\i (00:00:17) zoom in 48.1306 62.4692 -\i (00:00:17) trapsize 2757 +\i (00:00:14) zoom out 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom out 21.9438 59.0553 +\i (00:00:14) trapsize 11030 +\i (00:00:14) zoom out 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom out 64.3442 57.9524 +\i (00:00:14) trapsize 22060 +\i (00:00:17) open +\i (00:00:20) fillin "menu_cancel" +\i (00:00:20) generaledit \i (00:00:20) zoom in 1 \i (00:00:20) setwindow pcb -\i (00:00:20) zoom in 64.2893 72.1203 -\i (00:00:20) trapsize 1379 -\i (00:00:21) zoom out 1 -\i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 61.4492 70.2728 -\i (00:00:21) trapsize 2757 -\i (00:00:21) zoom out 1 -\i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 58.1402 66.3021 -\i (00:00:21) trapsize 5515 -\i (00:10:52) exit -\t (00:10:53) Journal end - Fri Sep 11 15:47:54 2026 +\i (00:00:20) zoom in 19.5632 59.7117 +\i (00:00:20) trapsize 11030 +\i (00:00:20) zoom in 1 +\i (00:00:20) setwindow pcb +\i (00:00:20) zoom in 11.6217 57.0646 +\i (00:00:20) trapsize 5515 +\i (00:00:22) open +\i (00:00:26) fillin "menu_cancel" +\i (00:00:26) generaledit +\i (00:00:26) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "Start Page" +\i (00:00:28) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged HC_DFCD_Protocol_V3_0 +\i (00:00:28) opencd D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/south/HC_DFCD_Source_Eload_V1_1/PCB/HC_DFCD_Source_Eload_V1_1.brd +\t (00:00:28) Opening existing design... +\i (00:00:29) trapsize 283 +\t (00:00:29) Journal end - Tue Sep 15 20:17:15 2026