From 8327cb3500d0f534e6890ace313997ba8070c5d4 Mon Sep 17 00:00:00 2001 From: wrh Date: Tue, 15 Sep 2026 20:51:50 +0800 Subject: [PATCH] =?UTF-8?q?=E5=BD=93=E5=89=8D=E7=89=88=E6=9C=AC=E5=AD=98?= =?UTF-8?q?=E5=9C=A8=E5=81=B6=E7=84=B6=E6=80=A7=E5=A4=B1=E8=B4=A5=E2=80=94?= =?UTF-8?q?=E2=80=94=E7=94=B5=E5=8E=8B=E5=88=B0=E4=BA=86=E4=B9=8B=E5=90=8E?= =?UTF-8?q?=E6=B2=A1=E7=94=B5=E6=B5=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1. apps/chrg/applications/thread/chrg_north.h: 更新版本号到V1.1.22 2. apps/chrg/applications/utils/chrg_eload.c: 清理冗余注释和调试打印代码 3. apps/chrg/applications/thread/chrg_comm.c: 更新版本号到V1.1.24，重构测试模式切换逻辑，新增优先级命令处理 4. apps/chrg/applications/thread/chrg_roll_sou.c: 新增优先级命令调度逻辑，优先处理测试停止/切换命令 5. apps/chrg/applications/utils/chrg_sink.c: 更新版本号到V1.1.24，重构初始化命令构建流程，新增初始化状态跟踪，增加调试打印开关 6. docs/Allegro.jrl和docs/allegro.jrl,1: 更新Allegro设计日志文件 --- apps/chrg/applications/thread/chrg_comm.c | 35 +- apps/chrg/applications/thread/chrg_north.h | 2 +- apps/chrg/applications/thread/chrg_roll_sou.c | 54 +- apps/chrg/applications/utils/chrg_eload.c | 18 +- apps/chrg/applications/utils/chrg_sink.c | 85 +- docs/Allegro.jrl | 144 +-- docs/allegro.jrl,1 | 1050 ++--------------- 7 files changed, 286 insertions(+), 1102 deletions(-) diff --git a/apps/chrg/applications/thread/chrg_comm.c b/apps/chrg/applications/thread/chrg_comm.c index b54d2bf..bc33f69 100644 --- a/apps/chrg/applications/thread/chrg_comm.c +++ b/apps/chrg/applications/thread/chrg_comm.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_comm.c 完成日期 : -当前版本号 : V1.1.23 +当前版本号 : V1.1.24 主要功能 : 实现对外通讯协议 MODBUS 服务端，以独立线程等待处理响应请求数据。 版本历史 : 创建原始版本 说明 : @@ -2571,6 +2571,7 @@ static eMBException chrg_comm_apply_sink_effect(rt_uint8_t ch, rt_uint16_t old_loadc = pReal->sink.loadc; rt_uint8_t old_on_work = pReal->sink.On_work; rt_uint8_t old_work_mode = pReal->sink.work_mode; + rt_bool_t old_test_or_load_active; rt_uint16_t sink_work = pShadow->sink.Now_State; chrg_param_diff_t diff_info; @@ -2610,9 +2611,31 @@ static eMBException chrg_comm_apply_sink_effect(rt_uint8_t ch, if (sink_work == 0x01) { curr_test = pReal->sink.test.test_mode; curr_test_old = pReal->sink.test.test_mode_old; - if (((curr_test_old == 0) && (curr_test != 0)) || - ((curr_test == 0) && (curr_test_old != 0))) { - if (curr_test_old == 0) { + old_test_or_load_active = (old_on_work == 1U) && + ((old_work_mode == SINK_WORK_RUNING) || + (old_work_mode == SINK_WORK_LOAD_STANDBY) || + (old_work_mode == SINK_WORK_ON_TEST_SHORT) || + (old_work_mode == SINK_WORK_ON_TEST_DYNA) || + (old_work_mode == SINK_WORK_ON_TEST_OCP)); + if (curr_test != curr_test_old) { + /* 测试模式切换优先清理旧批次，防止旧WORK_START插入新测试。 */ + if (chrg_sou_com_batch_cancel((eIDX_SOU_CH)ch) != 0) { + return MB_EX_SLAVE_BUSY; + } + if (curr_test == 0) { + /* Protocol-before-CC test flow is disabled in this version. */ + pReal->sub = IDX_SET_SINK_CC_BEFORE_PD; + pReal->sink.work_mode = SINK_WORK_INIT; + } else { + /* 普通负载或旧测试运行时，先停止电子负载再启动新测试。 */ + if (old_test_or_load_active) { + rt_uint16_t stop_reg = REG_WORK; + rt_uint16_t stop_val = WORK_STOP; + if (chrg_sou_com_batch_submit((eIDX_SOU_CH)ch, + &stop_reg, &stop_val, 1U) != 0) { + return MB_EX_SLAVE_BUSY; + } + } if (curr_test == SINK_TEST_DYNA) { pReal->sink.work_mode = SINK_WORK_ON_TEST_DYNA; } else if (curr_test == SINK_TEST_OCP) { @@ -2621,10 +2644,6 @@ static eMBException chrg_comm_apply_sink_effect(rt_uint8_t ch, pReal->sink.work_mode = SINK_WORK_ON_TEST_SHORT; } pReal->sink.test.test_mode_old = curr_test; - } else { - /* Protocol-before-CC test flow is disabled in this version. */ - pReal->sub = IDX_SET_SINK_CC_BEFORE_PD; - pReal->sink.work_mode = SINK_WORK_INIT; } } else if (pReal->sink.On_work == 0) { pReal->sink.On_work = 1; diff --git a/apps/chrg/applications/thread/chrg_north.h b/apps/chrg/applications/thread/chrg_north.h index 4c555e7..1201fa3 100644 --- a/apps/chrg/applications/thread/chrg_north.h +++ b/apps/chrg/applications/thread/chrg_north.h @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_north.h 完成日期 : -当前版本号 : V1.1.21 +当前版本号 : V1.1.22 主要功能 : 实现北向通信交互，包括接收命令解析，发送请求命令，切换通路。以独立线程处理。 版本历史 : 创建原始版本 说明 : diff --git a/apps/chrg/applications/thread/chrg_roll_sou.c b/apps/chrg/applications/thread/chrg_roll_sou.c index 3cf71bd..9546fdf 100644 --- a/apps/chrg/applications/thread/chrg_roll_sou.c +++ b/apps/chrg/applications/thread/chrg_roll_sou.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_roll_sou.c 完成日期 : -当前版本号 : V1.1.22 +当前版本号 : V1.1.23 主要功能 : 实现南向通信轮巡请求命令。以独立线程处理。 版本历史 : 创建原始版本 说明 : @@ -49,6 +49,37 @@ static rt_uint8_t g_sou_com_batch_rr_next_ch = 0U; static rt_uint8_t g_sou_com_batch_burst_ch = TOTAL_SOU_CHS; static rt_uint8_t g_sou_com_batch_burst_count = 0U; +static rt_bool_t sou_com_batch_is_priority(rt_uint8_t ch, + sou_com_batch_ch_t *pBatch) +{ + rt_uint16_t reg; + rt_uint16_t value; + + if ((ch >= TOTAL_SOU_CHS) || (pBatch == RT_NULL) || + (pBatch->cur_idx >= pBatch->reg_cnt)) { + return RT_FALSE; + } + reg = pBatch->reg_list[pBatch->cur_idx]; + value = pBatch->val_list[pBatch->cur_idx]; + if ((reg == REG_WORK) && (value == WORK_STOP)) { + return RT_TRUE; + } + if ((reg == ModbusRTU_ShortTest_CMD_MODE_FLAG) && + (value == ModbusRTU_DYNA_CMD_MODE_STOP)) { + return RT_TRUE; + } + if ((reg == REG_REL_ON) && (value == ALL_REL_OFF)) { + return RT_TRUE; + } + if ((reg == REG_WORK) && (value == WORK_START) && + (chrgnorth.sw[ch].sink.work_mode == SINK_WORK_ON_TEST_SHORT || + chrgnorth.sw[ch].sink.work_mode == SINK_WORK_ON_TEST_DYNA || + chrgnorth.sw[ch].sink.work_mode == SINK_WORK_ON_TEST_OCP)) { + return RT_TRUE; + } + return RT_FALSE; +} + struct chrg_rollsou_t chrgrollsou = { .run = RUN_AUTO, .ch = IDX_SOU_CH1, @@ -538,6 +569,25 @@ static int sou_com_batch_next(rt_uint8_t *ch, rt_uint16_t *reg, rt_uint16_t *val } now = rt_tick_get(); + /* 测试切换和停止命令先执行，避免被其它通道的长测试批次拖延。 */ + for (offset = 0; offset < TOTAL_SOU_CHS; offset++) { + idx = (rt_uint8_t)((g_sou_com_batch_rr_next_ch + offset) % + TOTAL_SOU_CHS); + sou_com_batch_ch_t *pBatch = &g_sou_com_batch.ch[idx]; + if ((pBatch->pending != RT_TRUE) || + (pBatch->cur_idx >= pBatch->reg_cnt) || + !sou_com_batch_is_priority(idx, pBatch) || + ((pBatch->next_send_tick != 0U) && + ((rt_int32_t)(now - pBatch->next_send_tick) < 0))) { + continue; + } + pBatch->next_send_tick = 0U; + *ch = idx; + *reg = pBatch->reg_list[pBatch->cur_idx]; + *value = pBatch->val_list[pBatch->cur_idx]; + rt_mutex_release(pTHR->mutex); + return 1; + } /* 短路保活的WORK_START达到周期后优先下发，避免长批次挤占30ms保活窗口。 */ for (offset = 0; offset < TOTAL_SOU_CHS; offset++) { idx = (rt_uint8_t)((g_sou_com_batch_rr_next_ch + offset) % @@ -927,7 +977,9 @@ void chrg_roll_sou_thread_entry (void *data) batch_ch = command_ch; command_valid = RT_TRUE; chrg_south_switch((eIDX_SOU_CH)command_ch); + #if SOUTH_COMMAND_DEBUG rt_kprintf("ch=%d",command_ch); + #endif chrg_eload_write_reg(ID_ELOAD, command_reg, command_value); } break; diff --git a/apps/chrg/applications/utils/chrg_eload.c b/apps/chrg/applications/utils/chrg_eload.c index 30f8a39..f3f6550 100644 --- a/apps/chrg/applications/utils/chrg_eload.c +++ b/apps/chrg/applications/utils/chrg_eload.c @@ -407,7 +407,6 @@ int chrg_eload_parse_version (rt_uint8_t idx, rt_uint8_t *data, rt_uint16_t len) { rt_uint16_t version; - /* A one-register Modbus 0x03 response is 7 bytes including CRC16. */ if ((idx >= TOTAL_SOU_CHS) || (data == RT_NULL) || (len != (MODBUSRTU_SW_VERSION_LEN * 2U + 5U)) || (data[0] != ID_ELOAD) || (data[1] != MB_REGISTER_RD) || @@ -416,7 +415,7 @@ int chrg_eload_parse_version (rt_uint8_t idx, rt_uint8_t *data, rt_uint16_t len) } version = u8v_to_u16(&data[3]); - /* HOLD_REG_CH0_VERSION is the per-channel south board version register. */ + usRegHoldBuf[HOLD_REG_CH0_VERSION + idx * TOTAL_HOLD_CH_REGS] = version; return 0; } @@ -443,9 +442,7 @@ int chrg_eload_parse (rt_uint8_t idx, rt_uint8_t pt, rt_uint8_t *data, rt_uint16 return -1; } struct eload_p1_t *pP1 = (struct eload_p1_t *)&data[3]; -// for(int i = 0;i<36;i++){ -// rt_kprintf("%02x ",data[i+3]); -// } + pLOAD->status1 = pP1->status1; pLOAD->status2 = pP1->status2; pLOAD->fault1 = pP1->fault1; @@ -465,6 +462,8 @@ int chrg_eload_parse (rt_uint8_t idx, rt_uint8_t pt, rt_uint8_t *data, rt_uint16 pLOAD->vpp = swap_u16(pP1->Vpp); pLOAD->Ripple = chrg_eload_ripple_filter_update(idx, swap_u16(pP1->Ripple)); +// if(idx == IDX_CH3) +// rt_kprintf("-----Ripple = %d-------\n",pLOAD->Ripple); /* 保留功率板返回的真实电流，供卸载保护判断使用。 */ pSW->Now_current = pLOAD->current; /* @@ -486,14 +485,6 @@ int chrg_eload_parse (rt_uint8_t idx, rt_uint8_t pt, rt_uint8_t *data, rt_uint16 /* 电压、电流均更新完成后再发布序号，避免状态机读取到半更新数据。 */ g_eload_sample_seq[idx]++; #if LCD_OPEN -// for(int i = 0;i<4;i++){ -// if(pNOR->sw[i].change_flag == 0x01){ -// pNOR->free_flag = 0x00; -// }else { -// pNOR->free_flag = 0x01; -// } -// } -// rt_kprintf("ch=%d,free_flag=%d,",idx,pNOR->free_flag); if(pNOR->free_flag==0x01){ LCD_SHOW(idx, pP1, pLOAD, pSW, pSOU->online[idx]); } @@ -525,7 +516,6 @@ int chrg_eload_parse (rt_uint8_t idx, rt_uint8_t pt, rt_uint8_t *data, rt_uint16 chrg_eload_dpdm_host_value(pSW->VZ); usRegHoldBuf[HOLD_REG_CH0_VF+idx*TOTAL_HOLD_CH_REGS] = chrg_eload_dpdm_host_value(pSW->VF); -// rt_kprintf("---------NOW VOLT END = %d\n----------",pSW->Now_voltage); return 0; } diff --git a/apps/chrg/applications/utils/chrg_sink.c b/apps/chrg/applications/utils/chrg_sink.c index 1e8d53d..fa2cdda 100644 --- a/apps/chrg/applications/utils/chrg_sink.c +++ b/apps/chrg/applications/utils/chrg_sink.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_sink.c 完成日期 : -当前版本号 : V1.1.21 +当前版本号 : V1.1.24 主要功能 : 北向数据sink请求数据填充及发送。 版本历史 : 创建原始版本 说明 : @@ -33,6 +33,7 @@ static rt_uint8_t g_sink_init_stage[TOTAL_SOU_CHS] = {0}; static rt_tick_t g_sink_init_north_relay_tick[TOTAL_SOU_CHS] = {0}; +static rt_bool_t g_sink_init_in_progress[TOTAL_SOU_CHS] = {RT_FALSE}; /* 主继电器闭合跟踪：1=已提交ALL_REL_ON（主继电器应已闭合） 0=未闭合/已断开。 * 用于0V硬保护区分"首次开载/握手恢复"（主继电器未闭合，Now_voltage=0属正常） @@ -255,22 +256,22 @@ static rt_uint8_t chrg_sink_init_build_commands(struct chrg_switch_t *pSW, { rt_uint8_t count; + regs[0] = ModbusRTU_ShortTest_CMD_MODE_FLAG; + vals[0] = ModbusRTU_DYNA_CMD_MODE_STOP; if (pSW->sink.test.test_mode_old == SINK_TEST_SHORT) { - regs[0] = REG_REL_ON; vals[0] = ALL_REL_OFF; - regs[1] = REG_REL_ON; vals[1] = FU_REL_ON; - regs[2] = REG_CURRENT_OUT + 1; vals[2] = 0; - regs[3] = REG_MODE; vals[3] = pSW->CV_mode; - regs[4] = Eload_Start_V_ON; vals[4] = (pSW->sink.volt_on <= 500) ? 500 : pSW->sink.volt_on; - regs[5] = ModbusRTU_ShortTest_CMD_MODE_FLAG; - vals[5] = ModbusRTU_DYNA_CMD_MODE_STOP; + regs[1] = REG_REL_ON; vals[1] = ALL_REL_OFF; + regs[2] = REG_REL_ON; vals[2] = FU_REL_ON; + regs[3] = REG_CURRENT_OUT + 1; vals[3] = 0; + regs[4] = REG_MODE; vals[4] = pSW->CV_mode; + regs[5] = Eload_Start_V_ON; vals[5] = (pSW->sink.volt_on <= 500) ? 500 : pSW->sink.volt_on; count = 6U; } else { - regs[0] = REG_REL_ON; vals[0] = FU_REL_ON; - regs[1] = REG_CURRENT_OUT + 1; vals[1] = 0; - regs[2] = REG_MODE; vals[2] = pSW->CV_mode; - regs[3] = Eload_Start_V_ON; vals[3] = + regs[1] = REG_REL_ON; vals[1] = FU_REL_ON; + regs[2] = REG_CURRENT_OUT + 1; vals[2] = 0; + regs[3] = REG_MODE; vals[3] = pSW->CV_mode; + regs[4] = Eload_Start_V_ON; vals[4] = (pSW->sink.volt_on <= 500) ? 500 : pSW->sink.volt_on; - count = 4U; + count = 5U; if (pSW->sink.test.test_mode_old == SINK_TEST_OCP) { regs[count] = ModbusRTU_OCPTest_CMD_MODE_FLAG; vals[count++] = ModbusRTU_DYNA_CMD_MODE_STOP; @@ -290,14 +291,11 @@ static int chrg_sink_init_submit_stage(eIDX_SOU_CH idx, rt_uint8_t total; rt_uint8_t start; rt_uint8_t count; - rt_bool_t short_exit; if ((idx >= TOTAL_SOU_CHS) || (pSW == RT_NULL)) { return -1; } total = chrg_sink_init_build_commands(pSW, regs, vals); - short_exit = (pSW->sink.test.test_mode_old == SINK_TEST_SHORT) ? - RT_TRUE : RT_FALSE; switch (g_sink_init_stage[idx]) { case SINK_INIT_STAGE_CLEAR_RELAY: @@ -305,12 +303,12 @@ static int chrg_sink_init_submit_stage(eIDX_SOU_CH idx, count = 1U; break; case SINK_INIT_STAGE_AUX_RELAY: - start = short_exit ? 1U : 0U; + start = 1U; count = 1U; break; case SINK_INIT_STAGE_REST: - start = short_exit ? 2U : 1U; - count = (rt_uint8_t)(total - start); + start = 2U; + count = (rt_uint8_t)(total - 2U); break; default: return -1; @@ -320,23 +318,23 @@ static int chrg_sink_init_submit_stage(eIDX_SOU_CH idx, /***************************************************************** 函数名称： chrg_sink_work_init -函数描述： 执行负载INIT入口，先提交辅助继电器命令 +函数描述： 执行负载INIT入口，首帧先退出短路测试 输入参数： idx:南向功率通道编号 pSW:当前通道控制结构体 -输出参数： 进入INIT_AUX_WAIT后台等待辅助继电器回码 +输出参数： 进入INIT_AUX_WAIT后台等待南向回码 返回说明： 0:初始化命令提交成功 <0:参数或命令提交失败 其它说明： 收到01 02有效回码后等待30ms，再打开北向Sink继电器 *****************************************************************/ static int chrg_sink_work_init(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) { - rt_bool_t short_exit; - if ((idx >= TOTAL_SOU_CHS) || (pSW == RT_NULL)) { return -1; } - short_exit = (pSW->sink.test.test_mode_old == SINK_TEST_SHORT) ? - RT_TRUE : RT_FALSE; - g_sink_init_stage[idx] = short_exit ? SINK_INIT_STAGE_CLEAR_RELAY : - SINK_INIT_STAGE_AUX_RELAY; + /* 初始化必须优先于本通道尚未发送的旧命令，避免旧WORK_START插入初始化流程。 */ + if (chrg_sou_com_batch_cancel(idx) != 0) { + return -1; + } + g_sink_init_in_progress[idx] = RT_TRUE; + g_sink_init_stage[idx] = SINK_INIT_STAGE_CLEAR_RELAY; g_sink_init_north_relay_tick[idx] = 0U; if (chrg_sink_init_submit_stage(idx, pSW) != 0) { return -1; @@ -374,7 +372,9 @@ static int chrg_sink_work_init_aux_wait(eIDX_SOU_CH idx, return 0; } chrg_nor_sw_rel((eIDX_NOR_CH)idx, ID_SINK); + #if SOUTH_COMMAND_DEBUG rt_kprintf("-------D+D- OPEN------\n"); + #endif pNOR->enable[idx] = 1; pSW->sub = IDX_SET_SINK_CC_BEFORE_PD; g_sink_init_stage[idx] = SINK_INIT_STAGE_REST; @@ -399,6 +399,7 @@ static int chrg_sink_work_init_aux_wait(eIDX_SOU_CH idx, } /* 北向可能已推进到CC或电压查询，此处只更新南向完成状态。 */ + g_sink_init_in_progress[idx] = RT_FALSE; pSOU->online[idx] = 1; pSW->sink.test.test_mode_old = 0; pSW->sink.work_mode = SINK_WORK_WAIT; @@ -492,6 +493,9 @@ static int chrg_sink_work_volt_runing(eIDX_SOU_CH idx, struct chrg_switch_t *pSW } /* RUNING批次必须完整发送：ALL_REL_ON、目标负载值、WORK_START。 */ ret = chrg_sou_com_batch_submit(idx, regs, vals, 3U); + #if SOUTH_COMMAND_DEBUG + rt_kprintf("------ALL_REL_ON-------\n"); + #endif if (ret == 0) { g_sink_rel_main_closed[idx] = 1; } @@ -517,6 +521,7 @@ static int chrg_sink_work_load_stop(eIDX_SOU_CH idx, return -1; } /* 自动停止优先于同通道残留启动批次，禁止STOP后继续发送WORK_START。 */ + g_sink_init_in_progress[idx] = RT_FALSE; if (chrg_sou_com_batch_cancel(idx) != 0) { return -1; } @@ -568,6 +573,7 @@ static int chrg_sink_nor_work_low(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) return -1; } /* 低压保护优先级最高，先丢弃该通道残留的启动或设定命令。 */ + g_sink_init_in_progress[idx] = RT_FALSE; if (chrg_sou_com_batch_cancel(idx) != 0) { return -1; } @@ -629,6 +635,7 @@ static int chrg_sink_work_stop_prepare(eIDX_SOU_CH idx, if ((idx >= TOTAL_SOU_CHS) || (pSW == RT_NULL)) { return -1; } + g_sink_init_in_progress[idx] = RT_FALSE; if (chrg_sou_com_batch_cancel(idx) != 0) { return -1; } @@ -918,8 +925,9 @@ static int chrg_sink_TEST_DYNA_ON(rt_uint8_t ch, struct chrg_switch_t *pSW) *****************************************************************/ static int chrg_sink_TEST_SHORT_ON(rt_uint8_t ch, struct chrg_switch_t *pSW) { - rt_uint16_t regs[4] = {Eload_Start_V_ON, ModbusRTU_ShortTest_Hold_Time, - ModbusRTU_ShortTest_CMD_MODE_FLAG, REG_WORK}; + rt_uint16_t regs[4] = {Eload_Start_V_ON, + ModbusRTU_ShortTest_Hold_Time, ModbusRTU_ShortTest_CMD_MODE_FLAG, + REG_WORK}; rt_uint16_t vals[4] = {SINK_SHORT_TEST_VON_MV, 0, 0, 0}; /* 外部工程固定短路测试保持60秒且不带载。 */ vals[1] = 60000; @@ -995,6 +1003,18 @@ int chrg_sink_volt_judge(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) if ((idx >= TOTAL_SOU_CHS) || (pSW == RT_NULL)) { return -1; } + /* 初始化及短路退出批次完成前，禁止电压判定提前启动普通负载。 */ + if (g_sink_init_in_progress[idx] || + (pSW->sink.work_mode == SINK_WORK_INIT) || + (pSW->sink.work_mode == SINK_WORK_INIT_AUX_WAIT)) { + if (g_sink_init_in_progress[idx] && + (pSW->sink.work_mode != SINK_WORK_INIT) && + (pSW->sink.work_mode != SINK_WORK_INIT_AUX_WAIT)) { + pSW->sink.work_mode = SINK_WORK_INIT_AUX_WAIT; + } + return chrg_sink_work(idx, pSW); + } + #if SINK_VON_VOLTAGE_SOURCE == SINK_VON_VOLTAGE_FROM_PROTOCOL voltage_seq = pSW->Sink_voltage_seq; #else @@ -1171,6 +1191,13 @@ int chrg_sink_work(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) } work_mode = pSW->sink.work_mode; workmode = work_mode; + /* 初始化事务独占该通道，防止其它路径改成RUNING后追加普通启动命令。 */ + if (g_sink_init_in_progress[idx] && + (work_mode != SINK_WORK_INIT) && + (work_mode != SINK_WORK_INIT_AUX_WAIT)) { + pSW->sink.work_mode = SINK_WORK_INIT_AUX_WAIT; + work_mode = SINK_WORK_INIT_AUX_WAIT; + } if (work_mode != SINK_WORK_ON_TEST_SHORT) { g_sink_short_start_tick[idx] = 0; } diff --git a/docs/Allegro.jrl b/docs/Allegro.jrl index b4d3f7f..6496f36 100644 --- a/docs/Allegro.jrl +++ b/docs/Allegro.jrl @@ -1,105 +1,49 @@ -\t (00:00:06) allegro 17.2 S079 Windows SPB 64-bit Edition -\t (00:00:06) Journal start - Fri Sep 11 15:37:07 2026 -\t (00:00:06) Host=DESKTOP-5RA9F3K User=Adminuser Pid=13160 CPUs=20 -\t (00:00:06) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe -\t (00:00:06) - (00:00:06) Loading axlcore.cxt -\t (00:00:06) Starting new design... -\i (00:00:07) trapsize 29310 -\i (00:00:08) generaledit -\i (00:00:11) open -\i (00:00:12) fillin "HC_DFCD_Protocol_V3_0.brd" -\i (00:00:12) trapsize 1230 -\i (00:00:12) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed -\t (00:00:12) Opening existing design... -\i (00:00:12) trapsize 2757 -\d (00:00:12) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd +\t (00:00:01) allegro 17.2 S079 Windows SPB 64-bit Edition +\t (00:00:01) Journal start - Tue Sep 15 20:16:48 2026 +\t (00:00:01) Host=DESKTOP-5RA9F3K User=Adminuser Pid=20076 CPUs=20 +\t (00:00:01) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe +\t (00:00:01) + (00:00:01) Loading axlcore.cxt +\t (00:00:02) Starting new design... +\i (00:00:04) trapsize 29310 +\i (00:00:05) generaledit +\i (00:00:12) open +\i (00:00:13) fillin "HC_DFCD_Protocol_V3_0.brd" +\i (00:00:13) trapsize 1230 +\i (00:00:13) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed +\t (00:00:13) Opening existing design... +\i (00:00:13) trapsize 2757 +\d (00:00:13) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd \i (00:00:13) generaledit -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 27.8998 58.3935 -\i (00:00:13) trapsize 5515 -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 27.7896 58.0627 -\i (00:00:13) trapsize 11030 -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 96.9925 57.6215 -\i (00:00:13) trapsize 22060 -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 299.2792 77.8006 -\i (00:00:13) trapsize 44119 -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 710.9119 236.1887 -\i (00:00:13) trapsize 88239 -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 1546.5306 547.6707 -\i (00:00:13) trapsize 176477 -\i (00:00:14) zoom in 1 +\i (00:00:14) zoom out 1 \i (00:00:14) setwindow pcb -\i (00:00:14) zoom in 101.1838 -64.7046 -\i (00:00:14) trapsize 88239 -\i (00:00:14) zoom in 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom in 99.4190 -62.9398 -\i (00:00:14) trapsize 44119 -\i (00:00:14) zoom in 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom in 92.3600 -31.1739 -\i (00:00:14) trapsize 22060 -\i (00:00:14) zoom in 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom in 92.3600 -30.7327 -\i (00:00:14) trapsize 11030 -\i (00:00:14) zoom in 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom in 92.3600 -30.5121 +\i (00:00:14) zoom out 17.5318 56.5185 \i (00:00:14) trapsize 5515 -\i (00:00:15) drag_start grid 110.6695 -6.4671 -\i (00:00:15) drag_stop 188.9811 -20.1441 -\i (00:00:15) zoom out 1 -\i (00:00:15) setwindow pcb -\i (00:00:15) zoom out 102.1765 2.3567 -\i (00:00:15) trapsize 11030 -\i (00:00:15) zoom out 1 -\i (00:00:15) setwindow pcb -\i (00:00:15) zoom out 102.3972 1.6950 -\i (00:00:15) trapsize 22060 -\i (00:00:15) zoom out 1 -\i (00:00:15) setwindow pcb -\i (00:00:15) zoom out 104.6031 47.3583 -\i (00:00:15) trapsize 44119 -\i (00:00:16) zoom in 1 -\i (00:00:16) setwindow pcb -\i (00:00:16) zoom in -19.8131 37.6521 -\i (00:00:16) trapsize 22060 -\i (00:00:16) zoom in 1 -\i (00:00:16) setwindow pcb -\i (00:00:16) zoom in -5.2538 42.5053 -\i (00:00:16) trapsize 11030 -\i (00:00:16) zoom in 1 -\i (00:00:16) setwindow pcb -\i (00:00:16) zoom in -5.2537 42.7259 -\i (00:00:16) trapsize 5515 -\i (00:00:17) zoom in 1 -\i (00:00:17) setwindow pcb -\i (00:00:17) zoom in 48.1306 62.4692 -\i (00:00:17) trapsize 2757 +\i (00:00:14) zoom out 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom out 21.9438 59.0553 +\i (00:00:14) trapsize 11030 +\i (00:00:14) zoom out 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom out 64.3442 57.9524 +\i (00:00:14) trapsize 22060 +\i (00:00:17) open +\i (00:00:20) fillin "menu_cancel" +\i (00:00:20) generaledit \i (00:00:20) zoom in 1 \i (00:00:20) setwindow pcb -\i (00:00:20) zoom in 64.2893 72.1203 -\i (00:00:20) trapsize 1379 -\i (00:00:21) zoom out 1 -\i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 61.4492 70.2728 -\i (00:00:21) trapsize 2757 -\i (00:00:21) zoom out 1 -\i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 58.1402 66.3021 -\i (00:00:21) trapsize 5515 -\i (00:10:52) exit -\t (00:10:53) Journal end - Fri Sep 11 15:47:54 2026 +\i (00:00:20) zoom in 19.5632 59.7117 +\i (00:00:20) trapsize 11030 +\i (00:00:20) zoom in 1 +\i (00:00:20) setwindow pcb +\i (00:00:20) zoom in 11.6217 57.0646 +\i (00:00:20) trapsize 5515 +\i (00:00:22) open +\i (00:00:26) fillin "menu_cancel" +\i (00:00:26) generaledit +\i (00:00:26) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "Start Page" +\i (00:00:28) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged HC_DFCD_Protocol_V3_0 +\i (00:00:28) opencd D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/south/HC_DFCD_Source_Eload_V1_1/PCB/HC_DFCD_Source_Eload_V1_1.brd +\t (00:00:28) Opening existing design... +\i (00:00:29) trapsize 283 +\t (00:00:29) Journal end - Tue Sep 15 20:17:15 2026 diff --git a/docs/allegro.jrl,1 b/docs/allegro.jrl,1 index f472350..b4d3f7f 100644 --- a/docs/allegro.jrl,1 +++ b/docs/allegro.jrl,1 @@ -1,953 +1,105 @@ -\t (00:00:02) allegro 17.2 S079 Windows SPB 64-bit Edition -\t (00:00:02) Journal start - Wed Aug 26 11:20:30 2026 -\t (00:00:02) Host=DESKTOP-5RA9F3K User=Adminuser Pid=37292 CPUs=20 -\t (00:00:02) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe -\t (00:00:02) - (00:00:02) Loading axlcore.cxt -\t (00:00:03) Starting new design... -\i (00:00:04) trapsize 29310 -\i (00:00:04) generaledit -\i (00:00:16) open -\i (00:00:19) fillin "HC_DFCD_Protocol_V3_0.brd" -\i (00:00:19) trapsize 1230 -\i (00:00:19) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed -\t (00:00:19) Opening existing design... -\i (00:00:20) trapsize 8018 -\d (00:00:20) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd -\i (00:00:20) generaledit -\i (00:00:21) zoom in 1 -\i (00:00:21) setwindow pcb -\i (00:00:21) zoom in 9.3881 57.0243 -\i (00:00:21) trapsize 4009 -\i (00:00:21) zoom in 1 -\i (00:00:21) setwindow pcb -\i (00:00:21) zoom in 9.3881 57.1046 -\i (00:00:21) trapsize 2005 +\t (00:00:06) allegro 17.2 S079 Windows SPB 64-bit Edition +\t (00:00:06) Journal start - Fri Sep 11 15:37:07 2026 +\t (00:00:06) Host=DESKTOP-5RA9F3K User=Adminuser Pid=13160 CPUs=20 +\t (00:00:06) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe +\t (00:00:06) + (00:00:06) Loading axlcore.cxt +\t (00:00:06) Starting new design... +\i (00:00:07) trapsize 29310 +\i (00:00:08) generaledit +\i (00:00:11) open +\i (00:00:12) fillin "HC_DFCD_Protocol_V3_0.brd" +\i (00:00:12) trapsize 1230 +\i (00:00:12) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed +\t (00:00:12) Opening existing design... +\i (00:00:12) trapsize 2757 +\d (00:00:12) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd +\i (00:00:13) generaledit +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 27.8998 58.3935 +\i (00:00:13) trapsize 5515 +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 27.7896 58.0627 +\i (00:00:13) trapsize 11030 +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 96.9925 57.6215 +\i (00:00:13) trapsize 22060 +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 299.2792 77.8006 +\i (00:00:13) trapsize 44119 +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 710.9119 236.1887 +\i (00:00:13) trapsize 88239 +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 1546.5306 547.6707 +\i (00:00:13) trapsize 176477 +\i (00:00:14) zoom in 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom in 101.1838 -64.7046 +\i (00:00:14) trapsize 88239 +\i (00:00:14) zoom in 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom in 99.4190 -62.9398 +\i (00:00:14) trapsize 44119 +\i (00:00:14) zoom in 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom in 92.3600 -31.1739 +\i (00:00:14) trapsize 22060 +\i (00:00:14) zoom in 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom in 92.3600 -30.7327 +\i (00:00:14) trapsize 11030 +\i (00:00:14) zoom in 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom in 92.3600 -30.5121 +\i (00:00:14) trapsize 5515 +\i (00:00:15) drag_start grid 110.6695 -6.4671 +\i (00:00:15) drag_stop 188.9811 -20.1441 +\i (00:00:15) zoom out 1 +\i (00:00:15) setwindow pcb +\i (00:00:15) zoom out 102.1765 2.3567 +\i (00:00:15) trapsize 11030 +\i (00:00:15) zoom out 1 +\i (00:00:15) setwindow pcb +\i (00:00:15) zoom out 102.3972 1.6950 +\i (00:00:15) trapsize 22060 +\i (00:00:15) zoom out 1 +\i (00:00:15) setwindow pcb +\i (00:00:15) zoom out 104.6031 47.3583 +\i (00:00:15) trapsize 44119 +\i (00:00:16) zoom in 1 +\i (00:00:16) setwindow pcb +\i (00:00:16) zoom in -19.8131 37.6521 +\i (00:00:16) trapsize 22060 +\i (00:00:16) zoom in 1 +\i (00:00:16) setwindow pcb +\i (00:00:16) zoom in -5.2538 42.5053 +\i (00:00:16) trapsize 11030 +\i (00:00:16) zoom in 1 +\i (00:00:16) setwindow pcb +\i (00:00:16) zoom in -5.2537 42.7259 +\i (00:00:16) trapsize 5515 +\i (00:00:17) zoom in 1 +\i (00:00:17) setwindow pcb +\i (00:00:17) zoom in 48.1306 62.4692 +\i (00:00:17) trapsize 2757 +\i (00:00:20) zoom in 1 +\i (00:00:20) setwindow pcb +\i (00:00:20) zoom in 64.2893 72.1203 +\i (00:00:20) trapsize 1379 \i (00:00:21) zoom out 1 \i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 11.3926 53.3761 -\i (00:00:21) trapsize 4009 +\i (00:00:21) zoom out 61.4492 70.2728 +\i (00:00:21) trapsize 2757 \i (00:00:21) zoom out 1 \i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 11.3926 53.3762 -\i (00:00:21) trapsize 8018 -\i (00:00:21) zoom out 1 -\i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 11.3925 53.3762 -\i (00:00:21) trapsize 16037 -\i (00:00:22) zoom in 1 -\i (00:00:22) setwindow pcb -\i (00:00:22) zoom in -23.2465 36.3774 -\i (00:00:22) trapsize 8018 -\i (00:00:22) zoom in 1 -\i (00:00:22) setwindow pcb -\i (00:00:22) zoom in 1.2895 29.4817 -\i (00:00:22) trapsize 4009 -\i (00:00:26) zoom out 1 -\i (00:00:26) setwindow pcb -\i (00:00:26) zoom out 34.8060 21.2229 -\i (00:00:26) trapsize 8018 -\i (00:00:27) zoom out 1 -\i (00:00:27) setwindow pcb -\i (00:00:27) zoom out 28.8724 21.5436 -\i (00:00:27) trapsize 16037 -\i (00:00:27) zoom out 1 -\i (00:00:27) setwindow pcb -\i (00:00:27) zoom out -0.5732 30.8448 -\i (00:00:27) trapsize 32073 -\i (00:00:27) zoom out 1 -\i (00:00:27) setwindow pcb -\i (00:00:27) zoom out 91.7976 36.6180 -\i (00:00:27) trapsize 64146 -\i (00:00:28) zoom in 1 -\i (00:00:28) setwindow pcb -\i (00:00:28) zoom in -3.7805 8.3937 -\i (00:00:28) trapsize 32073 -\i (00:00:28) zoom in 1 -\i (00:00:28) setwindow pcb -\i (00:00:28) zoom in -6.9878 8.3937 -\i (00:00:28) trapsize 16037 -\i (00:00:28) zoom in 1 -\i (00:00:28) setwindow pcb -\i (00:00:28) zoom in -4.1012 1.0169 -\i (00:00:28) trapsize 8018 -\i (00:00:29) zoom in 1 -\i (00:00:29) setwindow pcb -\i (00:00:29) zoom in -4.1012 1.0169 -\i (00:00:29) trapsize 4009 -\i (00:00:30) zoom in 1 -\i (00:00:30) setwindow pcb -\i (00:00:30) zoom in 32.5425 24.1097 -\i (00:00:30) trapsize 2005 -\i (00:00:30) zoom in 1 -\i (00:00:30) setwindow pcb -\i (00:00:30) zoom in 32.8232 23.3480 -\i (00:00:30) trapsize 1002 -\i (00:00:30) zoom in 1 -\i (00:00:30) setwindow pcb -\i (00:00:30) zoom in 33.2241 22.9672 -\i (00:00:30) trapsize 501 -\i (00:01:29) zoom out 1 -\i (00:01:29) setwindow pcb -\i (00:01:29) zoom out 31.5303 24.9216 -\i (00:01:29) trapsize 1002 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 30.3075 24.9016 -\i (00:01:30) trapsize 2005 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 29.9467 24.7012 -\i (00:01:30) trapsize 4009 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 29.7062 24.6211 -\i (00:01:30) trapsize 8018 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 28.4233 35.8467 -\i (00:01:30) trapsize 16037 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 28.1026 71.2708 -\i (00:01:30) trapsize 32073 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 98.2122 245.1074 -\i (00:01:30) trapsize 64146 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 296.4245 590.2147 -\i (00:01:30) trapsize 128293 -\i (00:01:31) zoom in 1 -\i (00:01:31) setwindow pcb -\i (00:01:31) zoom in -97.4341 64.2147 -\i (00:01:31) trapsize 64146 -\i (00:01:31) zoom in 1 -\i (00:01:31) setwindow pcb -\i (00:01:31) zoom in -97.4341 64.2147 -\i (00:01:31) trapsize 32073 -\i (00:01:31) zoom in 1 -\i (00:01:31) setwindow pcb -\i (00:01:31) zoom in -97.4340 64.8562 -\i (00:01:31) trapsize 16037 -\i (00:01:31) zoom in 1 -\i (00:01:31) setwindow pcb -\i (00:01:31) zoom in -78.5108 74.7989 -\i (00:01:31) trapsize 8018 -\i (00:01:32) zoom in 1 -\i (00:01:32) setwindow pcb -\i (00:01:32) zoom in 38.0752 90.8355 -\i (00:01:32) trapsize 4009 -\i (00:01:32) zoom in 1 -\i (00:01:32) setwindow pcb -\i (00:01:32) zoom in 36.0707 90.8356 -\i (00:01:32) trapsize 2005 -\i (00:01:32) zoom in 1 -\i (00:01:32) setwindow pcb -\i (00:01:32) zoom in 30.8187 90.1942 -\i (00:01:32) trapsize 1002 -\i (00:01:33) zoom in 1 -\i (00:01:33) setwindow pcb -\i (00:01:33) zoom in 21.8583 91.4170 -\i (00:01:33) trapsize 501 -\i (00:01:33) zoom out 1 -\i (00:01:33) setwindow pcb -\i (00:01:33) zoom out 21.9585 91.5072 -\i (00:01:33) trapsize 1002 -\i (00:01:34) zoom in 1 -\i (00:01:34) setwindow pcb -\i (00:01:34) zoom in 18.3102 91.2667 -\i (00:01:34) trapsize 501 -\i (00:01:35) zoom out 1 -\i (00:01:35) setwindow pcb -\i (00:01:35) zoom out 18.3403 91.3670 -\i (00:01:35) trapsize 1002 -\i (00:01:35) zoom out 1 -\i (00:01:35) setwindow pcb -\i (00:01:35) zoom out 18.3604 91.2667 -\i (00:01:35) trapsize 2005 -\i (00:01:35) zoom out 1 -\i (00:01:35) setwindow pcb -\i (00:01:35) zoom out 18.2803 90.5050 -\i (00:01:35) trapsize 4009 -\i (00:01:35) zoom out 1 -\i (00:01:35) setwindow pcb -\i (00:01:35) zoom out 18.2803 90.1842 -\i (00:01:35) trapsize 8018 -\i (00:01:36) zoom out 1 -\i (00:01:36) setwindow pcb -\i (00:01:36) zoom out 19.2424 88.9014 -\i (00:01:36) trapsize 16037 -\i (00:01:36) zoom out 1 -\i (00:01:36) setwindow pcb -\i (00:01:36) zoom out 19.2424 88.5806 -\i (00:01:36) trapsize 32073 -\i (00:01:36) zoom out 1 -\i (00:01:36) setwindow pcb -\i (00:01:36) zoom out 19.2425 60.9977 -\i (00:01:36) trapsize 64146 -\i (00:01:37) zoom out 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom out 17.9595 115.5317 -\i (00:01:37) trapsize 128293 -\i (00:01:37) zoom out 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom out 17.9595 323.3659 -\i (00:01:37) trapsize 256585 -\i (00:01:37) zoom in 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom in -79.5429 23.1610 -\i (00:01:37) trapsize 128293 -\i (00:01:37) zoom in 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom in -79.5429 23.1610 -\i (00:01:37) trapsize 64146 -\i (00:01:37) zoom in 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom in -79.5429 23.1610 -\i (00:01:37) trapsize 32073 -\i (00:01:37) zoom in 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom in -76.9770 37.2732 -\i (00:01:37) trapsize 16037 -\i (00:01:37) zoom in 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom in -75.0526 41.7635 -\i (00:01:37) trapsize 8018 -\i (00:01:38) zoom in 1 -\i (00:01:38) setwindow pcb -\i (00:01:38) zoom in -3.0483 90.8355 -\i (00:01:38) trapsize 4009 -\i (00:01:38) zoom in 1 -\i (00:01:38) setwindow pcb -\i (00:01:38) zoom in -0.7229 92.4392 -\i (00:01:38) trapsize 2005 -\i (00:01:39) zoom in 1 -\i (00:01:39) setwindow pcb -\i (00:01:39) zoom in 22.9712 93.2811 -\i (00:01:39) trapsize 1002 -\i (00:01:39) zoom in 1 -\i (00:01:39) setwindow pcb -\i (00:01:39) zoom in 22.9712 93.2811 -\i (00:01:39) trapsize 501 -\i (00:01:54) zoom out 1 -\i (00:01:54) setwindow pcb -\i (00:01:54) zoom out 19.1125 92.5294 -\i (00:01:54) trapsize 1002 -\i (00:07:02) zoom in 1 -\i (00:07:02) setwindow pcb -\i (00:07:02) zoom in 18.4710 93.8724 -\i (00:07:02) trapsize 501 -\i (00:07:04) zoom out 1 -\i (00:07:04) setwindow pcb -\i (00:07:04) zoom out 19.5334 91.9480 -\i (00:07:04) trapsize 1002 -\i (00:07:09) zoom in 1 -\i (00:07:09) setwindow pcb -\i (00:07:09) zoom in 18.4911 91.9882 -\i (00:07:09) trapsize 501 -\i (00:07:10) zoom out 1 -\i (00:07:10) setwindow pcb -\i (00:07:10) zoom out 19.2128 91.7075 -\i (00:07:10) trapsize 1002 -\i (00:07:25) zoom out 1 -\i (00:07:25) setwindow pcb -\i (00:07:25) zoom out 18.4110 90.8857 -\i (00:07:25) trapsize 2005 -\i (00:07:25) zoom in 1 -\i (00:07:25) setwindow pcb -\i (00:07:25) zoom in 19.7340 89.8032 -\i (00:07:25) trapsize 1002 -\i (00:07:25) zoom in 1 -\i (00:07:25) setwindow pcb -\i (00:07:25) zoom in 20.3755 89.3422 -\i (00:07:25) trapsize 501 -\i (00:07:29) drag_start grid 20.6361 90.3947 -\i (00:07:29) drag_stop 20.6361 90.5751 -\i (00:07:51) zoom out 1 -\i (00:07:51) setwindow pcb -\i (00:07:51) zoom out 21.4980 90.2343 -\i (00:07:51) trapsize 1002 -\i (00:07:57) zoom out 1 -\i (00:07:57) setwindow pcb -\i (00:07:57) zoom out 26.5496 91.6375 -\i (00:07:57) trapsize 2005 -\i (00:07:57) zoom out 1 -\i (00:07:57) setwindow pcb -\i (00:07:57) zoom out 26.5497 91.6375 -\i (00:07:57) trapsize 4009 -\i (00:07:57) zoom out 1 -\i (00:07:57) setwindow pcb -\i (00:07:57) zoom out 29.5966 88.4301 -\i (00:07:57) trapsize 8018 -\i (00:07:57) zoom out 1 -\i (00:07:57) setwindow pcb -\i (00:07:57) zoom out 94.8445 88.4302 -\i (00:07:57) trapsize 16037 -\i (00:07:58) zoom in 1 -\i (00:07:58) setwindow pcb -\i (00:07:58) zoom in 28.6134 86.8265 -\i (00:07:58) trapsize 8018 -\i (00:07:58) zoom in 1 -\i (00:07:58) setwindow pcb -\i (00:07:58) zoom in 39.8390 91.4771 -\i (00:07:58) trapsize 4009 -\i (00:07:58) zoom in 1 -\i (00:07:58) setwindow pcb -\i (00:07:58) zoom in 39.8391 91.3969 -\i (00:07:58) trapsize 2005 -\i (00:07:59) zoom in 1 -\i (00:07:59) setwindow pcb -\i (00:07:59) zoom in 38.3557 90.8757 -\i (00:07:59) trapsize 1002 -\i (00:07:59) zoom in 1 -\i (00:07:59) setwindow pcb -\i (00:07:59) zoom in 36.6719 90.9960 -\i (00:07:59) trapsize 501 -\i (00:08:03) zoom out 1 -\i (00:08:03) setwindow pcb -\i (00:08:03) zoom out 41.0920 90.8257 -\i (00:08:03) trapsize 1002 -\i (00:08:13) zoom out 1 -\i (00:08:13) setwindow pcb -\i (00:08:13) zoom out 47.9476 90.6251 -\i (00:08:13) trapsize 2005 -\i (00:08:14) zoom in 1 -\i (00:08:14) setwindow pcb -\i (00:08:14) zoom in 33.2742 88.2999 -\i (00:08:14) trapsize 1002 -\i (00:08:16) zoom out 1 -\i (00:08:16) setwindow pcb -\i (00:08:16) zoom out 20.1643 90.6653 -\i (00:08:16) trapsize 2005 -\i (00:08:16) zoom out 1 -\i (00:08:16) setwindow pcb -\i (00:08:16) zoom out 20.1241 90.6653 -\i (00:08:16) trapsize 4009 -\i (00:08:17) zoom in 1 -\i (00:08:17) setwindow pcb -\i (00:08:17) zoom in 15.1528 89.7031 -\i (00:08:17) trapsize 2005 -\i (00:08:17) zoom in 1 -\i (00:08:17) setwindow pcb -\i (00:08:17) zoom in 15.1529 89.7031 -\i (00:08:17) trapsize 1002 -\i (00:23:54) zoom out 1 -\i (00:23:54) setwindow pcb -\i (00:23:54) zoom out 36.2810 91.7077 -\i (00:23:54) trapsize 2005 -\i (00:23:55) zoom in 1 -\i (00:23:55) setwindow pcb -\i (00:23:55) zoom in 38.2858 92.3893 -\i (00:23:55) trapsize 1002 -\i (00:23:55) zoom in 1 -\i (00:23:55) setwindow pcb -\i (00:23:55) zoom in 38.2857 92.3893 -\i (00:23:55) trapsize 501 -\i (00:23:55) zoom out 1 -\i (00:23:55) setwindow pcb -\i (00:23:55) zoom out 38.8972 92.3492 -\i (00:23:55) trapsize 1002 -\i (00:23:55) zoom out 1 -\i (00:23:55) setwindow pcb -\i (00:23:55) zoom out 38.8971 92.3492 -\i (00:23:55) trapsize 2005 -\i (00:23:58) zoom out 1 -\i (00:23:58) setwindow pcb -\i (00:23:58) zoom out 39.6189 90.6253 -\i (00:23:58) trapsize 4009 -\i (00:23:58) zoom in 1 -\i (00:23:58) setwindow pcb -\i (00:23:58) zoom in 39.2180 90.0640 -\i (00:23:58) trapsize 2005 -\i (00:23:58) zoom in 1 -\i (00:23:58) setwindow pcb -\i (00:23:58) zoom in 39.2180 90.0641 -\i (00:23:58) trapsize 1002 -\i (00:23:59) zoom in 1 -\i (00:23:59) setwindow pcb -\i (00:23:59) zoom in 39.2180 90.0641 -\i (00:23:59) trapsize 501 -\i (00:24:00) zoom out 1 -\i (00:24:00) setwindow pcb -\i (00:24:00) zoom out 32.0116 89.7134 -\i (00:24:00) trapsize 1002 -\i (00:24:02) zoom out 1 -\i (00:24:02) setwindow pcb -\i (00:24:02) zoom out 23.3319 88.5707 -\i (00:24:02) trapsize 2005 -\i (00:24:02) zoom out 1 -\i (00:24:02) setwindow pcb -\i (00:24:02) zoom out 22.4498 88.2099 -\i (00:24:02) trapsize 4009 -\i (00:24:02) zoom out 1 -\i (00:24:02) setwindow pcb -\i (00:24:02) zoom out 22.3697 88.2100 -\i (00:24:02) trapsize 8018 -\i (00:24:02) zoom out 1 -\i (00:24:02) setwindow pcb -\i (00:24:02) zoom out 22.3697 88.2099 -\i (00:24:02) trapsize 16037 -\i (00:24:03) zoom in 1 -\i (00:24:03) setwindow pcb -\i (00:24:03) zoom in 23.0111 88.5306 -\i (00:24:03) trapsize 8018 -\i (00:24:03) zoom in 1 -\i (00:24:03) setwindow pcb -\i (00:24:03) zoom in 23.0111 88.5307 -\i (00:24:03) trapsize 4009 -\i (00:24:04) zoom out 1 -\i (00:24:04) setwindow pcb -\i (00:24:04) zoom out 20.8462 88.2902 -\i (00:24:04) trapsize 8018 -\i (00:24:04) zoom out 1 -\i (00:24:04) setwindow pcb -\i (00:24:04) zoom out 20.8462 88.2902 -\i (00:24:04) trapsize 16037 -\i (00:24:04) zoom out 1 -\i (00:24:04) setwindow pcb -\i (00:24:04) zoom out 17.9597 86.0450 -\i (00:24:04) trapsize 32073 -\i (00:24:04) zoom out 1 -\i (00:24:04) setwindow pcb -\i (00:24:04) zoom out 16.6768 83.4792 -\i (00:24:04) trapsize 64146 -\i (00:24:05) zoom in 1 -\i (00:24:05) setwindow pcb -\i (00:24:05) zoom in -2.5671 69.3464 -\i (00:24:05) trapsize 32073 -\i (00:24:05) zoom in 1 -\i (00:24:05) setwindow pcb -\i (00:24:05) zoom in -2.5671 69.3464 -\i (00:24:05) trapsize 16037 -\i (00:24:06) zoom in 1 -\i (00:24:06) setwindow pcb -\i (00:24:06) zoom in -0.0012 80.8927 -\i (00:24:06) trapsize 8018 -\i (00:24:06) zoom in 1 -\i (00:24:06) setwindow pcb -\i (00:24:06) zoom in -0.0011 80.8928 -\i (00:24:06) trapsize 4009 -\i (00:24:06) zoom in 1 -\i (00:24:06) setwindow pcb -\i (00:24:06) zoom in 8.4181 88.3498 -\i (00:24:06) trapsize 2005 -\i (00:24:06) zoom in 1 -\i (00:24:06) setwindow pcb -\i (00:24:06) zoom in 8.4181 88.3499 -\i (00:24:06) trapsize 1002 -\i (00:26:42) zoom out 1 -\i (00:26:42) setwindow pcb -\i (00:26:42) zoom out 12.4874 88.6506 -\i (00:26:42) trapsize 2005 -\i (00:26:43) zoom out 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom out 12.2870 87.2074 -\i (00:26:43) trapsize 4009 -\i (00:26:43) zoom out 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom out 12.2069 84.7216 -\i (00:26:43) trapsize 8018 -\i (00:26:43) zoom out 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom out 12.5276 82.4765 -\i (00:26:43) trapsize 16037 -\i (00:26:43) zoom in 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom in -19.5456 56.1766 -\i (00:26:43) trapsize 8018 -\i (00:26:43) zoom in 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom in -19.7060 56.1766 -\i (00:26:43) trapsize 4009 -\i (00:26:43) zoom in 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom in -19.7059 56.1767 -\i (00:26:43) trapsize 2005 -\i (00:26:44) zoom out 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom out 2.9458 64.2752 -\i (00:26:44) trapsize 4009 -\i (00:26:44) zoom in 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom in 2.7854 63.8743 -\i (00:26:44) trapsize 2005 -\i (00:26:44) zoom out 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom out 2.7854 63.8744 -\i (00:26:44) trapsize 4009 -\i (00:26:44) zoom out 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom out 2.7854 63.8743 -\i (00:26:44) trapsize 8018 -\i (00:26:44) zoom in 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom in 39.0372 93.7024 -\i (00:26:44) trapsize 4009 -\i (00:26:44) zoom in 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom in 34.3866 95.6268 -\i (00:26:44) trapsize 2005 -\i (00:26:44) zoom in 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom in 28.3328 95.3863 -\i (00:26:44) trapsize 1002 -\i (00:26:48) zoom in 1 -\i (00:26:48) setwindow pcb -\i (00:26:48) zoom in 31.0991 90.2947 -\i (00:26:48) trapsize 501 -\i (00:26:52) zoom out 1 -\i (00:26:52) setwindow pcb -\i (00:26:52) zoom out 24.5141 90.1143 -\i (00:26:52) trapsize 1002 -\i (00:26:53) zoom in 1 -\i (00:26:53) setwindow pcb -\i (00:26:53) zoom in 24.1733 91.3772 -\i (00:26:53) trapsize 501 -\i (00:26:54) zoom out 1 -\i (00:26:54) setwindow pcb -\i (00:26:54) zoom out 25.6667 91.2369 -\i (00:26:54) trapsize 1002 -\i (00:26:54) zoom out 1 -\i (00:26:54) setwindow pcb -\i (00:26:54) zoom out 25.6667 91.0967 -\i (00:26:54) trapsize 2005 -\i (00:26:55) zoom out 1 -\i (00:26:55) setwindow pcb -\i (00:26:55) zoom out 17.8489 90.8962 -\i (00:26:55) trapsize 4009 -\i (00:26:55) zoom in 1 -\i (00:26:55) setwindow pcb -\i (00:26:55) zoom in 15.8442 91.6981 -\i (00:26:55) trapsize 2005 -\i (00:26:56) zoom in 1 -\i (00:26:56) setwindow pcb -\i (00:26:56) zoom in 15.8443 91.6981 -\i (00:26:56) trapsize 1002 -\i (00:28:55) zoom out 1 -\i (00:28:55) setwindow pcb -\i (00:28:55) zoom out 24.3237 90.7159 -\i (00:28:55) trapsize 2005 -\i (00:28:55) zoom in 1 -\i (00:28:55) setwindow pcb -\i (00:28:55) zoom in 14.4612 92.3997 -\i (00:28:55) trapsize 1002 -\i (03:15:24) xrefdes K1 -\i (03:15:24) xname_flush -\i (03:15:24) trapsize 4733 -\i (03:15:26) xrefdes K3 -\i (03:15:26) xname_flush -\i (03:15:26) trapsize 4733 -\i (03:15:28) xrefdes K1 -\i (03:15:28) xname_flush -\i (03:15:28) trapsize 4733 -\i (03:15:56) xrefdes U21 -\i (03:15:56) xname_flush -\i (03:15:56) trapsize 1890 -\i (03:16:30) xNet Vbus+ -\i (03:16:30) xname_flush -\i (03:16:30) trapsize 7236 -\i (03:16:34) xNet Vbus+_Sw -\i (03:16:34) xname_flush -\i (03:16:34) trapsize 2674 -\i (03:16:38) xrefdes U5 -\i (03:16:38) xname_flush -\i (03:16:38) trapsize 2201 -\i (04:19:50) zoom out 1 -\i (04:19:50) setwindow pcb -\i (04:19:50) zoom out 28.4704 33.3770 -\i (04:19:50) trapsize 4401 -\i (04:19:50) zoom out 1 -\i (04:19:50) setwindow pcb -\i (04:19:50) zoom out 28.4704 33.3770 -\i (04:19:50) trapsize 8803 -\i (04:20:05) zoom in 1 -\i (04:20:05) setwindow pcb -\i (04:20:05) zoom in 67.9549 43.7641 -\i (04:20:05) trapsize 4401 -\i (04:20:07) zoom in 1 -\i (04:20:07) setwindow pcb -\i (04:20:07) zoom in 45.7722 39.8910 -\i (04:20:07) trapsize 2201 -\i (04:20:17) zoom out 1 -\i (04:20:17) setwindow pcb -\i (04:20:17) zoom out 51.8021 36.7661 -\i (04:20:17) trapsize 4401 -\i (04:20:18) zoom out 1 -\i (04:20:18) setwindow pcb -\i (04:20:18) zoom out 37.8939 32.3647 -\i (04:20:18) trapsize 8803 -\i (04:20:19) zoom out 1 -\i (04:20:19) setwindow pcb -\i (04:20:19) zoom out 13.0703 40.4631 -\i (04:20:19) trapsize 17605 -\i (04:20:20) zoom in 1 -\i (04:20:20) setwindow pcb -\i (04:20:20) zoom in 16.1952 5.2524 -\i (04:20:20) trapsize 8803 -\i (04:20:20) zoom in 1 -\i (04:20:20) setwindow pcb -\i (04:20:20) zoom in 15.4910 4.9004 -\i (04:20:20) trapsize 4401 -\i (04:20:22) zoom in 1 -\i (04:20:22) setwindow pcb -\i (04:20:22) zoom in 33.5365 21.7135 -\i (04:20:22) trapsize 2201 -\i (04:20:22) zoom in 1 -\i (04:20:22) setwindow pcb -\i (04:20:22) zoom in 34.5488 22.3737 -\i (04:20:22) trapsize 1100 -\i (04:20:22) zoom in 1 -\i (04:20:22) setwindow pcb -\i (04:20:22) zoom in 34.5488 22.3737 -\i (04:20:22) trapsize 550 -\i (04:20:23) zoom in 1 -\i (04:20:23) setwindow pcb -\i (04:20:23) zoom in 33.8446 23.6061 -\i (04:20:23) trapsize 275 -\i (04:20:23) zoom in 1 -\i (04:20:23) setwindow pcb -\i (04:20:23) zoom in 33.1183 23.8152 -\i (04:20:23) trapsize 138 -\i (04:20:23) zoom out 1 -\i (04:20:23) setwindow pcb -\i (04:20:23) zoom out 33.3383 23.8345 -\i (04:20:23) trapsize 275 -\i (04:20:23) zoom out 1 -\i (04:20:23) setwindow pcb -\i (04:20:23) zoom out 33.3438 23.7850 -\i (04:20:23) trapsize 550 -\i (04:20:33) zoom out 1 -\i (04:20:33) setwindow pcb -\i (04:20:33) zoom out 34.9944 23.6969 -\i (04:20:33) trapsize 1100 -\i (04:20:33) zoom out 1 -\i (04:20:33) setwindow pcb -\i (04:20:33) zoom out 35.2585 23.6970 -\i (04:20:33) trapsize 2201 -\i (04:20:34) zoom out 1 -\i (04:20:34) setwindow pcb -\i (04:20:34) zoom out 35.0825 22.9047 -\i (04:20:34) trapsize 4402 -\i (04:20:34) zoom out 1 -\i (04:20:34) setwindow pcb -\i (04:20:34) zoom out 35.0824 22.9047 -\i (04:20:34) trapsize 8803 -\i (04:20:35) zoom in 1 -\i (04:20:35) setwindow pcb -\i (04:20:35) zoom in 33.6739 48.2577 -\i (04:20:35) trapsize 4402 -\i (04:20:35) zoom in 1 -\i (04:20:35) setwindow pcb -\i (04:20:35) zoom in 36.9311 22.7287 -\i (04:20:35) trapsize 2201 -\i (04:20:35) zoom in 1 -\i (04:20:35) setwindow pcb -\i (04:20:35) zoom in 36.1389 22.1125 -\i (04:20:35) trapsize 1100 -\i (04:20:36) zoom in 1 -\i (04:20:36) setwindow pcb -\i (04:20:36) zoom in 31.9134 24.1592 -\i (04:20:36) trapsize 550 -\i (04:20:36) zoom in 1 -\i (04:20:36) setwindow pcb -\i (04:20:36) zoom in 31.9134 24.1592 -\i (04:20:36) trapsize 275 -\i (04:20:37) zoom out 1 -\i (04:20:37) setwindow pcb -\i (04:20:37) zoom out 34.8459 23.5815 -\i (04:20:37) trapsize 550 -\i (04:20:38) zoom in 1 -\i (04:20:38) setwindow pcb -\i (04:20:38) zoom in 36.3204 23.2514 -\i (04:20:38) trapsize 275 -\i (04:20:40) zoom out 1 -\i (04:20:40) setwindow pcb -\i (04:20:40) zoom out 35.9188 23.9722 -\i (04:20:40) trapsize 550 -\i (04:20:41) zoom out 1 -\i (04:20:41) setwindow pcb -\i (04:20:41) zoom out 37.6905 23.9502 -\i (04:20:41) trapsize 1100 -\i (04:20:41) zoom in 1 -\i (04:20:41) setwindow pcb -\i (04:20:41) zoom in 39.2309 23.4440 -\i (04:20:41) trapsize 550 -\i (04:20:42) zoom in 1 -\i (04:20:42) setwindow pcb -\i (04:20:42) zoom in 38.5377 23.6861 -\i (04:20:42) trapsize 275 -\i (04:20:42) zoom in 1 -\i (04:20:42) setwindow pcb -\i (04:20:42) zoom in 38.5377 23.6861 -\i (04:20:42) trapsize 138 -\i (04:20:43) zoom out 1 -\i (04:20:43) setwindow pcb -\i (04:20:43) zoom out 38.2736 23.7027 -\i (04:20:43) trapsize 275 -\i (04:20:45) zoom out 1 -\i (04:20:45) setwindow pcb -\i (04:20:45) zoom out 35.2366 23.8787 -\i (04:20:45) trapsize 550 -\i (04:20:46) zoom out 1 -\i (04:20:46) setwindow pcb -\i (04:20:46) zoom out 36.1169 24.6599 -\i (04:20:46) trapsize 1100 -\i (04:20:46) zoom out 1 -\i (04:20:46) setwindow pcb -\i (04:20:46) zoom out 36.1169 24.5499 -\i (04:20:46) trapsize 2201 -\i (04:20:46) zoom out 1 -\i (04:20:46) setwindow pcb -\i (04:20:46) zoom out 36.6011 24.6819 -\i (04:20:46) trapsize 4402 -\i (04:20:47) zoom out 1 -\i (04:20:47) setwindow pcb -\i (04:20:47) zoom out 35.1925 31.9005 -\i (04:20:47) trapsize 8803 -\i (04:20:47) zoom in 1 -\i (04:20:47) setwindow pcb -\i (04:20:47) zoom in 32.9036 29.6117 -\i (04:20:47) trapsize 4402 -\i (04:20:47) zoom out 1 -\i (04:20:47) setwindow pcb -\i (04:20:47) zoom out 32.7276 30.4920 -\i (04:20:47) trapsize 8803 -\i (04:20:47) zoom out 1 -\i (04:20:47) setwindow pcb -\i (04:20:47) zoom out 32.5515 30.4920 -\i (04:20:47) trapsize 17606 -\i (04:20:48) zoom in 1 -\i (04:20:48) setwindow pcb -\i (04:20:48) zoom in 18.3135 52.8216 -\i (04:20:48) trapsize 8803 -\i (04:20:48) zoom in 1 -\i (04:20:48) setwindow pcb -\i (04:20:48) zoom in 18.3135 52.8216 -\i (04:20:48) trapsize 4402 -\i (04:20:49) zoom in 1 -\i (04:20:49) setwindow pcb -\i (04:20:49) zoom in 34.3352 20.6903 -\i (04:20:49) trapsize 2201 -\i (04:20:50) zoom in 1 -\i (04:20:50) setwindow pcb -\i (04:20:50) zoom in 32.7506 19.7220 -\i (04:20:50) trapsize 1100 -\i (04:20:50) zoom in 1 -\i (04:20:50) setwindow pcb -\i (04:20:50) zoom in 33.0587 21.2626 -\i (04:20:50) trapsize 550 -\i (04:20:50) zoom in 1 -\i (04:20:50) setwindow pcb -\i (04:20:50) zoom in 33.0587 21.2626 -\i (04:20:50) trapsize 275 -\i (04:20:51) zoom out 1 -\i (04:20:51) setwindow pcb -\i (04:20:51) zoom out 33.0587 23.3203 -\i (04:20:51) trapsize 550 -\i (04:20:55) zoom in 1 -\i (04:20:55) setwindow pcb -\i (04:20:55) zoom in 34.3352 23.7385 -\i (04:20:55) trapsize 275 -\i (04:20:56) drag_start grid 34.3023 23.7275 -\i (04:20:56) zoom in 1 -\i (04:20:56) setwindow pcb -\i (04:20:56) zoom in 34.3408 23.0673 -\i (04:20:56) trapsize 138 -\i (04:20:56) drag_stop 34.3573 22.9353 -\i (04:20:57) zoom out 1 -\i (04:20:57) setwindow pcb -\i (04:20:57) zoom out 34.3436 22.9793 -\i (04:20:57) trapsize 275 -\i (04:20:57) zoom out 1 -\i (04:20:57) setwindow pcb -\i (04:20:57) zoom out 34.3436 22.9793 -\i (04:20:57) trapsize 550 -\i (04:20:57) zoom out 1 -\i (04:20:57) setwindow pcb -\i (04:20:57) zoom out 34.3545 22.9353 -\i (04:20:57) trapsize 1100 -\i (04:20:57) zoom in 1 -\i (04:20:57) setwindow pcb -\i (04:20:57) zoom in 33.4742 26.5226 -\i (04:20:57) trapsize 550 -\i (04:20:58) zoom in 1 -\i (04:20:58) setwindow pcb -\i (04:20:58) zoom in 34.8717 23.7717 -\i (04:20:58) trapsize 275 -\i (04:21:36) help -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 36.1042 24.5970 -\i (04:22:22) trapsize 550 -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 36.1041 24.5090 -\i (04:22:22) trapsize 1100 -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 36.1701 24.3990 -\i (04:22:22) trapsize 2201 -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 37.1825 23.6948 -\i (04:22:22) trapsize 4402 -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 46.2497 31.2655 -\i (04:22:22) trapsize 8803 -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 85.7451 31.2656 -\i (04:22:22) trapsize 17606 -\i (04:22:23) zoom in 1 -\i (04:22:23) setwindow pcb -\i (04:22:23) zoom in 13.7359 82.0478 -\i (04:22:23) trapsize 8803 -\i (04:22:26) zoom in 1 -\i (04:22:26) setwindow pcb -\i (04:22:26) zoom in 33.2788 57.5752 -\i (04:22:26) trapsize 4402 -\i (04:22:26) zoom in 1 -\i (04:22:26) setwindow pcb -\i (04:22:26) zoom in 33.2788 57.5753 -\i (04:22:26) trapsize 2201 -\i (04:22:27) zoom out 1 -\i (04:22:27) setwindow pcb -\i (04:22:27) zoom out 36.7560 59.1599 -\i (04:22:27) trapsize 4402 -\i (04:22:27) zoom out 1 -\i (04:22:27) setwindow pcb -\i (04:22:27) zoom out 36.7559 59.1599 -\i (04:22:27) trapsize 8803 -\i (04:22:27) zoom in 1 -\i (04:22:27) setwindow pcb -\i (04:22:27) zoom in 2.7760 75.0054 -\i (04:22:27) trapsize 4402 -\i (04:22:32) zoom out 1 -\i (04:22:32) setwindow pcb -\i (04:22:32) zoom out 69.6795 77.9985 -\i (04:22:32) trapsize 8803 -\i (04:22:34) zoom in 1 -\i (04:22:34) setwindow pcb -\i (04:22:34) zoom in 73.5968 80.6394 -\i (04:22:34) trapsize 4402 -\i (04:22:34) zoom in 1 -\i (04:22:34) setwindow pcb -\i (04:22:34) zoom in 73.5968 80.6395 -\i (04:22:34) trapsize 2201 -\i (04:22:34) zoom in 1 -\i (04:22:34) setwindow pcb -\i (04:22:34) zoom in 71.6601 81.1677 -\i (04:22:34) trapsize 1100 -\i (04:22:35) zoom in 1 -\i (04:22:35) setwindow pcb -\i (04:22:35) zoom in 72.6285 80.9257 -\i (04:22:35) trapsize 550 -\i (04:22:35) zoom in 1 -\i (04:22:35) setwindow pcb -\i (04:22:35) zoom in 72.6285 80.9257 -\i (04:22:35) trapsize 275 -\i (04:23:52) zoom out 1 -\i (04:23:52) setwindow pcb -\i (04:23:52) zoom out 70.3892 79.9464 -\i (04:23:52) trapsize 550 -\i (04:23:55) zoom in 1 -\i (04:23:55) setwindow pcb -\i (04:23:55) zoom in 66.5489 80.1885 -\i (04:23:55) trapsize 275 -\i (04:23:55) zoom in 1 -\i (04:23:55) setwindow pcb -\i (04:23:55) zoom in 66.0538 80.2106 -\i (04:23:55) trapsize 138 -\i (04:23:55) zoom in 1 -\i (04:23:55) setwindow pcb -\i (04:23:55) zoom in 66.0538 80.2106 -\i (04:23:55) trapsize 69 -\i (04:23:55) zoom out 1 -\i (04:23:55) setwindow pcb -\i (04:23:55) zoom out 66.1597 80.2492 -\i (04:23:55) trapsize 138 -\i (04:23:55) zoom out 1 -\i (04:23:55) setwindow pcb -\i (04:23:55) zoom out 66.1597 80.2492 -\i (04:23:55) trapsize 275 -\i (04:23:56) zoom out 1 -\i (04:23:56) setwindow pcb -\i (04:23:56) zoom out 66.5283 80.3812 -\i (04:23:56) trapsize 550 -\i (04:23:58) zoom in 1 -\i (04:23:58) setwindow pcb -\i (04:23:58) zoom in 71.8655 80.6564 -\i (04:23:58) trapsize 275 -\i (04:23:59) zoom out 1 -\i (04:23:59) setwindow pcb -\i (04:23:59) zoom out 71.7500 80.5023 -\i (04:23:59) trapsize 550 -\i (04:28:30) zoom out 1 -\i (04:28:30) setwindow pcb -\i (04:28:30) zoom out 73.0154 79.4459 -\i (04:28:30) trapsize 1100 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 72.3551 79.1158 -\i (04:28:31) trapsize 2201 -\i (04:28:31) zoom in 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom in 70.6824 76.9588 -\i (04:28:31) trapsize 1100 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 70.0882 77.3990 -\i (04:28:31) trapsize 2201 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 69.7801 77.3990 -\i (04:28:31) trapsize 4402 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 55.2541 77.8392 -\i (04:28:31) trapsize 8804 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 54.1977 69.5637 -\i (04:28:31) trapsize 17607 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 108.1170 57.9431 -\i (04:28:31) trapsize 35214 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 319.7555 52.1262 -\i (04:28:31) trapsize 70429 -\i (04:28:46) xdehilite -\i (04:28:46) xrefdes U5 -\i (04:28:46) xname_flush -\i (04:28:46) done -\i (04:28:46) generaledit -\i (04:29:34) xNet Pb10_Usart3_Tx -\i (04:29:34) xname_flush -\i (04:29:34) trapsize 710 -\i (04:39:25) xNet Pb9 -\i (04:39:25) xname_flush -\i (04:39:25) trapsize 580 -\i (04:42:22) xNet Pb10_Usart3_Tx -\i (04:42:22) xname_flush -\i (04:42:22) trapsize 710 -\i (04:42:36) xNet N3579505 -\i (04:42:36) xname_flush -\i (04:42:36) trapsize 137 -\i (04:43:09) xNet N3579545 -\i (04:43:09) xname_flush -\i (04:43:09) trapsize 290 -\i (04:43:17) xNet N3579545 -\i (04:43:17) xname_flush -\i (04:43:17) trapsize 290 -\i (04:43:23) xNet Pa9_Usart1_Tx -\i (04:43:23) xname_flush -\i (04:43:23) trapsize 2757 -\i (06:32:33) exit -\e (06:32:33) Do you want to save the changes you made to HC_DFCD_Protocol_V3_0.brd? -\i (06:32:34) fillin yes -\t (06:32:34) Journal end - Wed Aug 26 17:53:03 2026 +\i (00:00:21) zoom out 58.1402 66.3021 +\i (00:00:21) trapsize 5515 +\i (00:10:52) exit +\t (00:10:53) Journal end - Fri Sep 11 15:47:54 2026