From c55f05e838a0b18defe7b08653ff0db928bf701c Mon Sep 17 00:00:00 2001 From: wrh Date: Wed, 16 Sep 2026 10:51:11 +0800 Subject: [PATCH] =?UTF-8?q?chore:=20=E6=9B=B4=E6=96=B0=E5=8D=8F=E8=AE=AE?= =?UTF-8?q?=E6=9D=BF=E7=89=88=E6=9C=AC=E3=80=81=E9=80=9A=E4=BF=A1=E9=87=8D?= =?UTF-8?q?=E8=AF=95=E6=AC=A1=E6=95=B0=E5=8F=8A=E5=AE=8F=E5=AE=9A=E4=B9=89?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1. 修改apps/chrg/applications/thread/chrg_roll_sou.c：将通信最大尝试次数从3改为10 2. 修改apps/chrg/applications/thread/chrg_comm.c：更新协议板固件版本为0x0129(V1.1.25) 3. 修改apps/chrg/applications/utils/chrg_sink.c：替换初始化命令相关的硬编码宏为更语义化的常量 4. 更新docs/Allegro.jrl：更新Cadence Allegro操作日志记录 --- apps/chrg/applications/thread/chrg_roll_sou.c | 2 +- apps/chrg/applications/utils/chrg_sink.c | 4 +- docs/Allegro.jrl | 38 +++++++++++-------- 3 files changed, 25 insertions(+), 19 deletions(-) diff --git a/apps/chrg/applications/thread/chrg_roll_sou.c b/apps/chrg/applications/thread/chrg_roll_sou.c index 81664cb..d89f132 100644 --- a/apps/chrg/applications/thread/chrg_roll_sou.c +++ b/apps/chrg/applications/thread/chrg_roll_sou.c @@ -25,7 +25,7 @@ #define SOU_MUTEX_TIMEOUT_MS 100 #define SOU_RESPONSE_TIMEOUT_MS 20 -#define SOU_COM_MAX_ATTEMPTS 3 +#define SOU_COM_MAX_ATTEMPTS 10 #define SOU_COM_RETRY_YIELD_MS 1U #define SOU_REL_SWITCH_DELAY_MS 100U #define SOU_CHANNEL_BIT(ch) ((rt_uint8_t)(1U << (ch))) diff --git a/apps/chrg/applications/utils/chrg_sink.c b/apps/chrg/applications/utils/chrg_sink.c index 0912cc0..cd7dfae 100644 --- a/apps/chrg/applications/utils/chrg_sink.c +++ b/apps/chrg/applications/utils/chrg_sink.c @@ -260,8 +260,8 @@ static rt_uint8_t chrg_sink_init_build_commands(struct chrg_switch_t *pSW, { rt_uint8_t count; - regs[0] = ModbusRTU_ShortTest_CMD_MODE_FLAG; - vals[0] = ModbusRTU_DYNA_CMD_MODE_STOP; + regs[0] = REG_WORK; + vals[0] = WORK_STOP; if (pSW->sink.test.test_mode_old == SINK_TEST_SHORT) { regs[1] = REG_REL_ON; vals[1] = ALL_REL_OFF; regs[2] = REG_REL_ON; vals[2] = FU_REL_ON; diff --git a/docs/Allegro.jrl b/docs/Allegro.jrl index 6496f36..18239d2 100644 --- a/docs/Allegro.jrl +++ b/docs/Allegro.jrl @@ -1,19 +1,25 @@ -\t (00:00:01) allegro 17.2 S079 Windows SPB 64-bit Edition -\t (00:00:01) Journal start - Tue Sep 15 20:16:48 2026 -\t (00:00:01) Host=DESKTOP-5RA9F3K User=Adminuser Pid=20076 CPUs=20 -\t (00:00:01) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe -\t (00:00:01) - (00:00:01) Loading axlcore.cxt -\t (00:00:02) Starting new design... -\i (00:00:04) trapsize 29310 -\i (00:00:05) generaledit -\i (00:00:12) open -\i (00:00:13) fillin "HC_DFCD_Protocol_V3_0.brd" -\i (00:00:13) trapsize 1230 -\i (00:00:13) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed -\t (00:00:13) Opening existing design... -\i (00:00:13) trapsize 2757 -\d (00:00:13) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd +\t (00:00:06) allegro 17.2 S079 Windows SPB 64-bit Edition +\t (00:00:06) Journal start - Tue Sep 15 20:16:48 2026 +\t (00:00:06) Host=DESKTOP-5RA9F3K User=Adminuser Pid=8232 CPUs=20 +\t (00:00:06) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe +\t (00:00:06) + (00:00:06) Loading axlcore.cxt +\t (00:00:07) Starting new design... +\i (00:00:09) trapsize 29310 +\i (00:00:10) generaledit +\i (00:00:18) xhilite +\i (00:00:18) xname_flush +\i (00:00:18) done +\i (00:00:19) generaledit +\i (00:00:33) xhilite +\i (00:00:34) xname_flush +\i (00:00:34) done +\i (00:00:34) generaledit +\i (00:20:00) exit +\e (00:20:00) Do you want to save the changes you made to unnamed.brd? +\i (12:51:55) fillin no +\t (12:51:56) Journal end - Wed Sep 16 09:08:37 2026 + \i (00:00:13) generaledit \i (00:00:14) zoom out 1 \i (00:00:14) setwindow pcb