From 9a7950d1225ec95070a4431228d80b6638223ce1 Mon Sep 17 00:00:00 2001 From: wrh Date: Wed, 9 Sep 2026 20:37:09 +0800 Subject: [PATCH 1/4] =?UTF-8?q?=E4=BF=AE=E5=A4=8D=E4=BA=86=E7=9F=AD?= =?UTF-8?q?=E8=B7=AF=E6=B5=8B=E8=AF=95=E4=B8=8B=E7=94=B1=E4=BA=8E=E5=8F=91?= =?UTF-8?q?=E9=80=81=E8=BF=90=E8=A1=8C=E6=97=B6=E9=97=B4=E5=A4=AA=E7=9F=AD?= =?UTF-8?q?=E5=AF=BC=E8=87=B41~2=E6=8C=81=E7=BB=AD=E6=8A=A2=E5=8D=A0?= =?UTF-8?q?=E5=8D=97=E5=90=91=E5=8F=91=E9=80=81=20=E4=BF=AE=E5=A4=8D?= =?UTF-8?q?=E4=BA=86V=5FON=E5=9C=A8=E8=BF=90=E8=A1=8C=E7=8A=B6=E6=80=81?= =?UTF-8?q?=E4=B8=8B=E4=B8=8D=E8=83=BD=E5=8F=91=E9=80=81=E6=96=B0=E7=9A=84?= =?UTF-8?q?=E8=AE=BE=E7=BD=AE=E5=80=BC=E7=9A=84=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit chore: 更新版本号并新增运行中修改V_On功能 1. 更新多个文件的版本号至V1.1.14~V1.1.15 2. 新增Sink通道运行中修改V_On时下发Eload_Start_V_ON逻辑 3. 新增Sink电压判定可选来源配置，支持协议板或功率板电压 4. 优化chrg_sink_parse函数，新增实际电压读取和序号更新 5. 调整短路测试补发周期至50ms，移除冗余宏定义 6. 更新修改日志文档，新增V1.1.15版本变更记录 7. 新增协议板YMODEM升级文档 --- apps/chrg/applications/thread/chrg_comm.c | 18 +- apps/chrg/applications/thread/chrg_comm.h | 2 +- apps/chrg/applications/thread/chrg_north.c | 13 +- apps/chrg/applications/thread/chrg_north.h | 24 +- apps/chrg/applications/thread/chrg_roll_nor.c | 4 +- apps/chrg/applications/thread/chrg_roll_nor.h | 2 +- apps/chrg/applications/thread/chrg_roll_sou.c | 3 +- apps/chrg/applications/utils/chrg_sink.c | 45 +++- apps/chrg/applications/utils/chrg_sink.h | 4 +- apps/chrg/applications/utils/chrg_source.c | 2 +- apps/chrg/applications/utils/chrg_source.h | 2 +- apps/chrg/codex_von_verify.log | 9 + docs/修改日志.md | 12 + docs/协议板Boot_YMODEM上位机实现规则.md | 208 ++++++++++++++++++ 14 files changed, 319 insertions(+), 29 deletions(-) create mode 100644 apps/chrg/codex_von_verify.log create mode 100644 docs/协议板Boot_YMODEM上位机实现规则.md diff --git a/apps/chrg/applications/thread/chrg_comm.c b/apps/chrg/applications/thread/chrg_comm.c index 9d08969..4796e4f 100644 --- a/apps/chrg/applications/thread/chrg_comm.c +++ b/apps/chrg/applications/thread/chrg_comm.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_comm.c 完成日期 : -当前版本号 : V1.1.10 +当前版本号 : V1.1.15 主要功能 : 实现对外通讯协议 MODBUS 服务端，以独立线程等待处理响应请求数据。 版本历史 : 创建原始版本 说明 : @@ -27,7 +27,7 @@ #include "stm32f4xx_hal.h" #define HOLD_REG_FIRMWARE_VERSION 0x0300U /* 协议板固件版本，只读 */ -#define CHRG_FIRMWARE_VERSION 0x011AU /* 当前协议板版本：V1.1.10 */ +#define CHRG_FIRMWARE_VERSION 0x011FU /* 当前协议板版本：V1.1.15 */ rt_uint8_t ucDiscInBuf[(TOTAL_DISC_REGS+BITS_UCHAR-1)/BITS_UCHAR]; rt_uint8_t ucCoilBuf[(TOTAL_COIL_REGS+BITS_UCHAR-1)/BITS_UCHAR]; @@ -618,7 +618,7 @@ eMBException funcReadHoldingRegister (rt_uint8_t *reqFrame, rt_uint16_t reqLen, /* * 协议板版本号使用独立的只读地址0x0300，不占用现有通道保持寄存器空间。 - * 当前版本V1.1.10编码为0x011A，Modbus响应按高字节在前返回01 1A。 + * 当前版本V1.1.15编码为0x011F，Modbus响应按高字节在前返回01 1F。 * 该特殊地址只支持一次读取一个寄存器，避免与普通连续寄存器混用。 */ if (regAddress == HOLD_REG_FIRMWARE_VERSION) { @@ -2563,6 +2563,7 @@ static eMBException chrg_comm_apply_sink_effect(rt_uint8_t ch, rt_bool_t protocol_voltage_only; rt_bool_t protocol_current_change; rt_bool_t protocol_data_changed; + rt_bool_t von_changed; rt_uint8_t curr_test; rt_uint8_t curr_test_old; rt_uint8_t old_cv_mode = pReal->CV_mode; @@ -2587,6 +2588,17 @@ static eMBException chrg_comm_apply_sink_effect(rt_uint8_t ch, !full_handshake_change; protocol_voltage_only = diff_info.pro_voltage_changed && !full_handshake_change && !protocol_current_change; + von_changed = (pReal->sink.volt_on != pShadow->sink.volt_on); + if ((sink_work == 0x01) && (old_on_work == 1U) && von_changed) { + rt_uint16_t reg = Eload_Start_V_ON; + rt_uint16_t val = (pShadow->sink.volt_on <= 500U) ? + 500U : pShadow->sink.volt_on; + + if (chrg_sou_com_batch_submit((eIDX_SOU_CH)ch, ®, + &val, 1U) != 0) { + return MB_EX_SLAVE_BUSY; + } + } rt_memcpy(pReal, pShadow, sizeof(struct chrg_switch_t)); if (sink_work == 0x01) { diff --git a/apps/chrg/applications/thread/chrg_comm.h b/apps/chrg/applications/thread/chrg_comm.h index 1f3687d..76e30ec 100644 --- a/apps/chrg/applications/thread/chrg_comm.h +++ b/apps/chrg/applications/thread/chrg_comm.h @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_comm.h 完成日期 : -当前版本号 : V1.1.10 +当前版本号 : V1.1.15 主要功能 : 实现对外通讯协议 MODBUS 服务端，以独立线程等待处理响应请求数据。 版本历史 : 创建原始版本 说明 : diff --git a/apps/chrg/applications/thread/chrg_north.c b/apps/chrg/applications/thread/chrg_north.c index 16108f8..8fe2401 100644 --- a/apps/chrg/applications/thread/chrg_north.c +++ b/apps/chrg/applications/thread/chrg_north.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_north.c 完成日期 : -当前版本号 : V1.1.10 +当前版本号 : V1.1.14 主要功能 : 实现北向通信交互，包括接收命令解析，发送请求命令，切换通路。以独立线程处理。 版本历史 : 创建原始版本 说明 : @@ -212,13 +212,13 @@ void chrg_source_setting(rt_uint8_t *frame_data, eIDX_SOU_CH idx, /***************************************************************** 函数名称： chrg_sink_parse -函数描述： 解析北向负载板0x20回码，提取D+/D-电压到VZ/VF +函数描述： 解析北向负载板0x20回码，提取实际电压和D+/D-电压 输入参数： frame_data:完整北向回码 idx:当前通道 pSW:通道控制结构体 pNOR:北向总控结构体 -输出参数： 更新pSW->VZ(D+)、pSW->VF(D-) +输出参数： 更新pSW->Sink_voltage、VZ(D+)、VF(D-) 返回说明： - -其它说明： Sink电压状态机判定已迁移至chrg_sink_volt_judge， - 由北向轮询线程基于eload.c更新的Now_voltage驱动 +其它说明： Sink电压状态机可通过SINK_VON_VOLTAGE_SOURCE选择使用本回码 + 实际电压或功率板实际电压 *****************************************************************/ void chrg_sink_parse(rt_uint8_t *frame_data, eIDX_SOU_CH idx, struct chrg_switch_t *pSW, struct chrg_north_t *pNOR) @@ -227,6 +227,9 @@ void chrg_sink_parse(rt_uint8_t *frame_data, eIDX_SOU_CH idx, return; } + pSW->Sink_voltage = (rt_uint16_t)(((frame_data[4] << 8) | + frame_data[5]) * 10U); + pSW->Sink_voltage_seq++; pSW->VZ = ((frame_data[14] << 8) | frame_data[15]); pSW->VF = ((frame_data[16] << 8) | frame_data[17]); diff --git a/apps/chrg/applications/thread/chrg_north.h b/apps/chrg/applications/thread/chrg_north.h index 24d3c99..a67152e 100644 --- a/apps/chrg/applications/thread/chrg_north.h +++ b/apps/chrg/applications/thread/chrg_north.h @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_north.h 完成日期 : -当前版本号 : V1.0 +当前版本号 : V1.1.14 主要功能 : 实现北向通信交互，包括接收命令解析，发送请求命令，切换通路。以独立线程处理。 版本历史 : 创建原始版本 说明 : @@ -16,6 +16,20 @@ #include "chrg_sink.h" #include "chrg_def.h" +/* V_On启停判定电压源：切换后需重新编译固件。 */ +#define SINK_VON_VOLTAGE_FROM_PROTOCOL 1U +#define SINK_VON_VOLTAGE_FROM_POWER 2U +#ifndef SINK_VON_VOLTAGE_SOURCE +#define SINK_VON_VOLTAGE_SOURCE SINK_VON_VOLTAGE_FROM_POWER +#endif +#if (SINK_VON_VOLTAGE_SOURCE != SINK_VON_VOLTAGE_FROM_PROTOCOL) && \ + (SINK_VON_VOLTAGE_SOURCE != SINK_VON_VOLTAGE_FROM_POWER) +#error "Invalid SINK_VON_VOLTAGE_SOURCE" +#endif + +/* 南向COM批次中单通道连续收到有效回码后的最大发送条数。 */ +#define SOU_COM_BURST_MAX 10U + #define THR_NAME_NORTH "thr.nor" #define DEV_NAME_NORTH "uart3" @@ -23,10 +37,10 @@ #define MIN_FRAME_LENGTH (5) // 帧最短5字节 #define WORK_MIN_VOLT 500 // 工作电压下限，单位mV #define NORTH_FRAME_DEBUG 0x00 // 北向UART原始收发帧 -#define NORTH_SOURCE_DEBUG 0x01 // Source协议解析及组帧 -#define NORTH_SINK_DEBUG 0x01 // Sink协议解析及组帧 +#define NORTH_SOURCE_DEBUG 0x00 // Source协议解析及组帧 +#define NORTH_SINK_DEBUG 0x00 // Sink协议解析及组帧 #define SOUTH_FRAME_DEBUG 0x00 // 南向UART原始收发帧 -#define SOUTH_COMMAND_DEBUG 0x00 // 南向寄存器写命令 +#define SOUTH_COMMAND_DEBUG 0x01 // 南向寄存器写命令 #define COMM_FRAME_DEBUG 0x00 // COM UART原始收发帧 #define COMM_DEBUG 0x00 // COM寄存器读写过程 #define COMM_TRIM_DEBUG 0x00 // COM校准参数解析 @@ -56,6 +70,8 @@ struct chrg_switch_t { rt_uint8_t change_flag; //正在调整功率标志位 rt_uint16_t Now_voltage; // 当前电压 mV rt_uint16_t Now_current; // 当前电流 mA + rt_uint16_t Sink_voltage; // 协议板0x20回码的实际电压 mV + rt_uint32_t Sink_voltage_seq; // 协议板实际电压有效回码序号 rt_uint16_t VZ; rt_uint16_t VF; }; diff --git a/apps/chrg/applications/thread/chrg_roll_nor.c b/apps/chrg/applications/thread/chrg_roll_nor.c index 7b8a87a..4f60929 100644 --- a/apps/chrg/applications/thread/chrg_roll_nor.c +++ b/apps/chrg/applications/thread/chrg_roll_nor.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_roll_nor.c 完成日期 : -当前版本号 : V1.1.10 +当前版本号 : V1.1.14 主要功能 : 实现北向通信轮巡请求命令。以独立线程处理。 版本历史 : 创建原始版本 说明 : @@ -1033,7 +1033,7 @@ void chrg_roll_nor_thread_entry (void *data) source_waiting = chrg_roll_nor_source_wait_process(idx, pSW); sink_waiting = chrg_roll_nor_sink_wait_process(idx, pSW); - /* 全通道Sink电压判定：使用eload实际电压Now_voltage与V_On比较， + /* 全通道Sink电压判定：使用配置的V_On电压源与V_On比较， * 判定后统一由chrg_sink_work执行；短路测试由该入口负责WORK_START保活。 */ for (i = 0; i < TOTAL_NOR_CHS; i++) { struct chrg_switch_t *psw = &pNOR->sw[i]; diff --git a/apps/chrg/applications/thread/chrg_roll_nor.h b/apps/chrg/applications/thread/chrg_roll_nor.h index 74d3a7f..5bdffaa 100644 --- a/apps/chrg/applications/thread/chrg_roll_nor.h +++ b/apps/chrg/applications/thread/chrg_roll_nor.h @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_roll_nor.h 完成日期 : -当前版本号 : V1.1.10 +当前版本号 : V1.1.14 主要功能 : 实现北向通信轮巡请求命令。以独立线程处理。 版本历史 : 创建原始版本 说明 : diff --git a/apps/chrg/applications/thread/chrg_roll_sou.c b/apps/chrg/applications/thread/chrg_roll_sou.c index cc0a46d..65d6c89 100644 --- a/apps/chrg/applications/thread/chrg_roll_sou.c +++ b/apps/chrg/applications/thread/chrg_roll_sou.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_roll_sou.c 完成日期 : -当前版本号 : V1.0 +当前版本号 : V1.1.14 主要功能 : 实现南向通信轮巡请求命令。以独立线程处理。 版本历史 : 创建原始版本 说明 : @@ -26,7 +26,6 @@ #define SOU_MUTEX_TIMEOUT_MS 100 #define SOU_RESPONSE_TIMEOUT_MS 20 #define SOU_COM_MAX_ATTEMPTS 3 -#define SOU_COM_BURST_MAX 10U #define SOU_COM_RETRY_YIELD_MS 1U #define SOU_REL_SWITCH_DELAY_MS 100U #define SOU_CHANNEL_BIT(ch) ((rt_uint8_t)(1U << (ch))) diff --git a/apps/chrg/applications/utils/chrg_sink.c b/apps/chrg/applications/utils/chrg_sink.c index 9ee9355..fb28740 100644 --- a/apps/chrg/applications/utils/chrg_sink.c +++ b/apps/chrg/applications/utils/chrg_sink.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_sink.c 完成日期 : -当前版本号 : V1.0 +当前版本号 : V1.1.14 主要功能 : 北向数据sink请求数据填充及发送。 版本历史 : 创建原始版本 说明 : @@ -41,6 +41,10 @@ static rt_tick_t g_sink_unload_query_tick[TOTAL_SOU_CHS] = {0}; static rt_uint8_t g_sink_unload_confirm_count[TOTAL_SOU_CHS] = {0}; /* 记录各通道短路测试最近一次WORK_START的发送时间。 */ static rt_tick_t g_sink_short_start_tick[TOTAL_SOU_CHS] = {0}; +#if SINK_VON_VOLTAGE_SOURCE == SINK_VON_VOLTAGE_FROM_PROTOCOL +/* 只消费新的协议板0x20电压回码，避免同一帧重复计入稳定次数。 */ +static rt_uint32_t g_sink_von_voltage_seq[TOTAL_SOU_CHS] = {0}; +#endif enum { SINK_UNLOAD_NEXT_RUNNING = 0, @@ -263,9 +267,8 @@ static int chrg_sink_work_init(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) regs[0] = REG_REL_ON; vals[0] = ALL_REL_OFF; regs[1] = REG_REL_ON; vals[1] = FU_REL_ON; regs[2] = REG_CURRENT_OUT + 1; vals[2] = 0; - regs[3] = REG_MODE; vals[3] = pSW->CV_mode; - regs[4] = Eload_Start_V_ON; vals[4] = - (pSW->sink.volt_on <= 500) ? 500 : pSW->sink.volt_on; + regs[3] = REG_MODE; vals[3] = pSW->CV_mode; + regs[4] = Eload_Start_V_ON; vals[4] = (pSW->sink.volt_on <= 500) ? 500 : pSW->sink.volt_on; regs[5] = ModbusRTU_ShortTest_CMD_MODE_FLAG; vals[5] = ModbusRTU_DYNA_CMD_MODE_STOP; count = 6U; @@ -875,9 +878,18 @@ static rt_uint8_t chrg_sink_voltage_confirm_count(rt_uint16_t target_volt_mv) SINK_VOLT_CONFIRM_5V_COUNT : SINK_VOLT_CONFIRM_NORMAL_COUNT; } +static rt_uint16_t chrg_sink_von_voltage_get(const struct chrg_switch_t *pSW) +{ +#if SINK_VON_VOLTAGE_SOURCE == SINK_VON_VOLTAGE_FROM_PROTOCOL + return pSW->Sink_voltage; +#else + return pSW->Now_voltage; +#endif +} + /***************************************************************** 函数名称： chrg_sink_volt_judge -函数描述： 使用南向功率板实际电压Now_voltage与V_On比较，驱动负载进入RUNING +函数描述： 使用配置的V_On电压源与V_On比较，控制负载启停 输入参数： idx:南向通道 pSW:通道控制结构体 输出参数： 更新sink.work_mode并调用chrg_sink_work 返回说明： 0:处理完成 <0:参数错误 @@ -890,20 +902,31 @@ int chrg_sink_volt_judge(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) static rt_uint8_t volt_set_ok[TOTAL_SOU_CHS] = {0}; static rt_uint8_t volt_stable_count[TOTAL_SOU_CHS] = {0}; static rt_tick_t running_start_tick[TOTAL_SOU_CHS] = {0}; + rt_uint16_t von_voltage; if ((idx >= TOTAL_SOU_CHS) || (pSW == RT_NULL)) { return -1; } +#if SINK_VON_VOLTAGE_SOURCE == SINK_VON_VOLTAGE_FROM_PROTOCOL + if (pSW->Sink_voltage_seq == g_sink_von_voltage_seq[idx]) { + return chrg_sink_work(idx, pSW); + } + g_sink_von_voltage_seq[idx] = pSW->Sink_voltage_seq; +#endif + von_voltage = chrg_sink_von_voltage_get(pSW); stable_confirm_count = chrg_sink_voltage_confirm_count( pSW->sink.pro_loadv); if ((pSW->sink.On_work == 1) && (pSW->sink.test.test_mode == 0)) { - if (pSW->Now_voltage <= WORK_MIN_VOLT) { + if (von_voltage <= WORK_MIN_VOLT) { volt_stable_count[idx] = 0; if (volt_set_ok[idx] == 1 && ++volt_low[idx] >= 50) { volt_set_ok[idx] = 0; no_curr[idx] = 0; } + if (pSW->sink.work_mode == SINK_WORK_RUNING) { + return chrg_sink_work_load_stop(idx, pSW); + } } else { volt_low[idx] = 0; volt_set_ok[idx] = 1; @@ -918,7 +941,7 @@ int chrg_sink_volt_judge(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) /* 掉电安全批次完成前，不得进入RUNING。 */ volt_stable_count[idx] = 0; no_curr[idx] = 0; - } else if (pSW->Now_voltage > pSW->sink.volt_on) { + } else if (von_voltage > pSW->sink.volt_on) { if ((pSW->sink.work_mode != SINK_WORK_RUNING) && (pSW->sink.work_mode != SINK_WORK_LOAD_STANDBY)) { if (volt_stable_count[idx] < stable_confirm_count) { @@ -934,6 +957,10 @@ int chrg_sink_volt_judge(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) } else if (pSW->sink.work_mode == SINK_WORK_LOAD_STANDBY) { volt_stable_count[idx] = 0; no_curr[idx] = 0; + if (chrg_sink_load_should_start(pSW)) { + /* 因输入电压不足停止带载后，电压恢复时重新进入稳定确认。 */ + pSW->sink.work_mode = SINK_WORK_WAIT; + } } else if ((pSW->Now_current > 200) || (pSW->sink.loadc < 200)) { volt_stable_count[idx] = 0; no_curr[idx] = 0; @@ -948,6 +975,10 @@ int chrg_sink_volt_judge(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) } else { volt_stable_count[idx] = 0; no_curr[idx] = 0; + /* 配置电压源低于负载设置的V_On时，立即停止电子负载。 */ + if (pSW->sink.work_mode == SINK_WORK_RUNING) { + return chrg_sink_work_load_stop(idx, pSW); + } } } } else { diff --git a/apps/chrg/applications/utils/chrg_sink.h b/apps/chrg/applications/utils/chrg_sink.h index 92a185a..88bfee7 100644 --- a/apps/chrg/applications/utils/chrg_sink.h +++ b/apps/chrg/applications/utils/chrg_sink.h @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_sink.c 完成日期 : -当前版本号 : V1.0 +当前版本号 : V1.1.14 主要功能 : 北向数据sink请求数据填充及发送，命令字定义。 版本历史 : 创建原始版本 说明 : @@ -22,7 +22,7 @@ struct chrg_switch_t; #define SINK_TEST_OCP 2 #define SINK_TEST_DYNA 3 /* 短路测试期间按该周期补发WORK_START，防止功率板因超时停止。 */ -#define SINK_SHORT_START_INTERVAL_MS 30U +#define SINK_SHORT_START_INTERVAL_MS 50U //短路测试结构体 struct test_short { rt_uint16_t hold_time; // 短路测试时间 diff --git a/apps/chrg/applications/utils/chrg_source.c b/apps/chrg/applications/utils/chrg_source.c index 51276f4..dedc8da 100644 --- a/apps/chrg/applications/utils/chrg_source.c +++ b/apps/chrg/applications/utils/chrg_source.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_source.c 完成日期 : -当前版本号 : V1.1.10 +当前版本号 : V1.1.14 主要功能 : 北向数据source请求数据填充及发送。 版本历史 : 创建原始版本 说明 : diff --git a/apps/chrg/applications/utils/chrg_source.h b/apps/chrg/applications/utils/chrg_source.h index d45f908..1ed7427 100644 --- a/apps/chrg/applications/utils/chrg_source.h +++ b/apps/chrg/applications/utils/chrg_source.h @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_source.c 完成日期 : -当前版本号 : V1.1.10 +当前版本号 : V1.1.14 主要功能 : 北向数据source请求数据填充及发送，命令字定义。 版本历史 : 创建原始版本 说明 : diff --git a/apps/chrg/codex_von_verify.log b/apps/chrg/codex_von_verify.log new file mode 100644 index 0000000..d8bf63b --- /dev/null +++ b/apps/chrg/codex_von_verify.log @@ -0,0 +1,9 @@ +*** Using Compiler 'V6.16', folder: 'D:\keil mdk 2\ARM\ARMCLANG\Bin' +Build target 'chrg' +compiling chrg_comm.c... +linking... +Program Size: Code=151160 RO-data=15928 RW-data=9356 ZI-data=16036 +FromELF: creating hex file... +After Build - User command #1: fromelf --bin .\build\keil\Obj\chrg.axf -o build/chrg.bin +".\build\keil\Obj\chrg.axf" - 0 Error(s), 0 Warning(s). +Build Time Elapsed: 00:00:02 diff --git a/docs/修改日志.md b/docs/修改日志.md index 5748045..c6b2ce1 100644 --- a/docs/修改日志.md +++ b/docs/修改日志.md @@ -1,5 +1,17 @@ # 修改日志 +## V1.1.15 - 2026-09-09 + +### 运行中 V_On 更新 + +- Sink 通道处于运行状态时，参数生效检测到 `V_On` 改变，会向对应功率板下发 `Eload_Start_V_ON`。 +- 下发值保持既有下限：小于或等于 `500mV` 时按 `500mV` 发送。 +- 南向队列提交失败时，本次参数生效返回忙，协议板运行参数保持原 `V_On`。 + +### 验证记录 + +- 待硬件验证：运行中修改 `SINK_REG_VON_VOLT (0x0B)` 并执行参数生效，确认功率板收到 `Eload_Start_V_ON` 新值。 + ## V1.1.9 - 2026-08-25 ### Source 复位后的初始化流程 diff --git a/docs/协议板Boot_YMODEM上位机实现规则.md b/docs/协议板Boot_YMODEM上位机实现规则.md new file mode 100644 index 0000000..1cd9e1f --- /dev/null +++ b/docs/协议板Boot_YMODEM上位机实现规则.md @@ -0,0 +1,208 @@ +# 协议板 Boot：YMODEM 上位机实现规则 + +## 1. 适用范围 + +本文适用于 **PC 上位机通过 USART1 直连协议板 Boot**，传输协议为 YMODEM + CRC16。 + +不适用于“协议板 App 通过南向 Modbus `0x20` 转发功率板 Boot”的链路；该链路的报文封装、应答和状态机需要独立实现。 + +## 2. 基本要求 + +| 项目 | 规则 | +| --- | --- | +| 串口 | USART1，115200 bps，8N1，无校验、无流控 | +| 升级文件 | 必须发送已由现有打包工具生成的完整 `.upk` 文件 | +| 不支持的文件 | 裸 `.bin`，以及自行封装/加密但不符合工程 UPK 格式的文件 | +| 启动依据 | 等待 Boot 发出 ASCII `C`（`0x43`）后再开始传输 | +| Boot 上电等待 | 首次等待主机开始约 5 秒；超时后可能跳转 App | +| 传输中的帧间等待 | Boot 约 10 秒；上位机不得使相邻有效帧间隔达到 10 秒 | + +Boot 每约 1 秒发送一次 `C`。若没有收到 `C`，上位机不可直接发送 YMODEM 首帧；应提示设备未进入 Boot，或重新复位/触发其进入 Boot。 + +## 3. YMODEM 常量与帧格式 + +| 名称 | 值 | 含义 | +| --- | --- | --- | +| SOH | `0x01` | 128 字节数据包 | +| STX | `0x02` | 1024 字节数据包 | +| EOT | `0x04` | 数据结束 | +| ACK | `0x06` | 接收成功 | +| NAK | `0x15` | 接收失败/请求重发 | +| CAN | `0x18` | 取消传输 | +| C | `0x43` | 请求以 CRC16 模式发送 | + +数据包格式： + +```text +Header + PacketNo + (~PacketNo) + Data + CRC16_H + CRC16_L +``` + +| 包类型 | Data 长度 | 总长度 | +| --- | ---: | ---: | +| SOH | 128 | 133 | +| STX | 1024 | 1029 | + +CRC 算法必须为 **CRC-16/XMODEM**： + +```text +poly=0x1021, init=0x0000, RefIn=false, RefOut=false, XorOut=0x0000 +``` + +CRC 覆盖 `Data` 的全部固定长度字节（128 或 1024），并按 **高字节、低字节** 放在帧尾。 + +## 4. 包序号与数据填充 + +1. 元数据包必须使用 `SOH`，`PacketNo=0x00`，反码为 `0xFF`。 +2. 首个文件数据包使用 `PacketNo=0x01`；每得到 ACK 后序号加 1，按 8 位自然回绕。 +3. 数据包正常使用 `STX`（1024 字节）；最后一包不足 1024 字节时仍应补齐到 1024 字节，建议补 `0x1A`。 +4. Boot 校验包号、包号反码、帧长度与 CRC。任一校验失败会回复 NAK。 +5. 收到 NAK 时，必须重发**原完整帧**，包号不得递增。该 Boot 不将“前一帧重复包”当作成功帧，因此不能依赖重复包自动 ACK。 + +## 5. 元数据包规则 + +第一个包固定是包号 0 的 SOH 包，128 字节 Data 的内容为： + +```text +ASCII 文件名 + 0x00 + ASCII 十进制文件大小 + 0x00 + 其余补 0x00 +``` + +示例（文件名仅用于协议描述，实际可使用真实 `.upk` 文件名）： + +```text +protocol_v1.2.upk\0 123456\0 [其余填 0] +``` + +文件大小必须是待传输 `.upk` 的实际字节数。传输结束包也是 SOH/包号 0，但其 128 字节 Data 必须全部为 `0x00`。 + +## 6. `.upk` 文件要求 + +Boot 在接收数据后按 UPK 格式处理，而不是把它当作裸固件。 + +- 头部标识必须为 `UPK_IDENTIFIER=0x006B7075`（`"upk"`）。 +- UPK 头为 1 字节对齐、总计 96 字节，包含版本、目标分区、原始/包体大小、CRC 等字段。 +- 工程当前启用 AES-256-CBC 解密；上位机职责仅为原样传输既有打包工具产生的 `.upk`，无需也不得自行改变加密、CRC 或头内容。 +- Boot 根据 UPK 头确定下载与安装流程；当前配置会先写 download 分区，再更新 app 分区。 + +## 7. 完整正常时序 + +```text +Boot -> PC : C （每秒一次，等待开始） +PC -> Boot: SOH, 00, FF, 元数据, CRC +Boot -> PC : ACK +Boot -> PC : C （必须等待此 C） + +PC -> Boot: STX/SOH, 01, FE, 数据块, CRC +Boot -> PC : ACK +PC -> Boot: STX/SOH, 02, FD, 数据块, CRC +Boot -> PC : ACK +... （直至全部 .upk 数据发送完成） + +PC -> Boot: EOT +Boot -> PC : NAK +PC -> Boot: EOT +Boot -> PC : ACK +Boot -> PC : C +PC -> Boot: SOH, 00, FF, 128 字节全 0, CRC +Boot -> PC : ACK + +Boot : 校验 UPK、写 Flash、安装 App、校验 App，并可能跳转 App +``` + +关键点： + +- 元数据 ACK 后，必须等 Boot 的第二个 `C` 才能发送数据包。 +- 第一个 EOT 后，必须等 NAK；第二个 EOT 后，必须等 ACK。 +- 第二个 EOT 的 ACK 后，必须等 `C`，再发送结束空包。 +- Boot 处理擦除和 Flash 写入期间，ACK 可能延迟；PC 的单帧 ACK 等待建议设为 3～10 秒。 + +## 8. 上位机状态机（可直接实现） + +```text +WAIT_C_START + 收到 C -> SEND_META + +SEND_META + 发送包号 0 元数据 -> WAIT_META_ACK + +WAIT_META_ACK + ACK -> WAIT_C_DATA + NAK/超时 -> 重发元数据 + +WAIT_C_DATA + C -> SEND_DATA(包号=1) + +SEND_DATA + 发送当前数据包 -> WAIT_DATA_ACK + +WAIT_DATA_ACK + ACK -> 若还有数据：包号+1，SEND_DATA；否则 SEND_EOT_1 + NAK/超时 -> 重发当前数据包 + +SEND_EOT_1 + 发送 EOT -> WAIT_EOT_NAK + +WAIT_EOT_NAK + NAK -> SEND_EOT_2 + 超时 -> 重发 EOT（保持本状态） + +SEND_EOT_2 + 发送 EOT -> WAIT_EOT_ACK + +WAIT_EOT_ACK + ACK -> WAIT_C_END + NAK/超时 -> 重发 EOT + +WAIT_C_END + C -> SEND_END_PACKET + +SEND_END_PACKET + 发送包号 0 的全 0 SOH 包 -> WAIT_END_ACK + +WAIT_END_ACK + ACK -> TRANSFER_FINISHED + NAK/超时 -> 重发结束空包 +``` + +## 9. 超时、重发、取消与结果判定 + +| 事件 | 上位机处理 | +| --- | --- | +| 收到 ACK | 仅推进到下一协议状态；数据包 ACK 后才递增包号 | +| 收到 NAK | 立即重发当前完整帧，不改变包号和文件偏移 | +| 单帧等待超时 | 重发当前完整帧；建议最多连续 3 次 | +| 重发次数耗尽 | 发送 CAN 两次，标记升级传输失败 | +| 收到 CAN | 立即停止，标记 Boot 取消升级 | +| 用户取消 | 发送 CAN 两次，停止发送后续字节 | +| 无 C | 不开始发送，提示设备未进入 Boot 或串口参数/连线错误 | + +Boot 对单个 CAN 会进入取消流程并回 ACK；上位机仍建议按标准发送两个 CAN，并接受可能出现的 ACK。 + +`WAIT_*_ACK` 的建议超时为 3～10 秒，元数据后的 `WAIT_C_DATA`、结束阶段的 `WAIT_C_END` 建议为 10 秒。上位机可将串口接收设计为持续缓存并按字节解析，忽略调试文本或仅识别 `C/ACK/NAK/CAN` 控制字符，避免因分段到达造成误判。 + +## 10. 成功判定与日志 + +结束空包得到 ACK 仅表示 **YMODEM 文件传输完成**，不是最终“固件安装成功”的结构化回码。随后 Boot 仍需校验 `.upk`、写下载区、安装 App、校验 App。 + +上位机应分两级显示结果： + +1. `传输完成`：收到结束空包 ACK。 +2. `升级确认成功`：设备重启并进入 App 后，通过应用通信读取新固件版本（推荐）或观察 Boot/App 启动日志确认。 + +建议记录：开始时间、文件名/大小、每个包号、重试次数、控制字符、异常原因、传输完成时间和最终版本读取结果。 + +## 11. 与功率板 Boot 转发升级的边界 + +若上位机目标是功率板，而物理串口只连接协议板 App，则不能直接把本 YMODEM 原始字节流写到串口。需要按协议板 App 已实现/约定的 Modbus 扩展功能码 `0x20` 封装，再由 App 南向转发给功率板 Boot，并处理 App 的转发 ACK、`C`、NAK、超时和重发。 + +本文件可作为功率板转发方案中“YMODEM 内层状态机”的依据；外层 Modbus `0x20` 帧格式和升级进入/退出控制需以 `apps/chrg/applications/thread/chrg_comm.c`、`chrg_comm.h` 的实际实现为准，不能与协议板 Boot 直连流程混用。 + +## 12. 代码依据 + +- `apps/boot/application/main.c`：USART1/USART2 初始化及 Boot 启动。 +- `apps/boot/application/func/transfer.c`：USART1 接收传输层。 +- `apps/boot/application/include/ymodem.h`：YMODEM 常量、包定义。 +- `apps/boot/application/func/ymodem.c`：YMODEM 状态机、C/ACK/NAK/EOT 时序和超时。 +- `apps/boot/application/func/app.c`：UPK 接收、校验、写入和安装流程。 +- `apps/boot/application/include/firmware.h`：UPK 头和分区相关定义。 +- `apps/boot/application/func/utils.c`：CRC-16/XMODEM 实现。 +- `apps/boot/application/include/app_config.h`：超时、分区和 AES 配置。 From d231a497714f2cb0c54dc07302cc396a572edf53 Mon Sep 17 00:00:00 2001 From: wrh Date: Thu, 10 Sep 2026 16:43:43 +0800 Subject: [PATCH 2/4] =?UTF-8?q?=E7=9F=AD=E8=B7=AF=E6=B5=8B=E8=AF=95?= =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E5=85=88=E4=B8=8B=E5=8F=91V=5FON=E4=B8=BA500?= =?UTF-8?q?mv=E7=9A=84=E9=80=BB=E8=BE=91=E3=80=82=E8=AE=A9=E5=85=85?= =?UTF-8?q?=E7=94=B5=E5=A4=B4=E4=B8=80=E5=B8=A6=E7=94=B5=E5=B0=B1=E6=89=93?= =?UTF-8?q?=E5=97=9D=20=E5=88=87=E6=8D=A2=E5=8D=8F=E8=AE=AE=E5=92=8CCC?= =?UTF-8?q?=E7=BA=BF=E6=97=B6=EF=BC=8C=E5=B0=86V=5FON=E8=AE=BE=E7=BD=AE?= =?UTF-8?q?=E9=A1=BA=E5=BA=8F=E8=B0=83=E6=95=B4=EF=BC=8C=E9=81=BF=E5=85=8D?= =?UTF-8?q?=E6=8C=87=E4=BB=A4=E8=A2=AB=E6=B8=85=E6=A5=9A?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit feat: 发布V1.1.19版本，优化短路测试与电压恢复逻辑 1. 更新所有文件版本号到V1.1.19，固件版本寄存器改为0x0123 2. 新增短路测试最低启动电压宏，设置为500mV，绕过普通V_ON门槛 3. 调整南向COM单次最大发送条数为8条，优化通信批次 4. 重构电压稳定确认逻辑，新增自动停止后恢复确认计数 5. 优化协议软卸载与完整握手流程，统一下发WORK_STOP和V_ON命令 6. 新增修改日志文档，补充本次更新说明与验证项 7. 新增UPK打包规则与YMODEM上位机实现文档 --- apps/chrg/applications/thread/chrg_comm.c | 14 ++- apps/chrg/applications/thread/chrg_comm.h | 2 +- apps/chrg/applications/thread/chrg_north.h | 7 +- apps/chrg/applications/utils/chrg_sink.c | 122 ++++++++++++++------- apps/chrg/applications/utils/chrg_sink.h | 8 +- apps/chrg/codex_von_restart_verify.log | 21 ++++ docs/修改日志.md | 55 ++++++++++ docs/协议板Boot_UPK打包规则.md | 84 ++++++++++++++ docs/协议板Boot_YMODEM上位机实现规则.md | 23 ++-- 9 files changed, 279 insertions(+), 57 deletions(-) create mode 100644 apps/chrg/codex_von_restart_verify.log create mode 100644 docs/协议板Boot_UPK打包规则.md diff --git a/apps/chrg/applications/thread/chrg_comm.c b/apps/chrg/applications/thread/chrg_comm.c index 4796e4f..89f0e1e 100644 --- a/apps/chrg/applications/thread/chrg_comm.c +++ b/apps/chrg/applications/thread/chrg_comm.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_comm.c 完成日期 : -当前版本号 : V1.1.15 +当前版本号 : V1.1.19 主要功能 : 实现对外通讯协议 MODBUS 服务端，以独立线程等待处理响应请求数据。 版本历史 : 创建原始版本 说明 : @@ -27,7 +27,7 @@ #include "stm32f4xx_hal.h" #define HOLD_REG_FIRMWARE_VERSION 0x0300U /* 协议板固件版本，只读 */ -#define CHRG_FIRMWARE_VERSION 0x011FU /* 当前协议板版本：V1.1.15 */ +#define CHRG_FIRMWARE_VERSION 0x0123U /* 当前协议板版本：V1.1.19 */ rt_uint8_t ucDiscInBuf[(TOTAL_DISC_REGS+BITS_UCHAR-1)/BITS_UCHAR]; rt_uint8_t ucCoilBuf[(TOTAL_COIL_REGS+BITS_UCHAR-1)/BITS_UCHAR]; @@ -618,7 +618,7 @@ eMBException funcReadHoldingRegister (rt_uint8_t *reqFrame, rt_uint16_t reqLen, /* * 协议板版本号使用独立的只读地址0x0300，不占用现有通道保持寄存器空间。 - * 当前版本V1.1.15编码为0x011F，Modbus响应按高字节在前返回01 1F。 + * 当前版本V1.1.19编码为0x0123，Modbus响应按高字节在前返回01 23。 * 该特殊地址只支持一次读取一个寄存器，避免与普通连续寄存器混用。 */ if (regAddress == HOLD_REG_FIRMWARE_VERSION) { @@ -2589,7 +2589,13 @@ static eMBException chrg_comm_apply_sink_effect(rt_uint8_t ch, protocol_voltage_only = diff_info.pro_voltage_changed && !full_handshake_change && !protocol_current_change; von_changed = (pReal->sink.volt_on != pShadow->sink.volt_on); - if ((sink_work == 0x01) && (old_on_work == 1U) && von_changed) { + /* 完整握手或协议软卸载会先清理本通道批次，V_ON由对应状态机在 + * WORK_STOP之后重新加入；普通参数变化仍在这里立即下发。 */ + if ((sink_work == 0x01) && (old_on_work == 1U) && von_changed && + !full_handshake_change && !protocol_voltage_only && + !protocol_current_change && + (pReal->sink.test.test_mode != SINK_TEST_SHORT) && + (pShadow->sink.test.test_mode != SINK_TEST_SHORT)) { rt_uint16_t reg = Eload_Start_V_ON; rt_uint16_t val = (pShadow->sink.volt_on <= 500U) ? 500U : pShadow->sink.volt_on; diff --git a/apps/chrg/applications/thread/chrg_comm.h b/apps/chrg/applications/thread/chrg_comm.h index 76e30ec..ae6882f 100644 --- a/apps/chrg/applications/thread/chrg_comm.h +++ b/apps/chrg/applications/thread/chrg_comm.h @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_comm.h 完成日期 : -当前版本号 : V1.1.15 +当前版本号 : V1.1.19 主要功能 : 实现对外通讯协议 MODBUS 服务端，以独立线程等待处理响应请求数据。 版本历史 : 创建原始版本 说明 : diff --git a/apps/chrg/applications/thread/chrg_north.h b/apps/chrg/applications/thread/chrg_north.h index a67152e..0cc23a2 100644 --- a/apps/chrg/applications/thread/chrg_north.h +++ b/apps/chrg/applications/thread/chrg_north.h @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_north.h 完成日期 : -当前版本号 : V1.1.14 +当前版本号 : V1.1.19 主要功能 : 实现北向通信交互，包括接收命令解析，发送请求命令，切换通路。以独立线程处理。 版本历史 : 创建原始版本 说明 : @@ -28,7 +28,10 @@ #endif /* 南向COM批次中单通道连续收到有效回码后的最大发送条数。 */ -#define SOU_COM_BURST_MAX 10U +#define SOU_COM_BURST_MAX 8U + +/* 自动停止带载后，电压恢复时需要连续确认的新P1采样帧数。 */ +#define SINK_LOAD_RESTART_CONFIRM_COUNT 3U #define THR_NAME_NORTH "thr.nor" #define DEV_NAME_NORTH "uart3" diff --git a/apps/chrg/applications/utils/chrg_sink.c b/apps/chrg/applications/utils/chrg_sink.c index fb28740..8c52063 100644 --- a/apps/chrg/applications/utils/chrg_sink.c +++ b/apps/chrg/applications/utils/chrg_sink.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_sink.c 完成日期 : -当前版本号 : V1.1.14 +当前版本号 : V1.1.19 主要功能 : 北向数据sink请求数据填充及发送。 版本历史 : 创建原始版本 说明 : @@ -41,10 +41,12 @@ static rt_tick_t g_sink_unload_query_tick[TOTAL_SOU_CHS] = {0}; static rt_uint8_t g_sink_unload_confirm_count[TOTAL_SOU_CHS] = {0}; /* 记录各通道短路测试最近一次WORK_START的发送时间。 */ static rt_tick_t g_sink_short_start_tick[TOTAL_SOU_CHS] = {0}; -#if SINK_VON_VOLTAGE_SOURCE == SINK_VON_VOLTAGE_FROM_PROTOCOL -/* 只消费新的协议板0x20电压回码，避免同一帧重复计入稳定次数。 */ +/* 只消费新的V_On电压采样，避免同一帧重复计入稳定确认。 */ static rt_uint32_t g_sink_von_voltage_seq[TOTAL_SOU_CHS] = {0}; -#endif +/* 协议切换期间清零，避免旧电压样本累计成启动确认。 */ +static rt_uint8_t g_sink_von_stable_count[TOTAL_SOU_CHS] = {0}; +/* 自动停止带载后的恢复确认计数，独立于首次握手的电压确认计数。 */ +static rt_uint8_t g_sink_load_restart_confirm_count[TOTAL_SOU_CHS] = {0}; enum { SINK_UNLOAD_NEXT_RUNNING = 0, @@ -447,9 +449,15 @@ static int chrg_sink_work_load_stop(eIDX_SOU_CH idx, if ((idx >= TOTAL_SOU_CHS) || (pSW == RT_NULL)) { return -1; } + /* 自动停止优先于同通道残留启动批次，禁止STOP后继续发送WORK_START。 */ + if (chrg_sou_com_batch_cancel(idx) != 0) { + return -1; + } if (chrg_sou_com_batch_submit(idx, ®, &val, 1U) != 0) { return -1; } + g_sink_von_stable_count[idx] = 0U; + g_sink_load_restart_confirm_count[idx] = 0U; pSW->sink.work_mode = SINK_WORK_LOAD_STANDBY; return 0; } @@ -665,15 +673,23 @@ static int chrg_sink_work_switch(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) *****************************************************************/ static int chrg_sink_work_protocol_unload(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) { - rt_uint16_t reg = REG_WORK; - rt_uint16_t value = WORK_STOP; + rt_uint16_t regs[2] = {REG_WORK, Eload_Start_V_ON}; + rt_uint16_t values[2]; - if (chrg_sou_com_batch_submit(idx, ®, &value, 1U) != 0) { + if ((idx >= TOTAL_SOU_CHS) || (pSW == RT_NULL)) { + return -1; + } + values[0] = WORK_STOP; + values[1] = (pSW->sink.volt_on <= 500U) ? 500U : pSW->sink.volt_on; + + if (chrg_sou_com_batch_submit(idx, regs, values, 2U) != 0) { return -1; } /* WORK_STOP回码只确认命令接收；还需连续读取两帧合格的实际电流。 */ chrg_sink_unload_confirm_reset(idx); + g_sink_von_stable_count[idx] = 0U; + g_sink_load_restart_confirm_count[idx] = 0U; pSW->sink.work_mode = SINK_WORK_UNLOAD_WAIT; return 0; } @@ -683,31 +699,35 @@ static int chrg_sink_work_protocol_unload(eIDX_SOU_CH idx, struct chrg_switch_t 函数描述： 执行协议或CC完整重握手前的南向安全断开和副继电器恢复 输入参数： idx:南向功率板通道 pSW:当前通道控制结构体 输出参数： 命令提交成功后进入SINK_WORK_HANDSHAKE_WAIT -返回说明： 0:四条命令提交成功 <0:参数或命令提交失败 -其它说明： 命令顺序固定为WORK_STOP、CURRENT=1000mA、ALL_REL_OFF、FU_REL_ON； - WORK_STOP已关闭电子负载，1000mA仅为功率板停止阶段保存的电流设定值； +返回说明： 0:两条命令提交成功 <0:参数或命令提交失败 + 其它说明： 命令顺序固定为WORK_STOP、Eload_Start_V_ON； + WORK_STOP已关闭电子负载，V_ON随后更新到功率板； 主副继电器全部断开并确认回码后再单独打开副继电器； 北向Sink继电器保持接通，低电流确认完成后才允许重新握手 *****************************************************************/ static int chrg_sink_work_handshake_prepare(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) { - rt_uint16_t reg = REG_WORK; - rt_uint16_t value = WORK_STOP; + rt_uint16_t regs[2] = {REG_WORK, Eload_Start_V_ON}; + rt_uint16_t values[2]; if ((idx >= TOTAL_SOU_CHS) || (pSW == RT_NULL)) { return -1; } + values[0] = WORK_STOP; + values[1] = (pSW->sink.volt_on <= 500U) ? 500U : pSW->sink.volt_on; /* 新CC/协议事务必须抢占本通道尚未发送的旧启动和设定命令。 */ if (chrg_sou_com_batch_cancel(idx) != 0) { return -1; } - if (chrg_sou_com_batch_submit(idx, ®, &value, 1U) != 0) { + if (chrg_sou_com_batch_submit(idx, regs, values, 2U) != 0) { return -1; } /* 协议或CC切换先停止电子负载，连续2次确认低电流后再操作继电器。 */ chrg_sink_unload_confirm_reset(idx); + g_sink_von_stable_count[idx] = 0U; + g_sink_load_restart_confirm_count[idx] = 0U; pSW->sink.work_mode = SINK_WORK_HANDSHAKE_WAIT; return 0; } @@ -719,7 +739,7 @@ static int chrg_sink_work_handshake_prepare(eIDX_SOU_CH idx, full_handshake:RT_TRUE为完整重握手 RT_FALSE为协议参数软卸载 输出参数： 确认成功后将sink.work_mode切换为SINK_WORK_WAIT 返回说明： 0:继续等待或确认成功 <0:状态查询或优先量测请求失败 -其它说明： 软卸载只要求WORK_STOP收到匹配回码后建立量测基线；完整重握手 + 其它说明： 软卸载要求WORK_STOP和V_ON收到匹配回码后建立量测基线；完整重握手 还要求CURRENT=1000mA、ALL_REL_OFF和FU_REL_ON回码成功，但保持北向Sink继电器接通 *****************************************************************/ static int chrg_sink_work_current_wait(eIDX_SOU_CH idx, @@ -831,13 +851,14 @@ static int chrg_sink_TEST_DYNA_ON(rt_uint8_t ch, struct chrg_switch_t *pSW) *****************************************************************/ static int chrg_sink_TEST_SHORT_ON(rt_uint8_t ch, struct chrg_switch_t *pSW) { - rt_uint16_t regs[3] = {ModbusRTU_ShortTest_Hold_Time,ModbusRTU_ShortTest_CMD_MODE_FLAG, REG_WORK}; - rt_uint16_t vals[3] = {0,0,0}; + rt_uint16_t regs[4] = {Eload_Start_V_ON, ModbusRTU_ShortTest_Hold_Time, + ModbusRTU_ShortTest_CMD_MODE_FLAG, REG_WORK}; + rt_uint16_t vals[4] = {SINK_SHORT_TEST_VON_MV, 0, 0, 0}; /* 外部工程固定短路测试保持60秒且不带载。 */ - vals[0] = 60000; - vals[1] = ModbusRTU_DYNA_CMD_MODE_RUN_NO_CURR; - vals[2] = WORK_START; - if (chrg_sou_com_batch_submit((eIDX_SOU_CH)ch, regs, vals, 3) == 0) { + vals[1] = 60000; + vals[2] = ModbusRTU_DYNA_CMD_MODE_RUN_NO_CURR; + vals[3] = WORK_START; + if (chrg_sou_com_batch_submit((eIDX_SOU_CH)ch, regs, vals, 4) == 0) { g_sink_short_start_tick[ch] = rt_tick_get(); return 0; } @@ -897,10 +918,10 @@ static rt_uint16_t chrg_sink_von_voltage_get(const struct chrg_switch_t *pSW) int chrg_sink_volt_judge(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) { rt_uint8_t stable_confirm_count; + rt_uint32_t voltage_seq; static rt_uint8_t volt_low[TOTAL_SOU_CHS] = {0}; static rt_uint8_t no_curr[TOTAL_SOU_CHS] = {0}; static rt_uint8_t volt_set_ok[TOTAL_SOU_CHS] = {0}; - static rt_uint8_t volt_stable_count[TOTAL_SOU_CHS] = {0}; static rt_tick_t running_start_tick[TOTAL_SOU_CHS] = {0}; rt_uint16_t von_voltage; @@ -908,18 +929,32 @@ int chrg_sink_volt_judge(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) return -1; } #if SINK_VON_VOLTAGE_SOURCE == SINK_VON_VOLTAGE_FROM_PROTOCOL - if (pSW->Sink_voltage_seq == g_sink_von_voltage_seq[idx]) { + voltage_seq = pSW->Sink_voltage_seq; +#else + voltage_seq = chrg_eload_get_sample_seq(idx); +#endif + if (voltage_seq == g_sink_von_voltage_seq[idx]) { + return chrg_sink_work(idx, pSW); + } + g_sink_von_voltage_seq[idx] = voltage_seq; + /* 卸载和协议重配尚未完成时，旧电压只能用于推进安全流程，不能触发WORK_START。 */ + if ((pSW->sink.work_mode == SINK_WORK_UNLOAD_WAIT) || + (pSW->sink.work_mode == SINK_WORK_HANDSHAKE_WAIT) || + ((pSW->sink.work_mode != SINK_WORK_RUNING) && + (pSW->sink.work_mode != SINK_WORK_LOAD_STANDBY) && + (pSW->sub != IDX_GET_SINK_VC))) { + g_sink_von_stable_count[idx] = 0U; + g_sink_load_restart_confirm_count[idx] = 0U; return chrg_sink_work(idx, pSW); } - g_sink_von_voltage_seq[idx] = pSW->Sink_voltage_seq; -#endif von_voltage = chrg_sink_von_voltage_get(pSW); stable_confirm_count = chrg_sink_voltage_confirm_count( pSW->sink.pro_loadv); if ((pSW->sink.On_work == 1) && (pSW->sink.test.test_mode == 0)) { if (von_voltage <= WORK_MIN_VOLT) { - volt_stable_count[idx] = 0; + g_sink_von_stable_count[idx] = 0U; + g_sink_load_restart_confirm_count[idx] = 0U; if (volt_set_ok[idx] == 1 && ++volt_low[idx] >= 50) { volt_set_ok[idx] = 0; no_curr[idx] = 0; @@ -933,47 +968,58 @@ int chrg_sink_volt_judge(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) pSW->change_flag = 0; if (pSW->sink.work_mode == SINK_WORK_LOW_MONITOR) { /* 副继电器恢复后首次重新检测到输入电压，只启动协议重握手。 */ - volt_stable_count[idx] = 0; + g_sink_von_stable_count[idx] = 0U; no_curr[idx] = 0; pSW->sink.work_mode = SINK_WORK_WAIT; } else if ((pSW->sink.work_mode == SINK_WORK_LOW) || (pSW->sink.work_mode == SINK_WORK_LOW_AUX_WAIT)) { /* 掉电安全批次完成前，不得进入RUNING。 */ - volt_stable_count[idx] = 0; + g_sink_von_stable_count[idx] = 0U; no_curr[idx] = 0; } else if (von_voltage > pSW->sink.volt_on) { if ((pSW->sink.work_mode != SINK_WORK_RUNING) && (pSW->sink.work_mode != SINK_WORK_LOAD_STANDBY)) { - if (volt_stable_count[idx] < stable_confirm_count) { - volt_stable_count[idx]++; + if (g_sink_von_stable_count[idx] < stable_confirm_count) { + g_sink_von_stable_count[idx]++; } - if (volt_stable_count[idx] >= stable_confirm_count) { + if (g_sink_von_stable_count[idx] >= stable_confirm_count) { /* 连续达到当前目标对应的确认帧数后进入RUNING。 */ - volt_stable_count[idx] = 0; + g_sink_von_stable_count[idx] = 0U; pSW->sink.work_mode = SINK_WORK_RUNING; running_start_tick[idx] = rt_tick_get(); no_curr[idx] = 0; } } else if (pSW->sink.work_mode == SINK_WORK_LOAD_STANDBY) { - volt_stable_count[idx] = 0; no_curr[idx] = 0; if (chrg_sink_load_should_start(pSW)) { - /* 因输入电压不足停止带载后，电压恢复时重新进入稳定确认。 */ - pSW->sink.work_mode = SINK_WORK_WAIT; + /* 自动停止后只接受新的电压采样；达到恢复确认帧数才允许重启。 */ + if (g_sink_load_restart_confirm_count[idx] < + SINK_LOAD_RESTART_CONFIRM_COUNT) { + g_sink_load_restart_confirm_count[idx]++; + } + if (g_sink_load_restart_confirm_count[idx] >= + SINK_LOAD_RESTART_CONFIRM_COUNT) { + g_sink_load_restart_confirm_count[idx] = 0U; + pSW->sink.work_mode = SINK_WORK_RUNING; + running_start_tick[idx] = rt_tick_get(); + } + } else { + g_sink_load_restart_confirm_count[idx] = 0U; } } else if ((pSW->Now_current > 200) || (pSW->sink.loadc < 200)) { - volt_stable_count[idx] = 0; + g_sink_von_stable_count[idx] = 0U; no_curr[idx] = 0; } else if ((rt_tick_t)(rt_tick_get() - running_start_tick[idx]) >= rt_tick_from_millisecond(SINK_CURRENT_START_GRACE_MS)) { - volt_stable_count[idx] = 0; + g_sink_von_stable_count[idx] = 0U; if (++no_curr[idx] >= 2) { pSW->sink.work_mode = SINK_WORK_WAIT; no_curr[idx] = 0; } } } else { - volt_stable_count[idx] = 0; + g_sink_von_stable_count[idx] = 0U; + g_sink_load_restart_confirm_count[idx] = 0U; no_curr[idx] = 0; /* 配置电压源低于负载设置的V_On时，立即停止电子负载。 */ if (pSW->sink.work_mode == SINK_WORK_RUNING) { @@ -985,7 +1031,7 @@ int chrg_sink_volt_judge(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) volt_low[idx] = 0; no_curr[idx] = 0; volt_set_ok[idx] = 0; - volt_stable_count[idx] = 0; + g_sink_von_stable_count[idx] = 0U; } return chrg_sink_work(idx, pSW); } diff --git a/apps/chrg/applications/utils/chrg_sink.h b/apps/chrg/applications/utils/chrg_sink.h index 88bfee7..9c6c009 100644 --- a/apps/chrg/applications/utils/chrg_sink.h +++ b/apps/chrg/applications/utils/chrg_sink.h @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_sink.c 完成日期 : -当前版本号 : V1.1.14 +当前版本号 : V1.1.19 主要功能 : 北向数据sink请求数据填充及发送，命令字定义。 版本历史 : 创建原始版本 说明 : @@ -23,6 +23,8 @@ struct chrg_switch_t; #define SINK_TEST_DYNA 3 /* 短路测试期间按该周期补发WORK_START，防止功率板因超时停止。 */ #define SINK_SHORT_START_INTERVAL_MS 50U +/* 短路测试不受普通V_ON门槛限制，功率板使用最低启动电压。 */ +#define SINK_SHORT_TEST_VON_MV 500U //短路测试结构体 struct test_short { rt_uint16_t hold_time; // 短路测试时间 @@ -212,8 +214,8 @@ enum { /* Sink电压稳定确认参数，供chrg_sink_volt_judge使用。 */ #define SINK_VOLT_5V_TARGET_MV 5000U -#define SINK_VOLT_CONFIRM_NORMAL_COUNT 5U -#define SINK_VOLT_CONFIRM_5V_COUNT 15U +#define SINK_VOLT_CONFIRM_NORMAL_COUNT 3U +#define SINK_VOLT_CONFIRM_5V_COUNT 12U #define SINK_CURRENT_START_GRACE_MS 200U /* 主继电器闭合后的0V持续监控：由北向轮询线程每轮调用，掉电立即转掉电保护。 */ diff --git a/apps/chrg/codex_von_restart_verify.log b/apps/chrg/codex_von_restart_verify.log new file mode 100644 index 0000000..d573f4b --- /dev/null +++ b/apps/chrg/codex_von_restart_verify.log @@ -0,0 +1,21 @@ +*** Using Compiler 'V6.16', folder: 'D:\keil mdk 2\ARM\ARMCLANG\Bin' +Build target 'chrg' +compiling chrg_north_pkg.c... +compiling chrg_vcom.c... +compiling chrg_thread.c... +compiling chrg_lcd.c... +compiling chrg_rel.c... +compiling chrg_eload.c... +compiling chrg_south.c... +compiling chrg_sink.c... +compiling chrg_north.c... +compiling chrg_source.c... +compiling chrg_roll_nor.c... +compiling chrg_roll_sou.c... +compiling chrg_comm.c... +linking... +Program Size: Code=151456 RO-data=15928 RW-data=9356 ZI-data=16052 +FromELF: creating hex file... +After Build - User command #1: fromelf --bin .\build\keil\Obj\chrg.axf -o build/chrg.bin +".\build\keil\Obj\chrg.axf" - 0 Error(s), 0 Warning(s). +Build Time Elapsed: 00:00:05 diff --git a/docs/修改日志.md b/docs/修改日志.md index c6b2ce1..469c7b1 100644 --- a/docs/修改日志.md +++ b/docs/修改日志.md @@ -1,5 +1,60 @@ # 修改日志 +## V1.1.19 - 2026-09-10 + +### 短路测试绕过 V_ON 门槛 + +- 短路测试启动批次增加 `Eload_Start_V_ON=500mV`，保证5V输入时不因用户设置的6V V_ON而拒绝短路启动。 +- 短路测试期间忽略普通 V_ON 更新，保持功率板使用500mV短路启动门槛。 +- 退出短路测试时由初始化流程恢复用户设定的 V_ON。 +- 协议板版本号更新为 `V1.1.19`，固件版本寄存器更新为 `0x0123`。 + +### 验证记录 + +- 待硬件验证：V_ON=6V、输入PD5V时，短路模式仍能启动并按周期发送 `WORK_START`。 +- 待硬件验证：退出短路模式后，功率板恢复用户设定的 V_ON。 + +## V1.1.18 - 2026-09-10 + +### 修复 CC 切换时 V_ON 丢失 + +- 修复 V_ON 与 CC 线同时修改时，V_ON 命令先入队后被完整握手清队列取消的问题。 +- 协议软卸载和完整握手统一按 `WORK_STOP -> Eload_Start_V_ON` 顺序下发。 +- 握手或命令重试时会重新携带当前 V_ON，避免功率板继续使用旧阈值。 +- 协议板版本号更新为 `V1.1.18`，固件版本寄存器更新为 `0x0122`。 + +### 验证记录 + +- 待硬件验证：同时修改 V_ON 与 CC 线，确认功率板收到 `Eload_Start_V_ON`。 +- 待硬件验证：确认 CC 切换失败重试、协议电压切换和其他通道调度正常。 + +## V1.1.17 - 2026-09-10 + +### 协议切换期间禁止误启动 + +- 将 V_On 稳定确认计数提升为通道级状态，并在协议软卸载、完整握手和自动停止时清零。 +- `UNLOAD_WAIT`、`HANDSHAKE_WAIT` 以及协议配置未完成前，电压采样只推进安全流程，不允许进入 `RUNING` 或发送 `WORK_START`。 +- 协议/模式配置完成并回到 `IDX_GET_SINK_VC` 后，才重新累计 V_On 稳定确认帧，避免停止后约40ms因旧电压再次启动。 +- 协议板版本号更新为 `V1.1.17`，固件版本寄存器更新为 `0x0121`。 + +### 验证记录 + +- 待硬件验证：协议电压切换时确认 `WORK_STOP` 后、协议配置完成前不再出现 `WORK_START`。 +- 待硬件验证：确认协议切换、自动停止恢复和三个通道并行调度不受影响。 + +## V1.1.16 - 2026-09-09 + +### Sink 自动停止后的恢复保护 + +- 新增 `SINK_LOAD_RESTART_CONFIRM_COUNT`，位于 `chrg_north.h`，当前设为 `2U`。 +- 功率板电压作为 V_On 判定源时，仅消费新的 P1 采样帧，旧采样不再重复累计稳定次数。 +- 自动停止带载时取消本通道残留南向批次，再单独下发 `WORK_STOP`，避免残留 `WORK_START` 在停止后执行。 +- 自动恢复带载前必须收到连续 `2` 帧新的、满足 `V_On` 的电压采样。 + +### 验证记录 + +- 待硬件验证：触发 CH1 自动停止后，确认停止后 2 帧新P1到达前不再出现 `WORK_START`；同时确认其它通道南向命令正常调度。 + ## V1.1.15 - 2026-09-09 ### 运行中 V_On 更新 diff --git a/docs/协议板Boot_UPK打包规则.md b/docs/协议板Boot_UPK打包规则.md new file mode 100644 index 0000000..2829092 --- /dev/null +++ b/docs/协议板Boot_UPK打包规则.md @@ -0,0 +1,84 @@ +# 协议板 Boot：UPK 打包规则 + +## 1. 适用范围 + +本文用于实现协议板 App 固件的 `.upk` 打包和解析工具，适配 `apps/boot` 当前 Boot。传输层 YMODEM 规则见[协议板Boot_YMODEM上位机实现规则.md](协议板Boot_YMODEM上位机实现规则.md)。 + +## 2. 1K 文件布局 + +当前 Boot 收到第一个文件数据帧时，只取其中前 96 字节作为 UPK 头，**会忽略该帧其余数据**。因此打包文件必须使用固定 1024 字节首数据块： + +```text +输出 .upk 文件 +偏移 0x000 ~ 0x05F : 96 字节 UPK 逻辑头 +偏移 0x060 ~ 0x3FF : 928 字节 0x00 填充 +偏移 0x400 起 : package body（未加密 BIN 或 AES 加密后的 body） +``` + +- `.upk` 实际文件大小：`1024 + pkg_size`。 +- YMODEM 元数据包的文件大小必须为上述实际文件大小。 +- 上位机必须从偏移 0 开始以 `STX/1024` 发送；第一个 STX 是头区，真正 body 从第二个 STX 开始。 +- YMODEM 最后一帧的 `0x1A` 补齐仅属于传输层，不能计入文件大小、`raw_size` 或 `pkg_size`。 + +界面中的“表头尺寸 `1024 (ymodem1k)`”应改名为“YMODEM 首数据块/头区尺寸”，并固定为 1024；UPK 逻辑头固定为 96，不能让用户修改。 + +## 3. 输入、分区与版本 + +| 项目 | 规则 | +| --- | --- | +| 输入文件 | 仅协议板 App 裸 `bin`，例如 `apps/chrg/build/chrg.bin`；拒绝 `.hex`、`.elf`、已有 `.upk`。 | +| `name[4]` | 固定 ASCII `upk\0`。 | +| `part_name[16]` | 仅允许 `app`、`download`、`factory`，ASCII NUL 结尾；协议板常规升级默认 `app`，Boot 会修正为 `download` 后安装到 `app`。 | +| `fw_old_ver[16]` | 目标设备当前版本，前 4 字节为数值 `major, minor, fix, build`，其余 `0x00`。 | +| `fw_new_ver[16]` | 新固件版本，编码同上。 | +| 版本输入 | 界面应分别提供“当前/旧版本”与“新版本”；不能只保留一个版本号，且不得写 ASCII 版本字符串。 | +| `user_string[16]` | ASCII 水印最多 15 字节，NUL 结尾，其余 `0x00`。 | +| `timestamp` | 当前 Unix 时间戳，`uint32` 小端。 | +| 大小限制 | `raw_size <= 262144` 且 `pkg_size <= 262144`，即 App/download 分区各 256KB。 | + +## 4. 加密、大小与 CRC + +1. `raw_body` 为原始 `.bin`：`raw_size = len(raw_body)`，`raw_crc = crc32_boot(raw_body)`。 +2. 未加密：`package_body = raw_body`，`pkg_size = raw_size`，`pkg_crc = raw_crc`，`config[1]=0x00`。 +3. AES：`config[1]=0x01`，使用 AES-256-CBC；Key=`0123456789ABCDEF0123456789ABCDEF`，IV=`0123456789ABCDEF`。加密前 body 必须补齐到 16 字节整数倍；`pkg_size`、`pkg_crc`对应加密后的 body。Key、IV 必须与 Boot 编译配置一致。 +4. `config[0]`、`config[2]`、`config[3]` 固定 `0x00`。 +5. `head_crc = crc32_boot(逻辑头前 92 字节)`；最后 4 字节按小端写入 `head_crc`。 +6. 所有 `uint32` 字段按 STM32 小端序写入。 + +`crc32_boot()` 必须与 `apps/boot/application/func/utils.c` 的 `crc32_step(0xFFFFFFFF, data, size)` 完全一致；不能直接使用未校验的库默认 CRC32。 + +## 5. 96 字节逻辑头字段 + +```text +0x00 name[4] +0x04 config[4] +0x08 fw_old_ver[16] +0x18 fw_new_ver[16] +0x28 user_string[16] +0x38 part_name[16] +0x48 raw_size uint32 little-endian +0x4C pkg_size uint32 little-endian +0x50 timestamp uint32 little-endian +0x54 raw_crc uint32 little-endian +0x58 pkg_crc uint32 little-endian +0x5C head_crc uint32 little-endian +``` + +## 6. 打包完成前的强制自检 + +1. 重新解析刚生成的 `.upk`。 +2. 校验总长度是否为 `1024 + pkg_size`，并检查 `0x60~0x3FF` 全部为 `0x00`。 +3. 校验 `name`、分区名、版本字段、大小限制和 `head_crc`。 +4. 校验 `pkg_crc`；未加密时还必须校验 `raw_crc`。加密时使用相同 Key/IV 解密后校验 `raw_crc`。 +5. 解析页显示 `raw_size`、`pkg_size`、全部 CRC、加密状态、分区、旧/新版本和时间戳；任一项异常时禁止输出成功文件。 + +## 7. 当前样本 + +工程中的 `apps/chrg/chrg.upk` 已验证：实际长度 `155816`，`pkg_size=154792`，两者相差 1024，符合本规则。 + +## 8. 代码依据 + +- `apps/boot/application/include/firmware.h` +- `apps/boot/application/func/firmware.c` +- `apps/boot/application/func/app.c` +- `apps/boot/application/func/utils.c` diff --git a/docs/协议板Boot_YMODEM上位机实现规则.md b/docs/协议板Boot_YMODEM上位机实现规则.md index 1cd9e1f..47da7b4 100644 --- a/docs/协议板Boot_YMODEM上位机实现规则.md +++ b/docs/协议板Boot_YMODEM上位机实现规则.md @@ -16,8 +16,9 @@ | 启动依据 | 等待 Boot 发出 ASCII `C`（`0x43`）后再开始传输 | | Boot 上电等待 | 首次等待主机开始约 5 秒；超时后可能跳转 App | | 传输中的帧间等待 | Boot 约 10 秒；上位机不得使相邻有效帧间隔达到 10 秒 | +| 单帧发送方式 | 一个完整 YMODEM 帧必须连续写入串口；不得把同一帧拆开并在中间产生明显空闲间隔 | -Boot 每约 1 秒发送一次 `C`。若没有收到 `C`，上位机不可直接发送 YMODEM 首帧；应提示设备未进入 Boot，或重新复位/触发其进入 Boot。 +Boot 每约 1 秒发送一次 `C`。若没有收到 `C`，上位机不可直接发送 YMODEM 首帧；应提示设备未进入 Boot，或重新复位/触发其进入 Boot。Boot 的接收层按 UART 收帧处理，不会为上位机重组被空闲间隔拆断的 YMODEM 包。 ## 3. YMODEM 常量与帧格式 @@ -54,7 +55,7 @@ CRC 覆盖 `Data` 的全部固定长度字节（128 或 1024），并按 **高 1. 元数据包必须使用 `SOH`，`PacketNo=0x00`，反码为 `0xFF`。 2. 首个文件数据包使用 `PacketNo=0x01`；每得到 ACK 后序号加 1，按 8 位自然回绕。 -3. 数据包正常使用 `STX`（1024 字节）；最后一包不足 1024 字节时仍应补齐到 1024 字节，建议补 `0x1A`。 +3. 本 Boot 的 `.upk` 使用 1K 首数据块布局，因此文件数据包必须使用 `STX`（1024 字节）；最后一包不足 1024 字节时仍应补齐到 1024 字节，建议补 `0x1A`。 4. Boot 校验包号、包号反码、帧长度与 CRC。任一校验失败会回复 NAK。 5. 收到 NAK 时，必须重发**原完整帧**，包号不得递增。该 Boot 不将“前一帧重复包”当作成功帧，因此不能依赖重复包自动 ACK。 @@ -79,10 +80,12 @@ protocol_v1.2.upk\0 123456\0 [其余填 0] Boot 在接收数据后按 UPK 格式处理，而不是把它当作裸固件。 - 头部标识必须为 `UPK_IDENTIFIER=0x006B7075`（`"upk"`）。 -- UPK 头为 1 字节对齐、总计 96 字节，包含版本、目标分区、原始/包体大小、CRC 等字段。 -- 工程当前启用 AES-256-CBC 解密；上位机职责仅为原样传输既有打包工具产生的 `.upk`，无需也不得自行改变加密、CRC 或头内容。 +- UPK 逻辑头为 1 字节对齐、总计 96 字节，包含版本、目标分区、原始/包体大小、CRC 等字段。 +- 工程启用了 AES-256-CBC 解密组件，但不强制加密；`config[1]=0` 的未加密包和 `config[1]=1` 的 AES-256-CBC 包均可被当前 Boot 处理。 - Boot 根据 UPK 头确定下载与安装流程；当前配置会先写 download 分区，再更新 app 分区。 +打包输出的 `.upk` 必须符合[协议板Boot_UPK打包规则.md](协议板Boot_UPK打包规则.md)，特别是 1024 字节首数据块布局。YMODEM 元数据中的文件大小使用该 `.upk` 的实际字节数。 + ## 7. 完整正常时序 ```text @@ -91,9 +94,9 @@ PC -> Boot: SOH, 00, FF, 元数据, CRC Boot -> PC : ACK Boot -> PC : C （必须等待此 C） -PC -> Boot: STX/SOH, 01, FE, 数据块, CRC +PC -> Boot: STX, 01, FE, 数据块, CRC Boot -> PC : ACK -PC -> Boot: STX/SOH, 02, FD, 数据块, CRC +PC -> Boot: STX, 02, FD, 数据块, CRC Boot -> PC : ACK ... （直至全部 .upk 数据发送完成） @@ -168,15 +171,17 @@ WAIT_END_ACK | 事件 | 上位机处理 | | --- | --- | | 收到 ACK | 仅推进到下一协议状态；数据包 ACK 后才递增包号 | -| 收到 NAK | 立即重发当前完整帧，不改变包号和文件偏移 | -| 单帧等待超时 | 重发当前完整帧；建议最多连续 3 次 | -| 重发次数耗尽 | 发送 CAN 两次，标记升级传输失败 | +| 收到明确 NAK | 重发当前完整帧；建议最多连续 3 次 | +| 等待 ACK 超时 | 标记“传输结果不确定”，停止本次会话；重新进入 Boot 后从元数据包开始完整传输 | +| 明确 NAK 重发耗尽 | 发送 CAN 两次，标记升级传输失败 | | 收到 CAN | 立即停止，标记 Boot 取消升级 | | 用户取消 | 发送 CAN 两次，停止发送后续字节 | | 无 C | 不开始发送，提示设备未进入 Boot 或串口参数/连线错误 | Boot 对单个 CAN 会进入取消流程并回 ACK；上位机仍建议按标准发送两个 CAN，并接受可能出现的 ACK。 +> **当前 Boot 的可靠性限制：** 成功接收一个数据包后，Boot 已把期望包号加一；若该包的 ACK 在串口上丢失，上位机重发同一包会被 Boot 判为“重复包”并回复 NAK，而不是再次回复 ACK。因此“ACK 超时后无条件重发当前包”不能可靠恢复。本文规则可在直连、稳定的串口环境中正常升级；若要支持 ACK 丢失后的可靠自动重发，需要修改 Boot，使其收到“期望包号减一”的重复帧且 CRC 正确时直接回复 ACK、不再次写入数据。 + `WAIT_*_ACK` 的建议超时为 3～10 秒，元数据后的 `WAIT_C_DATA`、结束阶段的 `WAIT_C_END` 建议为 10 秒。上位机可将串口接收设计为持续缓存并按字节解析，忽略调试文本或仅识别 `C/ACK/NAK/CAN` 控制字符，避免因分段到达造成误判。 ## 10. 成功判定与日志 From 05309dfb41efcbf8b09ffc8a45f4cae1945cf15c Mon Sep 17 00:00:00 2001 From: wrh Date: Mon, 14 Sep 2026 15:13:20 +0800 Subject: [PATCH 3/4] =?UTF-8?q?=E4=B8=80=EF=BC=9A=E5=A2=9E=E5=8A=A0?= =?UTF-8?q?=E4=BA=86=E7=BA=B9=E6=B3=A2=E6=BB=A4=E6=B3=A2=EF=BC=8C=E5=BD=93?= =?UTF-8?q?=E7=BA=B9=E6=B3=A2=E6=9D=BF=E6=9C=89=E7=94=B5=E9=98=BB=E6=97=B6?= =?UTF-8?q?=E6=89=93=E5=BC=80=E8=BE=85=E5=8A=A9=E7=BB=A7=E7=94=B5=E5=99=A8?= =?UTF-8?q?=E5=BA=94=E8=AF=A5=E4=B8=BA3=E5=B8=A7=E8=BF=87=E5=86=B2?= =?UTF-8?q?=EF=BC=8C=E4=BD=BF=E7=94=A8=E4=BA=94=E6=AC=A1=E8=BF=87=E6=BB=A4?= =?UTF-8?q?=E5=8F=AF=E4=BB=A5=E6=B6=88=E9=99=A4=E5=BC=82=E5=B8=B8=E7=BA=B9?= =?UTF-8?q?=E6=B3=A2=20=E4=BA=8C=E3=80=81=E4=BF=AE=E6=94=B9=E4=BA=86?= =?UTF-8?q?=E8=B4=9F=E8=BD=BD=E5=90=AF=E5=8A=A8=E7=9A=84=E9=A1=BA=E5=BA=8F?= =?UTF-8?q?=EF=BC=8C=E5=85=88=E5=BC=80=E5=90=AF=E8=BE=85=E5=8A=A9=E7=BB=A7?= =?UTF-8?q?=E7=94=B5=E5=99=A8=E4=BD=BF=E5=9C=B0=E7=9B=B8=E9=80=9A=EF=BC=8C?= =?UTF-8?q?=E5=86=8D=E5=BC=80=E5=90=AFD+D-=E7=BB=A7=E7=94=B5=E5=99=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit feat: 发布V1.1.23版本，优化负载初始化继电器时序 - 更新所有头文件版本号至V1.1.21~V1.1.23，协议板固件版本更新为0x0127 - 新增纹波滤波相关宏定义与函数，实现继电器闭合后纹波过滤 - 调整负载初始化流程：先下发辅助继电器，等待回码后延迟30ms再打开北向继电器 - 优化D+/D-寄存器上位机显示单位，适配0.001V解析格式 - 补充YMODEM升级文档说明，完善传输校验与重发规则 - 清理冗余调试打印与Allegro工程日志文件 --- apps/chrg/applications/thread/chrg_comm.c | 6 +- apps/chrg/applications/thread/chrg_comm.h | 2 +- apps/chrg/applications/thread/chrg_north.c | 2 + apps/chrg/applications/thread/chrg_north.h | 10 +- apps/chrg/applications/thread/chrg_roll_sou.c | 18 +- apps/chrg/applications/thread/chrg_roll_sou.h | 2 +- apps/chrg/applications/utils/chrg_eload.c | 122 +- apps/chrg/applications/utils/chrg_eload.h | 5 +- apps/chrg/applications/utils/chrg_sink.c | 131 +- apps/chrg/applications/utils/chrg_sink.h | 2 +- docs/Allegro.jrl | 1050 +---- docs/allegro.jrl,1 | 3408 +++++------------ docs/修改日志.md | 52 + docs/协议板Boot_UPK打包规则.md | 15 + docs/协议板Boot_YMODEM上位机实现规则.md | 8 +- 15 files changed, 1343 insertions(+), 3490 deletions(-) diff --git a/apps/chrg/applications/thread/chrg_comm.c b/apps/chrg/applications/thread/chrg_comm.c index 89f0e1e..b54d2bf 100644 --- a/apps/chrg/applications/thread/chrg_comm.c +++ b/apps/chrg/applications/thread/chrg_comm.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_comm.c 完成日期 : -当前版本号 : V1.1.19 +当前版本号 : V1.1.23 主要功能 : 实现对外通讯协议 MODBUS 服务端，以独立线程等待处理响应请求数据。 版本历史 : 创建原始版本 说明 : @@ -27,7 +27,7 @@ #include "stm32f4xx_hal.h" #define HOLD_REG_FIRMWARE_VERSION 0x0300U /* 协议板固件版本，只读 */ -#define CHRG_FIRMWARE_VERSION 0x0123U /* 当前协议板版本：V1.1.19 */ +#define CHRG_FIRMWARE_VERSION 0x0127U /* 当前协议板版本：V1.1.23 */ rt_uint8_t ucDiscInBuf[(TOTAL_DISC_REGS+BITS_UCHAR-1)/BITS_UCHAR]; rt_uint8_t ucCoilBuf[(TOTAL_COIL_REGS+BITS_UCHAR-1)/BITS_UCHAR]; @@ -618,7 +618,7 @@ eMBException funcReadHoldingRegister (rt_uint8_t *reqFrame, rt_uint16_t reqLen, /* * 协议板版本号使用独立的只读地址0x0300，不占用现有通道保持寄存器空间。 - * 当前版本V1.1.19编码为0x0123，Modbus响应按高字节在前返回01 23。 + * 当前版本V1.1.23编码为0x0127，Modbus响应按高字节在前返回01 27。 * 该特殊地址只支持一次读取一个寄存器，避免与普通连续寄存器混用。 */ if (regAddress == HOLD_REG_FIRMWARE_VERSION) { diff --git a/apps/chrg/applications/thread/chrg_comm.h b/apps/chrg/applications/thread/chrg_comm.h index ae6882f..15899f6 100644 --- a/apps/chrg/applications/thread/chrg_comm.h +++ b/apps/chrg/applications/thread/chrg_comm.h @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_comm.h 完成日期 : -当前版本号 : V1.1.19 +当前版本号 : V1.1.21 主要功能 : 实现对外通讯协议 MODBUS 服务端，以独立线程等待处理响应请求数据。 版本历史 : 创建原始版本 说明 : diff --git a/apps/chrg/applications/thread/chrg_north.c b/apps/chrg/applications/thread/chrg_north.c index 8fe2401..4f6b83b 100644 --- a/apps/chrg/applications/thread/chrg_north.c +++ b/apps/chrg/applications/thread/chrg_north.c @@ -233,6 +233,8 @@ void chrg_sink_parse(rt_uint8_t *frame_data, eIDX_SOU_CH idx, pSW->VZ = ((frame_data[14] << 8) | frame_data[15]); pSW->VF = ((frame_data[16] << 8) | frame_data[17]); + //rt_kprintf("VZ=%d,VF=%d\n",pSW->VZ,pSW->VF); + #if NORTH_SINK_DEBUG LOG_D("Sink[%d] real volt: %d mV", idx, ((frame_data[4] << 8) | frame_data[5]) * 10); diff --git a/apps/chrg/applications/thread/chrg_north.h b/apps/chrg/applications/thread/chrg_north.h index 0cc23a2..4c555e7 100644 --- a/apps/chrg/applications/thread/chrg_north.h +++ b/apps/chrg/applications/thread/chrg_north.h @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_north.h 完成日期 : -当前版本号 : V1.1.19 +当前版本号 : V1.1.21 主要功能 : 实现北向通信交互，包括接收命令解析，发送请求命令，切换通路。以独立线程处理。 版本历史 : 创建原始版本 说明 : @@ -28,12 +28,16 @@ #endif /* 南向COM批次中单通道连续收到有效回码后的最大发送条数。 */ -#define SOU_COM_BURST_MAX 8U +#define SOU_COM_BURST_MAX 6U /* 自动停止带载后，电压恢复时需要连续确认的新P1采样帧数。 */ #define SINK_LOAD_RESTART_CONFIRM_COUNT 3U -#define THR_NAME_NORTH "thr.nor" +/* 主继电器闭合后的纹波瞬态过滤参数，单位为新的P1采样帧。 */ +#define RIPPLE_RELAY_IGNORE_P1_COUNT 5U +#define RIPPLE_MEDIAN_WINDOW_SIZE 3U + +#define THR_NAME_NORTH "thr.nor" #define DEV_NAME_NORTH "uart3" #define LEN_FRAME_HEAD (4) // [帧长, 0x00, id, 命令] diff --git a/apps/chrg/applications/thread/chrg_roll_sou.c b/apps/chrg/applications/thread/chrg_roll_sou.c index 65d6c89..3cf71bd 100644 --- a/apps/chrg/applications/thread/chrg_roll_sou.c +++ b/apps/chrg/applications/thread/chrg_roll_sou.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_roll_sou.c 完成日期 : -当前版本号 : V1.1.14 +当前版本号 : V1.1.22 主要功能 : 实现南向通信轮巡请求命令。以独立线程处理。 版本历史 : 创建原始版本 说明 : @@ -619,6 +619,13 @@ static int sou_com_batch_complete(rt_uint8_t ch, rt_uint16_t reg, rt_uint16_t va } pBatch->cur_idx++; + if ((reg == REG_REL_ON) && + (((value & MAIN_REL_ON) != 0U) || (value == FU_REL_ON))) { + chrg_eload_ripple_filter_relay_start(ch); + } + if ((reg == REG_WORK) && (value == WORK_STOP)) { + chrg_eload_ripple_filter_relay_stop(ch); + } /* 暂时关闭副继电器与主继电器之间的固定延时；需要恢复时重新启用本段。 */ if ((reg == REG_REL_ON) && (value == ALL_REL_OFF) && (pBatch->cur_idx < pBatch->reg_cnt) && @@ -983,6 +990,15 @@ void chrg_roll_sou_thread_entry (void *data) "batch changed", &retry_count[batch_ch]); } } else if (run != RUN_AUTO) { + if ((run == RUN_LCD) && (single_reg == REG_REL_ON) && + (((single_value & MAIN_REL_ON) != 0U) || + (single_value == FU_REL_ON))) { + chrg_eload_ripple_filter_relay_start(single_ch); + } + if ((run == RUN_LCD) && (single_reg == REG_WORK) && + (single_value == WORK_STOP)) { + chrg_eload_ripple_filter_relay_stop(single_ch); + } sou_single_command_finish(run); } else { if (version_probe) { diff --git a/apps/chrg/applications/thread/chrg_roll_sou.h b/apps/chrg/applications/thread/chrg_roll_sou.h index f1427b8..80a78c3 100644 --- a/apps/chrg/applications/thread/chrg_roll_sou.h +++ b/apps/chrg/applications/thread/chrg_roll_sou.h @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_roll_sou.h 完成日期 : -当前版本号 : V1.0 +当前版本号 : V1.1.21 主要功能 : 实现南向通信轮巡请求命令。以独立线程处理。 版本历史 : 创建原始版本 说明 : diff --git a/apps/chrg/applications/utils/chrg_eload.c b/apps/chrg/applications/utils/chrg_eload.c index 2826834..30f8a39 100644 --- a/apps/chrg/applications/utils/chrg_eload.c +++ b/apps/chrg/applications/utils/chrg_eload.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_eload.c 完成日期 : -当前版本号 : V1.0 +当前版本号 : V1.1.22 主要功能 : 源载命令数据解析，封装，读写请求。 版本历史 : 创建原始版本 说明 : @@ -20,6 +20,14 @@ #include "chrg_south.h" #define ELOAD_VALID_VOLTAGE_MIN_MV 2000U +#define DPDM_HOST_READ_SCALE 10U + +static rt_uint16_t chrg_eload_dpdm_host_value(rt_uint16_t value) +{ + rt_uint32_t scaled_value = (rt_uint32_t)value * DPDM_HOST_READ_SCALE; + + return (scaled_value > 0xFFFFU) ? 0xFFFFU : (rt_uint16_t)scaled_value; +} extern void LCD_SHOW(rt_uint8_t idx, struct eload_p1_t *pP1, struct chrg_eload_t *pLOAD, struct chrg_switch_t *pSW, rt_uint8_t online); @@ -41,9 +49,104 @@ rt_uint32_t chrg_eload_get_sample_seq(rt_uint8_t idx) } return g_eload_sample_seq[idx]; } -static rt_uint16_t ripple_base[TOTAL_SOU_CHS] = {0}; -static rt_uint8_t ripple_cal_flag[TOTAL_SOU_CHS] = {0}; -rt_uint16_t real_ripple[TOTAL_SOU_CHS] = {0}; +typedef struct { + rt_uint16_t samples[RIPPLE_MEDIAN_WINDOW_SIZE]; + rt_uint16_t filtered_value; + rt_uint8_t sample_count; + rt_uint8_t sample_next; + rt_uint8_t ignore_count; + rt_uint8_t ignore_total; + rt_tick_t relay_start_tick; + rt_uint32_t frame_count; + rt_bool_t relay_started; +} chrg_ripple_filter_t; + +static chrg_ripple_filter_t g_ripple_filter[TOTAL_SOU_CHS] = {0}; + +static rt_uint16_t chrg_eload_ripple_median(rt_uint16_t value0, + rt_uint16_t value1, rt_uint16_t value2) +{ + if (value0 > value1) { + rt_uint16_t temp = value0; + value0 = value1; + value1 = temp; + } + if (value1 > value2) { + rt_uint16_t temp = value1; + value1 = value2; + value2 = temp; + } + if (value0 > value1) { + value1 = value0; + } + return value1; +} + +static rt_uint16_t chrg_eload_ripple_filter_update(rt_uint8_t idx, + rt_uint16_t raw_value) +{ + chrg_ripple_filter_t *pFilter = &g_ripple_filter[idx]; + + pFilter->frame_count++; + + if (pFilter->ignore_count > 0U) { + pFilter->ignore_count--; + return pFilter->filtered_value; + } + pFilter->samples[pFilter->sample_next] = raw_value; + pFilter->sample_next = (pFilter->sample_next + 1U) % RIPPLE_MEDIAN_WINDOW_SIZE; + if (pFilter->sample_count < RIPPLE_MEDIAN_WINDOW_SIZE) { + pFilter->sample_count++; + } + if (pFilter->sample_count < RIPPLE_MEDIAN_WINDOW_SIZE) { + pFilter->filtered_value = raw_value; + } else { + pFilter->filtered_value = chrg_eload_ripple_median( + pFilter->samples[0], pFilter->samples[1], pFilter->samples[2]); + } + return pFilter->filtered_value; +} + +void chrg_eload_ripple_filter_reset(rt_uint8_t idx) +{ + chrg_ripple_filter_t *pFilter; + + if (idx >= TOTAL_SOU_CHS) { + return; + } + pFilter = &g_ripple_filter[idx]; + pFilter->sample_count = 0U; + pFilter->sample_next = 0U; + pFilter->ignore_count = (rt_uint8_t)RIPPLE_RELAY_IGNORE_P1_COUNT; + pFilter->ignore_total = pFilter->ignore_count; +} + +void chrg_eload_ripple_filter_relay_start(rt_uint8_t idx) +{ + chrg_ripple_filter_t *pFilter; + + if (idx >= TOTAL_SOU_CHS) { + return; + } + pFilter = &g_ripple_filter[idx]; + chrg_eload_ripple_filter_reset(idx); + pFilter->relay_start_tick = rt_tick_get(); + pFilter->frame_count = 0U; + pFilter->relay_started = RT_TRUE; +} + +void chrg_eload_ripple_filter_relay_stop(rt_uint8_t idx) +{ + chrg_ripple_filter_t *pFilter; + + if (idx >= TOTAL_SOU_CHS) { + return; + } + pFilter = &g_ripple_filter[idx]; + pFilter->relay_started = RT_FALSE; + pFilter->relay_start_tick = 0U; + pFilter->frame_count = 0U; +} /* ======================== Ymodem 升级应答缓存 ======================== */ static rt_uint8_t g_eload_ymodem_resp = 0; // 南向返回的ymodem应答字节(0=无应答) @@ -360,7 +463,8 @@ int chrg_eload_parse (rt_uint8_t idx, rt_uint8_t pt, rt_uint8_t *data, rt_uint16 pLOAD->vpkp = swap_u16(pP1->Vpkp); pLOAD->vpkn = swap_u16(pP1->Vpkn); pLOAD->vpp = swap_u16(pP1->Vpp); - pLOAD->Ripple = swap_u16(pP1->Ripple); + pLOAD->Ripple = chrg_eload_ripple_filter_update(idx, + swap_u16(pP1->Ripple)); /* 保留功率板返回的真实电流，供卸载保护判断使用。 */ pSW->Now_current = pLOAD->current; /* @@ -374,6 +478,7 @@ int chrg_eload_parse (rt_uint8_t idx, rt_uint8_t pt, rt_uint8_t *data, rt_uint16 pLOAD->vpkn = 0; pLOAD->vpp = 0; pLOAD->Ripple = 0; + chrg_eload_ripple_filter_reset(idx); pSW->VZ = 0; pSW->VF = 0; } @@ -415,8 +520,11 @@ int chrg_eload_parse (rt_uint8_t idx, rt_uint8_t pt, rt_uint8_t *data, rt_uint16 usRegHoldBuf[HOLD_REG_CH0_VPKN+idx*TOTAL_HOLD_CH_REGS] = pLOAD->vpkn; usRegHoldBuf[HOLD_REG_CH0_VPP+idx*TOTAL_HOLD_CH_REGS] = pLOAD->vpp; usRegHoldBuf[HOLD_REG_CH0_Ripple+idx*TOTAL_HOLD_CH_REGS] = pLOAD->Ripple; - usRegHoldBuf[HOLD_REG_CH0_VZ+idx*TOTAL_HOLD_CH_REGS] = pSW->VZ; - usRegHoldBuf[HOLD_REG_CH0_VF+idx*TOTAL_HOLD_CH_REGS] = pSW->VF; + /* 上位机D+/D-寄存器按0.001V解释，内部/LCD仍保持0.01V原始值。 */ + usRegHoldBuf[HOLD_REG_CH0_VZ+idx*TOTAL_HOLD_CH_REGS] = + chrg_eload_dpdm_host_value(pSW->VZ); + usRegHoldBuf[HOLD_REG_CH0_VF+idx*TOTAL_HOLD_CH_REGS] = + chrg_eload_dpdm_host_value(pSW->VF); // rt_kprintf("---------NOW VOLT END = %d\n----------",pSW->Now_voltage); return 0; } diff --git a/apps/chrg/applications/utils/chrg_eload.h b/apps/chrg/applications/utils/chrg_eload.h index 0fbd63a..ae0b23b 100644 --- a/apps/chrg/applications/utils/chrg_eload.h +++ b/apps/chrg/applications/utils/chrg_eload.h @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_eload.h 完成日期 : -当前版本号 : V1.0 +当前版本号 : V1.1.22 主要功能 : 源载命令数据解析，封装，读写请求，寄存器定义，数据结构定义。 版本历史 : 创建原始版本 说明 : @@ -299,6 +299,9 @@ extern int chrg_eload_parse_version (rt_uint8_t idx, rt_uint8_t *data, rt_uint16 其它说明： 每成功解析一帧P1数据后递增，用于区分控制命令前后的新旧量测 *****************************************************************/ extern rt_uint32_t chrg_eload_get_sample_seq(rt_uint8_t idx); +extern void chrg_eload_ripple_filter_reset(rt_uint8_t idx); +extern void chrg_eload_ripple_filter_relay_start(rt_uint8_t idx); +extern void chrg_eload_ripple_filter_relay_stop(rt_uint8_t idx); // 定义2条继电器指令，控制主继电器和滤波继电器（保留原有有效指令，移除未使用的停止指令） static const rt_uint8_t EXTRA_CMD_SOURCE[8] = {0x03, 0x06, 0x00, 0x01, 0x00, 0x01, 0x18, 0x28}; extern int chrg_eload_send_relay(rt_uint8_t cmd_type); diff --git a/apps/chrg/applications/utils/chrg_sink.c b/apps/chrg/applications/utils/chrg_sink.c index 8c52063..1e8d53d 100644 --- a/apps/chrg/applications/utils/chrg_sink.c +++ b/apps/chrg/applications/utils/chrg_sink.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_sink.c 完成日期 : -当前版本号 : V1.1.19 +当前版本号 : V1.1.21 主要功能 : 北向数据sink请求数据填充及发送。 版本历史 : 创建原始版本 说明 : @@ -24,6 +24,15 @@ #define SINK_UNLOAD_CURRENT_MAX_MA 200U // 判定负载已安全卸载的最大实际电流 #define SINK_UNLOAD_CONFIRM_COUNT 2U // 连续满足低电流条件的量测帧数 #define SINK_SHORT_KEEPALIVE_MS 30U // 短路测试WORK_START保活下发周期 +#define SINK_INIT_NORTH_RELAY_DELAY_MS 30U // 辅助继电器回码后打开北向继电器的等待时间 + +#define SINK_INIT_STAGE_CLEAR_RELAY 0U +#define SINK_INIT_STAGE_AUX_RELAY 1U +#define SINK_INIT_STAGE_DELAY 2U +#define SINK_INIT_STAGE_REST 3U + +static rt_uint8_t g_sink_init_stage[TOTAL_SOU_CHS] = {0}; +static rt_tick_t g_sink_init_north_relay_tick[TOTAL_SOU_CHS] = {0}; /* 主继电器闭合跟踪：1=已提交ALL_REL_ON（主继电器应已闭合） 0=未闭合/已断开。 * 用于0V硬保护区分"首次开载/握手恢复"（主继电器未闭合，Now_voltage=0属正常） @@ -241,31 +250,12 @@ int sink_set_pd (rt_uint8_t pd, rt_uint8_t *buf) return chrg_north_send(frame, len); } -/***************************************************************** -函数名称： chrg_sink_work_init -函数描述： 执行负载INIT入口，将副继电器和初始化命令按顺序提交南向 -输入参数： idx:南向功率通道编号 pSW:当前通道控制结构体 -输出参数： 立即打开北向Sink继电器和enable，并进入INIT_AUX_WAIT后台确认 -返回说明： 0:初始化批次提交成功 <0:参数或命令提交失败 - 其它说明： 南向顺序为FU_REL_ON、CURRENT=0、MODE、VON和可选测试停止； - 北向按“CC线->协议->电压查询”顺序执行，南北向从批次入队后并行执行 -*****************************************************************/ -static int chrg_sink_work_init(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) +static rt_uint8_t chrg_sink_init_build_commands(struct chrg_switch_t *pSW, + rt_uint16_t *regs, rt_uint16_t *vals) { - struct chrg_north_t *pNOR = &chrgnorth; - rt_uint16_t regs[6]; - rt_uint16_t vals[6]; - rt_bool_t first_start; rt_uint8_t count; - if ((idx >= TOTAL_SOU_CHS) || (pSW == RT_NULL)) { - return -1; - } - /* COM进入INIT前已经设置On_work，使用原工作状态区分首次提交和后台重试。 */ - first_start = (pSW->sink.work_mode != SINK_WORK_INIT_AUX_WAIT) ? - RT_TRUE : RT_FALSE; if (pSW->sink.test.test_mode_old == SINK_TEST_SHORT) { - /* 短路测试退出：先断开全部继电器，再打开辅助继电器，最后停止短路测试。 */ regs[0] = REG_REL_ON; vals[0] = ALL_REL_OFF; regs[1] = REG_REL_ON; vals[1] = FU_REL_ON; regs[2] = REG_CURRENT_OUT + 1; vals[2] = 0; @@ -289,18 +279,70 @@ static int chrg_sink_work_init(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) vals[count++] = ModbusRTU_DYNA_CMD_MODE_STOP; } } - if (chrg_sou_com_batch_submit(idx, regs, vals, count) != 0) { + return count; +} + +static int chrg_sink_init_submit_stage(eIDX_SOU_CH idx, + struct chrg_switch_t *pSW) +{ + rt_uint16_t regs[6]; + rt_uint16_t vals[6]; + rt_uint8_t total; + rt_uint8_t start; + rt_uint8_t count; + rt_bool_t short_exit; + + if ((idx >= TOTAL_SOU_CHS) || (pSW == RT_NULL)) { + return -1; + } + total = chrg_sink_init_build_commands(pSW, regs, vals); + short_exit = (pSW->sink.test.test_mode_old == SINK_TEST_SHORT) ? + RT_TRUE : RT_FALSE; + + switch (g_sink_init_stage[idx]) { + case SINK_INIT_STAGE_CLEAR_RELAY: + start = 0U; + count = 1U; + break; + case SINK_INIT_STAGE_AUX_RELAY: + start = short_exit ? 1U : 0U; + count = 1U; + break; + case SINK_INIT_STAGE_REST: + start = short_exit ? 2U : 1U; + count = (rt_uint8_t)(total - start); + break; + default: + return -1; + } + return chrg_sou_com_batch_submit(idx, ®s[start], &vals[start], count); +} + +/***************************************************************** +函数名称： chrg_sink_work_init +函数描述： 执行负载INIT入口，先提交辅助继电器命令 +输入参数： idx:南向功率通道编号 pSW:当前通道控制结构体 +输出参数： 进入INIT_AUX_WAIT后台等待辅助继电器回码 +返回说明： 0:初始化命令提交成功 <0:参数或命令提交失败 +其它说明： 收到01 02有效回码后等待30ms，再打开北向Sink继电器 +*****************************************************************/ +static int chrg_sink_work_init(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) +{ + rt_bool_t short_exit; + + if ((idx >= TOTAL_SOU_CHS) || (pSW == RT_NULL)) { + return -1; + } + short_exit = (pSW->sink.test.test_mode_old == SINK_TEST_SHORT) ? + RT_TRUE : RT_FALSE; + g_sink_init_stage[idx] = short_exit ? SINK_INIT_STAGE_CLEAR_RELAY : + SINK_INIT_STAGE_AUX_RELAY; + g_sink_init_north_relay_tick[idx] = 0U; + if (chrg_sink_init_submit_stage(idx, pSW) != 0) { return -1; } pSW->sink.On_work = 1; - if (first_start) { - /* 南向批次已入队，北向按“CC->协议”顺序立即开始完整握手。 */ - chrg_nor_sw_rel((eIDX_NOR_CH)idx, ID_SINK); - pNOR->enable[idx] = 1; - /* Protocol-before-CC test flow is disabled in this version. */ - pSW->sub = IDX_SET_SINK_CC_BEFORE_PD; - } pSW->sink.work_mode = SINK_WORK_INIT_AUX_WAIT; return 0; } @@ -316,6 +358,7 @@ static int chrg_sink_work_init(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) static int chrg_sink_work_init_aux_wait(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) { + struct chrg_north_t *pNOR = &chrgnorth; struct chrg_south_t *pSOU = &chrgsouth; int batch_result; @@ -325,10 +368,34 @@ static int chrg_sink_work_init_aux_wait(eIDX_SOU_CH idx, if (chrg_sou_com_batch_is_pending(idx)) { return 0; } + if (g_sink_init_stage[idx] == SINK_INIT_STAGE_DELAY) { + if ((rt_int32_t)(rt_tick_get() - + g_sink_init_north_relay_tick[idx]) < 0) { + return 0; + } + chrg_nor_sw_rel((eIDX_NOR_CH)idx, ID_SINK); + rt_kprintf("-------D+D- OPEN------\n"); + pNOR->enable[idx] = 1; + pSW->sub = IDX_SET_SINK_CC_BEFORE_PD; + g_sink_init_stage[idx] = SINK_INIT_STAGE_REST; + if (chrg_sink_init_submit_stage(idx, pSW) != 0) { + return -1; + } + return 0; + } batch_result = chrg_sou_com_batch_get_result(idx); if (batch_result <= 0) { - /* 北向保持当前事务，南向独立重试完整初始化批次。 */ - return chrg_sink_work_init(idx, pSW); + return chrg_sink_init_submit_stage(idx, pSW); + } + if (g_sink_init_stage[idx] == SINK_INIT_STAGE_CLEAR_RELAY) { + g_sink_init_stage[idx] = SINK_INIT_STAGE_AUX_RELAY; + return chrg_sink_init_submit_stage(idx, pSW); + } + if (g_sink_init_stage[idx] == SINK_INIT_STAGE_AUX_RELAY) { + g_sink_init_stage[idx] = SINK_INIT_STAGE_DELAY; + g_sink_init_north_relay_tick[idx] = rt_tick_get() + + rt_tick_from_millisecond(SINK_INIT_NORTH_RELAY_DELAY_MS); + return 0; } /* 北向可能已推进到CC或电压查询，此处只更新南向完成状态。 */ diff --git a/apps/chrg/applications/utils/chrg_sink.h b/apps/chrg/applications/utils/chrg_sink.h index 9c6c009..9b1bbb0 100644 --- a/apps/chrg/applications/utils/chrg_sink.h +++ b/apps/chrg/applications/utils/chrg_sink.h @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_sink.c 完成日期 : -当前版本号 : V1.1.19 +当前版本号 : V1.1.23 主要功能 : 北向数据sink请求数据填充及发送，命令字定义。 版本历史 : 创建原始版本 说明 : diff --git a/docs/Allegro.jrl b/docs/Allegro.jrl index f472350..b4d3f7f 100644 --- a/docs/Allegro.jrl +++ b/docs/Allegro.jrl @@ -1,953 +1,105 @@ -\t (00:00:02) allegro 17.2 S079 Windows SPB 64-bit Edition -\t (00:00:02) Journal start - Wed Aug 26 11:20:30 2026 -\t (00:00:02) Host=DESKTOP-5RA9F3K User=Adminuser Pid=37292 CPUs=20 -\t (00:00:02) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe -\t (00:00:02) - (00:00:02) Loading axlcore.cxt -\t (00:00:03) Starting new design... -\i (00:00:04) trapsize 29310 -\i (00:00:04) generaledit -\i (00:00:16) open -\i (00:00:19) fillin "HC_DFCD_Protocol_V3_0.brd" -\i (00:00:19) trapsize 1230 -\i (00:00:19) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed -\t (00:00:19) Opening existing design... -\i (00:00:20) trapsize 8018 -\d (00:00:20) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd -\i (00:00:20) generaledit -\i (00:00:21) zoom in 1 -\i (00:00:21) setwindow pcb -\i (00:00:21) zoom in 9.3881 57.0243 -\i (00:00:21) trapsize 4009 -\i (00:00:21) zoom in 1 -\i (00:00:21) setwindow pcb -\i (00:00:21) zoom in 9.3881 57.1046 -\i (00:00:21) trapsize 2005 +\t (00:00:06) allegro 17.2 S079 Windows SPB 64-bit Edition +\t (00:00:06) Journal start - Fri Sep 11 15:37:07 2026 +\t (00:00:06) Host=DESKTOP-5RA9F3K User=Adminuser Pid=13160 CPUs=20 +\t (00:00:06) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe +\t (00:00:06) + (00:00:06) Loading axlcore.cxt +\t (00:00:06) Starting new design... +\i (00:00:07) trapsize 29310 +\i (00:00:08) generaledit +\i (00:00:11) open +\i (00:00:12) fillin "HC_DFCD_Protocol_V3_0.brd" +\i (00:00:12) trapsize 1230 +\i (00:00:12) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed +\t (00:00:12) Opening existing design... +\i (00:00:12) trapsize 2757 +\d (00:00:12) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd +\i (00:00:13) generaledit +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 27.8998 58.3935 +\i (00:00:13) trapsize 5515 +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 27.7896 58.0627 +\i (00:00:13) trapsize 11030 +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 96.9925 57.6215 +\i (00:00:13) trapsize 22060 +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 299.2792 77.8006 +\i (00:00:13) trapsize 44119 +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 710.9119 236.1887 +\i (00:00:13) trapsize 88239 +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 1546.5306 547.6707 +\i (00:00:13) trapsize 176477 +\i (00:00:14) zoom in 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom in 101.1838 -64.7046 +\i (00:00:14) trapsize 88239 +\i (00:00:14) zoom in 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom in 99.4190 -62.9398 +\i (00:00:14) trapsize 44119 +\i (00:00:14) zoom in 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom in 92.3600 -31.1739 +\i (00:00:14) trapsize 22060 +\i (00:00:14) zoom in 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom in 92.3600 -30.7327 +\i (00:00:14) trapsize 11030 +\i (00:00:14) zoom in 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom in 92.3600 -30.5121 +\i (00:00:14) trapsize 5515 +\i (00:00:15) drag_start grid 110.6695 -6.4671 +\i (00:00:15) drag_stop 188.9811 -20.1441 +\i (00:00:15) zoom out 1 +\i (00:00:15) setwindow pcb +\i (00:00:15) zoom out 102.1765 2.3567 +\i (00:00:15) trapsize 11030 +\i (00:00:15) zoom out 1 +\i (00:00:15) setwindow pcb +\i (00:00:15) zoom out 102.3972 1.6950 +\i (00:00:15) trapsize 22060 +\i (00:00:15) zoom out 1 +\i (00:00:15) setwindow pcb +\i (00:00:15) zoom out 104.6031 47.3583 +\i (00:00:15) trapsize 44119 +\i (00:00:16) zoom in 1 +\i (00:00:16) setwindow pcb +\i (00:00:16) zoom in -19.8131 37.6521 +\i (00:00:16) trapsize 22060 +\i (00:00:16) zoom in 1 +\i (00:00:16) setwindow pcb +\i (00:00:16) zoom in -5.2538 42.5053 +\i (00:00:16) trapsize 11030 +\i (00:00:16) zoom in 1 +\i (00:00:16) setwindow pcb +\i (00:00:16) zoom in -5.2537 42.7259 +\i (00:00:16) trapsize 5515 +\i (00:00:17) zoom in 1 +\i (00:00:17) setwindow pcb +\i (00:00:17) zoom in 48.1306 62.4692 +\i (00:00:17) trapsize 2757 +\i (00:00:20) zoom in 1 +\i (00:00:20) setwindow pcb +\i (00:00:20) zoom in 64.2893 72.1203 +\i (00:00:20) trapsize 1379 \i (00:00:21) zoom out 1 \i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 11.3926 53.3761 -\i (00:00:21) trapsize 4009 +\i (00:00:21) zoom out 61.4492 70.2728 +\i (00:00:21) trapsize 2757 \i (00:00:21) zoom out 1 \i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 11.3926 53.3762 -\i (00:00:21) trapsize 8018 -\i (00:00:21) zoom out 1 -\i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 11.3925 53.3762 -\i (00:00:21) trapsize 16037 -\i (00:00:22) zoom in 1 -\i (00:00:22) setwindow pcb -\i (00:00:22) zoom in -23.2465 36.3774 -\i (00:00:22) trapsize 8018 -\i (00:00:22) zoom in 1 -\i (00:00:22) setwindow pcb -\i (00:00:22) zoom in 1.2895 29.4817 -\i (00:00:22) trapsize 4009 -\i (00:00:26) zoom out 1 -\i (00:00:26) setwindow pcb -\i (00:00:26) zoom out 34.8060 21.2229 -\i (00:00:26) trapsize 8018 -\i (00:00:27) zoom out 1 -\i (00:00:27) setwindow pcb -\i (00:00:27) zoom out 28.8724 21.5436 -\i (00:00:27) trapsize 16037 -\i (00:00:27) zoom out 1 -\i (00:00:27) setwindow pcb -\i (00:00:27) zoom out -0.5732 30.8448 -\i (00:00:27) trapsize 32073 -\i (00:00:27) zoom out 1 -\i (00:00:27) setwindow pcb -\i (00:00:27) zoom out 91.7976 36.6180 -\i (00:00:27) trapsize 64146 -\i (00:00:28) zoom in 1 -\i (00:00:28) setwindow pcb -\i (00:00:28) zoom in -3.7805 8.3937 -\i (00:00:28) trapsize 32073 -\i (00:00:28) zoom in 1 -\i (00:00:28) setwindow pcb -\i (00:00:28) zoom in -6.9878 8.3937 -\i (00:00:28) trapsize 16037 -\i (00:00:28) zoom in 1 -\i (00:00:28) setwindow pcb -\i (00:00:28) zoom in -4.1012 1.0169 -\i (00:00:28) trapsize 8018 -\i (00:00:29) zoom in 1 -\i (00:00:29) setwindow pcb -\i (00:00:29) zoom in -4.1012 1.0169 -\i (00:00:29) trapsize 4009 -\i (00:00:30) zoom in 1 -\i (00:00:30) setwindow pcb -\i (00:00:30) zoom in 32.5425 24.1097 -\i (00:00:30) trapsize 2005 -\i (00:00:30) zoom in 1 -\i (00:00:30) setwindow pcb -\i (00:00:30) zoom in 32.8232 23.3480 -\i (00:00:30) trapsize 1002 -\i (00:00:30) zoom in 1 -\i (00:00:30) setwindow pcb -\i (00:00:30) zoom in 33.2241 22.9672 -\i (00:00:30) trapsize 501 -\i (00:01:29) zoom out 1 -\i (00:01:29) setwindow pcb -\i (00:01:29) zoom out 31.5303 24.9216 -\i (00:01:29) trapsize 1002 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 30.3075 24.9016 -\i (00:01:30) trapsize 2005 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 29.9467 24.7012 -\i (00:01:30) trapsize 4009 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 29.7062 24.6211 -\i (00:01:30) trapsize 8018 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 28.4233 35.8467 -\i (00:01:30) trapsize 16037 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 28.1026 71.2708 -\i (00:01:30) trapsize 32073 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 98.2122 245.1074 -\i (00:01:30) trapsize 64146 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 296.4245 590.2147 -\i (00:01:30) trapsize 128293 -\i (00:01:31) zoom in 1 -\i (00:01:31) setwindow pcb -\i (00:01:31) zoom in -97.4341 64.2147 -\i (00:01:31) trapsize 64146 -\i (00:01:31) zoom in 1 -\i (00:01:31) setwindow pcb -\i (00:01:31) zoom in -97.4341 64.2147 -\i (00:01:31) trapsize 32073 -\i (00:01:31) zoom in 1 -\i (00:01:31) setwindow pcb -\i (00:01:31) zoom in -97.4340 64.8562 -\i (00:01:31) trapsize 16037 -\i (00:01:31) zoom in 1 -\i (00:01:31) setwindow pcb -\i (00:01:31) zoom in -78.5108 74.7989 -\i (00:01:31) trapsize 8018 -\i (00:01:32) zoom in 1 -\i (00:01:32) setwindow pcb -\i (00:01:32) zoom in 38.0752 90.8355 -\i (00:01:32) trapsize 4009 -\i (00:01:32) zoom in 1 -\i (00:01:32) setwindow pcb -\i (00:01:32) zoom in 36.0707 90.8356 -\i (00:01:32) trapsize 2005 -\i (00:01:32) zoom in 1 -\i (00:01:32) setwindow pcb -\i (00:01:32) zoom in 30.8187 90.1942 -\i (00:01:32) trapsize 1002 -\i (00:01:33) zoom in 1 -\i (00:01:33) setwindow pcb -\i (00:01:33) zoom in 21.8583 91.4170 -\i (00:01:33) trapsize 501 -\i (00:01:33) zoom out 1 -\i (00:01:33) setwindow pcb -\i (00:01:33) zoom out 21.9585 91.5072 -\i (00:01:33) trapsize 1002 -\i (00:01:34) zoom in 1 -\i (00:01:34) setwindow pcb -\i (00:01:34) zoom in 18.3102 91.2667 -\i (00:01:34) trapsize 501 -\i (00:01:35) zoom out 1 -\i (00:01:35) setwindow pcb -\i (00:01:35) zoom out 18.3403 91.3670 -\i (00:01:35) trapsize 1002 -\i (00:01:35) zoom out 1 -\i (00:01:35) setwindow pcb -\i (00:01:35) zoom out 18.3604 91.2667 -\i (00:01:35) trapsize 2005 -\i (00:01:35) zoom out 1 -\i (00:01:35) setwindow pcb -\i (00:01:35) zoom out 18.2803 90.5050 -\i (00:01:35) trapsize 4009 -\i (00:01:35) zoom out 1 -\i (00:01:35) setwindow pcb -\i (00:01:35) zoom out 18.2803 90.1842 -\i (00:01:35) trapsize 8018 -\i (00:01:36) zoom out 1 -\i (00:01:36) setwindow pcb -\i (00:01:36) zoom out 19.2424 88.9014 -\i (00:01:36) trapsize 16037 -\i (00:01:36) zoom out 1 -\i (00:01:36) setwindow pcb -\i (00:01:36) zoom out 19.2424 88.5806 -\i (00:01:36) trapsize 32073 -\i (00:01:36) zoom out 1 -\i (00:01:36) setwindow pcb -\i (00:01:36) zoom out 19.2425 60.9977 -\i (00:01:36) trapsize 64146 -\i (00:01:37) zoom out 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom out 17.9595 115.5317 -\i (00:01:37) trapsize 128293 -\i (00:01:37) zoom out 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom out 17.9595 323.3659 -\i (00:01:37) trapsize 256585 -\i (00:01:37) zoom in 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom in -79.5429 23.1610 -\i (00:01:37) trapsize 128293 -\i (00:01:37) zoom in 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom in -79.5429 23.1610 -\i (00:01:37) trapsize 64146 -\i (00:01:37) zoom in 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom in -79.5429 23.1610 -\i (00:01:37) trapsize 32073 -\i (00:01:37) zoom in 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom in -76.9770 37.2732 -\i (00:01:37) trapsize 16037 -\i (00:01:37) zoom in 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom in -75.0526 41.7635 -\i (00:01:37) trapsize 8018 -\i (00:01:38) zoom in 1 -\i (00:01:38) setwindow pcb -\i (00:01:38) zoom in -3.0483 90.8355 -\i (00:01:38) trapsize 4009 -\i (00:01:38) zoom in 1 -\i (00:01:38) setwindow pcb -\i (00:01:38) zoom in -0.7229 92.4392 -\i (00:01:38) trapsize 2005 -\i (00:01:39) zoom in 1 -\i (00:01:39) setwindow pcb -\i (00:01:39) zoom in 22.9712 93.2811 -\i (00:01:39) trapsize 1002 -\i (00:01:39) zoom in 1 -\i (00:01:39) setwindow pcb -\i (00:01:39) zoom in 22.9712 93.2811 -\i (00:01:39) trapsize 501 -\i (00:01:54) zoom out 1 -\i (00:01:54) setwindow pcb -\i (00:01:54) zoom out 19.1125 92.5294 -\i (00:01:54) trapsize 1002 -\i (00:07:02) zoom in 1 -\i (00:07:02) setwindow pcb -\i (00:07:02) zoom in 18.4710 93.8724 -\i (00:07:02) trapsize 501 -\i (00:07:04) zoom out 1 -\i (00:07:04) setwindow pcb -\i (00:07:04) zoom out 19.5334 91.9480 -\i (00:07:04) trapsize 1002 -\i (00:07:09) zoom in 1 -\i (00:07:09) setwindow pcb -\i (00:07:09) zoom in 18.4911 91.9882 -\i (00:07:09) trapsize 501 -\i (00:07:10) zoom out 1 -\i (00:07:10) setwindow pcb -\i (00:07:10) zoom out 19.2128 91.7075 -\i (00:07:10) trapsize 1002 -\i (00:07:25) zoom out 1 -\i (00:07:25) setwindow pcb -\i (00:07:25) zoom out 18.4110 90.8857 -\i (00:07:25) trapsize 2005 -\i (00:07:25) zoom in 1 -\i (00:07:25) setwindow pcb -\i (00:07:25) zoom in 19.7340 89.8032 -\i (00:07:25) trapsize 1002 -\i (00:07:25) zoom in 1 -\i (00:07:25) setwindow pcb -\i (00:07:25) zoom in 20.3755 89.3422 -\i (00:07:25) trapsize 501 -\i (00:07:29) drag_start grid 20.6361 90.3947 -\i (00:07:29) drag_stop 20.6361 90.5751 -\i (00:07:51) zoom out 1 -\i (00:07:51) setwindow pcb -\i (00:07:51) zoom out 21.4980 90.2343 -\i (00:07:51) trapsize 1002 -\i (00:07:57) zoom out 1 -\i (00:07:57) setwindow pcb -\i (00:07:57) zoom out 26.5496 91.6375 -\i (00:07:57) trapsize 2005 -\i (00:07:57) zoom out 1 -\i (00:07:57) setwindow pcb -\i (00:07:57) zoom out 26.5497 91.6375 -\i (00:07:57) trapsize 4009 -\i (00:07:57) zoom out 1 -\i (00:07:57) setwindow pcb -\i (00:07:57) zoom out 29.5966 88.4301 -\i (00:07:57) trapsize 8018 -\i (00:07:57) zoom out 1 -\i (00:07:57) setwindow pcb -\i (00:07:57) zoom out 94.8445 88.4302 -\i (00:07:57) trapsize 16037 -\i (00:07:58) zoom in 1 -\i (00:07:58) setwindow pcb -\i (00:07:58) zoom in 28.6134 86.8265 -\i (00:07:58) trapsize 8018 -\i (00:07:58) zoom in 1 -\i (00:07:58) setwindow pcb -\i (00:07:58) zoom in 39.8390 91.4771 -\i (00:07:58) trapsize 4009 -\i (00:07:58) zoom in 1 -\i (00:07:58) setwindow pcb -\i (00:07:58) zoom in 39.8391 91.3969 -\i (00:07:58) trapsize 2005 -\i (00:07:59) zoom in 1 -\i (00:07:59) setwindow pcb -\i (00:07:59) zoom in 38.3557 90.8757 -\i (00:07:59) trapsize 1002 -\i (00:07:59) zoom in 1 -\i (00:07:59) setwindow pcb -\i (00:07:59) zoom in 36.6719 90.9960 -\i (00:07:59) trapsize 501 -\i (00:08:03) zoom out 1 -\i (00:08:03) setwindow pcb -\i (00:08:03) zoom out 41.0920 90.8257 -\i (00:08:03) trapsize 1002 -\i (00:08:13) zoom out 1 -\i (00:08:13) setwindow pcb -\i (00:08:13) zoom out 47.9476 90.6251 -\i (00:08:13) trapsize 2005 -\i (00:08:14) zoom in 1 -\i (00:08:14) setwindow pcb -\i (00:08:14) zoom in 33.2742 88.2999 -\i (00:08:14) trapsize 1002 -\i (00:08:16) zoom out 1 -\i (00:08:16) setwindow pcb -\i (00:08:16) zoom out 20.1643 90.6653 -\i (00:08:16) trapsize 2005 -\i (00:08:16) zoom out 1 -\i (00:08:16) setwindow pcb -\i (00:08:16) zoom out 20.1241 90.6653 -\i (00:08:16) trapsize 4009 -\i (00:08:17) zoom in 1 -\i (00:08:17) setwindow pcb -\i (00:08:17) zoom in 15.1528 89.7031 -\i (00:08:17) trapsize 2005 -\i (00:08:17) zoom in 1 -\i (00:08:17) setwindow pcb -\i (00:08:17) zoom in 15.1529 89.7031 -\i (00:08:17) trapsize 1002 -\i (00:23:54) zoom out 1 -\i (00:23:54) setwindow pcb -\i (00:23:54) zoom out 36.2810 91.7077 -\i (00:23:54) trapsize 2005 -\i (00:23:55) zoom in 1 -\i (00:23:55) setwindow pcb -\i (00:23:55) zoom in 38.2858 92.3893 -\i (00:23:55) trapsize 1002 -\i (00:23:55) zoom in 1 -\i (00:23:55) setwindow pcb -\i (00:23:55) zoom in 38.2857 92.3893 -\i (00:23:55) trapsize 501 -\i (00:23:55) zoom out 1 -\i (00:23:55) setwindow pcb -\i (00:23:55) zoom out 38.8972 92.3492 -\i (00:23:55) trapsize 1002 -\i (00:23:55) zoom out 1 -\i (00:23:55) setwindow pcb -\i (00:23:55) zoom out 38.8971 92.3492 -\i (00:23:55) trapsize 2005 -\i (00:23:58) zoom out 1 -\i (00:23:58) setwindow pcb -\i (00:23:58) zoom out 39.6189 90.6253 -\i (00:23:58) trapsize 4009 -\i (00:23:58) zoom in 1 -\i (00:23:58) setwindow pcb -\i (00:23:58) zoom in 39.2180 90.0640 -\i (00:23:58) trapsize 2005 -\i (00:23:58) zoom in 1 -\i (00:23:58) setwindow pcb -\i (00:23:58) zoom in 39.2180 90.0641 -\i (00:23:58) trapsize 1002 -\i (00:23:59) zoom in 1 -\i (00:23:59) setwindow pcb -\i (00:23:59) zoom in 39.2180 90.0641 -\i (00:23:59) trapsize 501 -\i (00:24:00) zoom out 1 -\i (00:24:00) setwindow pcb -\i (00:24:00) zoom out 32.0116 89.7134 -\i (00:24:00) trapsize 1002 -\i (00:24:02) zoom out 1 -\i (00:24:02) setwindow pcb -\i (00:24:02) zoom out 23.3319 88.5707 -\i (00:24:02) trapsize 2005 -\i (00:24:02) zoom out 1 -\i (00:24:02) setwindow pcb -\i (00:24:02) zoom out 22.4498 88.2099 -\i (00:24:02) trapsize 4009 -\i (00:24:02) zoom out 1 -\i (00:24:02) setwindow pcb -\i (00:24:02) zoom out 22.3697 88.2100 -\i (00:24:02) trapsize 8018 -\i (00:24:02) zoom out 1 -\i (00:24:02) setwindow pcb -\i (00:24:02) zoom out 22.3697 88.2099 -\i (00:24:02) trapsize 16037 -\i (00:24:03) zoom in 1 -\i (00:24:03) setwindow pcb -\i (00:24:03) zoom in 23.0111 88.5306 -\i (00:24:03) trapsize 8018 -\i (00:24:03) zoom in 1 -\i (00:24:03) setwindow pcb -\i (00:24:03) zoom in 23.0111 88.5307 -\i (00:24:03) trapsize 4009 -\i (00:24:04) zoom out 1 -\i (00:24:04) setwindow pcb -\i (00:24:04) zoom out 20.8462 88.2902 -\i (00:24:04) trapsize 8018 -\i (00:24:04) zoom out 1 -\i (00:24:04) setwindow pcb -\i (00:24:04) zoom out 20.8462 88.2902 -\i (00:24:04) trapsize 16037 -\i (00:24:04) zoom out 1 -\i (00:24:04) setwindow pcb -\i (00:24:04) zoom out 17.9597 86.0450 -\i (00:24:04) trapsize 32073 -\i (00:24:04) zoom out 1 -\i (00:24:04) setwindow pcb -\i (00:24:04) zoom out 16.6768 83.4792 -\i (00:24:04) trapsize 64146 -\i (00:24:05) zoom in 1 -\i (00:24:05) setwindow pcb -\i (00:24:05) zoom in -2.5671 69.3464 -\i (00:24:05) trapsize 32073 -\i (00:24:05) zoom in 1 -\i (00:24:05) setwindow pcb -\i (00:24:05) zoom in -2.5671 69.3464 -\i (00:24:05) trapsize 16037 -\i (00:24:06) zoom in 1 -\i (00:24:06) setwindow pcb -\i (00:24:06) zoom in -0.0012 80.8927 -\i (00:24:06) trapsize 8018 -\i (00:24:06) zoom in 1 -\i (00:24:06) setwindow pcb -\i (00:24:06) zoom in -0.0011 80.8928 -\i (00:24:06) trapsize 4009 -\i (00:24:06) zoom in 1 -\i (00:24:06) setwindow pcb -\i (00:24:06) zoom in 8.4181 88.3498 -\i (00:24:06) trapsize 2005 -\i (00:24:06) zoom in 1 -\i (00:24:06) setwindow pcb -\i (00:24:06) zoom in 8.4181 88.3499 -\i (00:24:06) trapsize 1002 -\i (00:26:42) zoom out 1 -\i (00:26:42) setwindow pcb -\i (00:26:42) zoom out 12.4874 88.6506 -\i (00:26:42) trapsize 2005 -\i (00:26:43) zoom out 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom out 12.2870 87.2074 -\i (00:26:43) trapsize 4009 -\i (00:26:43) zoom out 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom out 12.2069 84.7216 -\i (00:26:43) trapsize 8018 -\i (00:26:43) zoom out 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom out 12.5276 82.4765 -\i (00:26:43) trapsize 16037 -\i (00:26:43) zoom in 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom in -19.5456 56.1766 -\i (00:26:43) trapsize 8018 -\i (00:26:43) zoom in 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom in -19.7060 56.1766 -\i (00:26:43) trapsize 4009 -\i (00:26:43) zoom in 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom in -19.7059 56.1767 -\i (00:26:43) trapsize 2005 -\i (00:26:44) zoom out 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom out 2.9458 64.2752 -\i (00:26:44) trapsize 4009 -\i (00:26:44) zoom in 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom in 2.7854 63.8743 -\i (00:26:44) trapsize 2005 -\i (00:26:44) zoom out 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom out 2.7854 63.8744 -\i (00:26:44) trapsize 4009 -\i (00:26:44) zoom out 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom out 2.7854 63.8743 -\i (00:26:44) trapsize 8018 -\i (00:26:44) zoom in 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom in 39.0372 93.7024 -\i (00:26:44) trapsize 4009 -\i (00:26:44) zoom in 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom in 34.3866 95.6268 -\i (00:26:44) trapsize 2005 -\i (00:26:44) zoom in 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom in 28.3328 95.3863 -\i (00:26:44) trapsize 1002 -\i (00:26:48) zoom in 1 -\i (00:26:48) setwindow pcb -\i (00:26:48) zoom in 31.0991 90.2947 -\i (00:26:48) trapsize 501 -\i (00:26:52) zoom out 1 -\i (00:26:52) setwindow pcb -\i (00:26:52) zoom out 24.5141 90.1143 -\i (00:26:52) trapsize 1002 -\i (00:26:53) zoom in 1 -\i (00:26:53) setwindow pcb -\i (00:26:53) zoom in 24.1733 91.3772 -\i (00:26:53) trapsize 501 -\i (00:26:54) zoom out 1 -\i (00:26:54) setwindow pcb -\i (00:26:54) zoom out 25.6667 91.2369 -\i (00:26:54) trapsize 1002 -\i (00:26:54) zoom out 1 -\i (00:26:54) setwindow pcb -\i (00:26:54) zoom out 25.6667 91.0967 -\i (00:26:54) trapsize 2005 -\i (00:26:55) zoom out 1 -\i (00:26:55) setwindow pcb -\i (00:26:55) zoom out 17.8489 90.8962 -\i (00:26:55) trapsize 4009 -\i (00:26:55) zoom in 1 -\i (00:26:55) setwindow pcb -\i (00:26:55) zoom in 15.8442 91.6981 -\i (00:26:55) trapsize 2005 -\i (00:26:56) zoom in 1 -\i (00:26:56) setwindow pcb -\i (00:26:56) zoom in 15.8443 91.6981 -\i (00:26:56) trapsize 1002 -\i (00:28:55) zoom out 1 -\i (00:28:55) setwindow pcb -\i (00:28:55) zoom out 24.3237 90.7159 -\i (00:28:55) trapsize 2005 -\i (00:28:55) zoom in 1 -\i (00:28:55) setwindow pcb -\i (00:28:55) zoom in 14.4612 92.3997 -\i (00:28:55) trapsize 1002 -\i (03:15:24) xrefdes K1 -\i (03:15:24) xname_flush -\i (03:15:24) trapsize 4733 -\i (03:15:26) xrefdes K3 -\i (03:15:26) xname_flush -\i (03:15:26) trapsize 4733 -\i (03:15:28) xrefdes K1 -\i (03:15:28) xname_flush -\i (03:15:28) trapsize 4733 -\i (03:15:56) xrefdes U21 -\i (03:15:56) xname_flush -\i (03:15:56) trapsize 1890 -\i (03:16:30) xNet Vbus+ -\i (03:16:30) xname_flush -\i (03:16:30) trapsize 7236 -\i (03:16:34) xNet Vbus+_Sw -\i (03:16:34) xname_flush -\i (03:16:34) trapsize 2674 -\i (03:16:38) xrefdes U5 -\i (03:16:38) xname_flush -\i (03:16:38) trapsize 2201 -\i (04:19:50) zoom out 1 -\i (04:19:50) setwindow pcb -\i (04:19:50) zoom out 28.4704 33.3770 -\i (04:19:50) trapsize 4401 -\i (04:19:50) zoom out 1 -\i (04:19:50) setwindow pcb -\i (04:19:50) zoom out 28.4704 33.3770 -\i (04:19:50) trapsize 8803 -\i (04:20:05) zoom in 1 -\i (04:20:05) setwindow pcb -\i (04:20:05) zoom in 67.9549 43.7641 -\i (04:20:05) trapsize 4401 -\i (04:20:07) zoom in 1 -\i (04:20:07) setwindow pcb -\i (04:20:07) zoom in 45.7722 39.8910 -\i (04:20:07) trapsize 2201 -\i (04:20:17) zoom out 1 -\i (04:20:17) setwindow pcb -\i (04:20:17) zoom out 51.8021 36.7661 -\i (04:20:17) trapsize 4401 -\i (04:20:18) zoom out 1 -\i (04:20:18) setwindow pcb -\i (04:20:18) zoom out 37.8939 32.3647 -\i (04:20:18) trapsize 8803 -\i (04:20:19) zoom out 1 -\i (04:20:19) setwindow pcb -\i (04:20:19) zoom out 13.0703 40.4631 -\i (04:20:19) trapsize 17605 -\i (04:20:20) zoom in 1 -\i (04:20:20) setwindow pcb -\i (04:20:20) zoom in 16.1952 5.2524 -\i (04:20:20) trapsize 8803 -\i (04:20:20) zoom in 1 -\i (04:20:20) setwindow pcb -\i (04:20:20) zoom in 15.4910 4.9004 -\i (04:20:20) trapsize 4401 -\i (04:20:22) zoom in 1 -\i (04:20:22) setwindow pcb -\i (04:20:22) zoom in 33.5365 21.7135 -\i (04:20:22) trapsize 2201 -\i (04:20:22) zoom in 1 -\i (04:20:22) setwindow pcb -\i (04:20:22) zoom in 34.5488 22.3737 -\i (04:20:22) trapsize 1100 -\i (04:20:22) zoom in 1 -\i (04:20:22) setwindow pcb -\i (04:20:22) zoom in 34.5488 22.3737 -\i (04:20:22) trapsize 550 -\i (04:20:23) zoom in 1 -\i (04:20:23) setwindow pcb -\i (04:20:23) zoom in 33.8446 23.6061 -\i (04:20:23) trapsize 275 -\i (04:20:23) zoom in 1 -\i (04:20:23) setwindow pcb -\i (04:20:23) zoom in 33.1183 23.8152 -\i (04:20:23) trapsize 138 -\i (04:20:23) zoom out 1 -\i (04:20:23) setwindow pcb -\i (04:20:23) zoom out 33.3383 23.8345 -\i (04:20:23) trapsize 275 -\i (04:20:23) zoom out 1 -\i (04:20:23) setwindow pcb -\i (04:20:23) zoom out 33.3438 23.7850 -\i (04:20:23) trapsize 550 -\i (04:20:33) zoom out 1 -\i (04:20:33) setwindow pcb -\i (04:20:33) zoom out 34.9944 23.6969 -\i (04:20:33) trapsize 1100 -\i (04:20:33) zoom out 1 -\i (04:20:33) setwindow pcb -\i (04:20:33) zoom out 35.2585 23.6970 -\i (04:20:33) trapsize 2201 -\i (04:20:34) zoom out 1 -\i (04:20:34) setwindow pcb -\i (04:20:34) zoom out 35.0825 22.9047 -\i (04:20:34) trapsize 4402 -\i (04:20:34) zoom out 1 -\i (04:20:34) setwindow pcb -\i (04:20:34) zoom out 35.0824 22.9047 -\i (04:20:34) trapsize 8803 -\i (04:20:35) zoom in 1 -\i (04:20:35) setwindow pcb -\i (04:20:35) zoom in 33.6739 48.2577 -\i (04:20:35) trapsize 4402 -\i (04:20:35) zoom in 1 -\i (04:20:35) setwindow pcb -\i (04:20:35) zoom in 36.9311 22.7287 -\i (04:20:35) trapsize 2201 -\i (04:20:35) zoom in 1 -\i (04:20:35) setwindow pcb -\i (04:20:35) zoom in 36.1389 22.1125 -\i (04:20:35) trapsize 1100 -\i (04:20:36) zoom in 1 -\i (04:20:36) setwindow pcb -\i (04:20:36) zoom in 31.9134 24.1592 -\i (04:20:36) trapsize 550 -\i (04:20:36) zoom in 1 -\i (04:20:36) setwindow pcb -\i (04:20:36) zoom in 31.9134 24.1592 -\i (04:20:36) trapsize 275 -\i (04:20:37) zoom out 1 -\i (04:20:37) setwindow pcb -\i (04:20:37) zoom out 34.8459 23.5815 -\i (04:20:37) trapsize 550 -\i (04:20:38) zoom in 1 -\i (04:20:38) setwindow pcb -\i (04:20:38) zoom in 36.3204 23.2514 -\i (04:20:38) trapsize 275 -\i (04:20:40) zoom out 1 -\i (04:20:40) setwindow pcb -\i (04:20:40) zoom out 35.9188 23.9722 -\i (04:20:40) trapsize 550 -\i (04:20:41) zoom out 1 -\i (04:20:41) setwindow pcb -\i (04:20:41) zoom out 37.6905 23.9502 -\i (04:20:41) trapsize 1100 -\i (04:20:41) zoom in 1 -\i (04:20:41) setwindow pcb -\i (04:20:41) zoom in 39.2309 23.4440 -\i (04:20:41) trapsize 550 -\i (04:20:42) zoom in 1 -\i (04:20:42) setwindow pcb -\i (04:20:42) zoom in 38.5377 23.6861 -\i (04:20:42) trapsize 275 -\i (04:20:42) zoom in 1 -\i (04:20:42) setwindow pcb -\i (04:20:42) zoom in 38.5377 23.6861 -\i (04:20:42) trapsize 138 -\i (04:20:43) zoom out 1 -\i (04:20:43) setwindow pcb -\i (04:20:43) zoom out 38.2736 23.7027 -\i (04:20:43) trapsize 275 -\i (04:20:45) zoom out 1 -\i (04:20:45) setwindow pcb -\i (04:20:45) zoom out 35.2366 23.8787 -\i (04:20:45) trapsize 550 -\i (04:20:46) zoom out 1 -\i (04:20:46) setwindow pcb -\i (04:20:46) zoom out 36.1169 24.6599 -\i (04:20:46) trapsize 1100 -\i (04:20:46) zoom out 1 -\i (04:20:46) setwindow pcb -\i (04:20:46) zoom out 36.1169 24.5499 -\i (04:20:46) trapsize 2201 -\i (04:20:46) zoom out 1 -\i (04:20:46) setwindow pcb -\i (04:20:46) zoom out 36.6011 24.6819 -\i (04:20:46) trapsize 4402 -\i (04:20:47) zoom out 1 -\i (04:20:47) setwindow pcb -\i (04:20:47) zoom out 35.1925 31.9005 -\i (04:20:47) trapsize 8803 -\i (04:20:47) zoom in 1 -\i (04:20:47) setwindow pcb -\i (04:20:47) zoom in 32.9036 29.6117 -\i (04:20:47) trapsize 4402 -\i (04:20:47) zoom out 1 -\i (04:20:47) setwindow pcb -\i (04:20:47) zoom out 32.7276 30.4920 -\i (04:20:47) trapsize 8803 -\i (04:20:47) zoom out 1 -\i (04:20:47) setwindow pcb -\i (04:20:47) zoom out 32.5515 30.4920 -\i (04:20:47) trapsize 17606 -\i (04:20:48) zoom in 1 -\i (04:20:48) setwindow pcb -\i (04:20:48) zoom in 18.3135 52.8216 -\i (04:20:48) trapsize 8803 -\i (04:20:48) zoom in 1 -\i (04:20:48) setwindow pcb -\i (04:20:48) zoom in 18.3135 52.8216 -\i (04:20:48) trapsize 4402 -\i (04:20:49) zoom in 1 -\i (04:20:49) setwindow pcb -\i (04:20:49) zoom in 34.3352 20.6903 -\i (04:20:49) trapsize 2201 -\i (04:20:50) zoom in 1 -\i (04:20:50) setwindow pcb -\i (04:20:50) zoom in 32.7506 19.7220 -\i (04:20:50) trapsize 1100 -\i (04:20:50) zoom in 1 -\i (04:20:50) setwindow pcb -\i (04:20:50) zoom in 33.0587 21.2626 -\i (04:20:50) trapsize 550 -\i (04:20:50) zoom in 1 -\i (04:20:50) setwindow pcb -\i (04:20:50) zoom in 33.0587 21.2626 -\i (04:20:50) trapsize 275 -\i (04:20:51) zoom out 1 -\i (04:20:51) setwindow pcb -\i (04:20:51) zoom out 33.0587 23.3203 -\i (04:20:51) trapsize 550 -\i (04:20:55) zoom in 1 -\i (04:20:55) setwindow pcb -\i (04:20:55) zoom in 34.3352 23.7385 -\i (04:20:55) trapsize 275 -\i (04:20:56) drag_start grid 34.3023 23.7275 -\i (04:20:56) zoom in 1 -\i (04:20:56) setwindow pcb -\i (04:20:56) zoom in 34.3408 23.0673 -\i (04:20:56) trapsize 138 -\i (04:20:56) drag_stop 34.3573 22.9353 -\i (04:20:57) zoom out 1 -\i (04:20:57) setwindow pcb -\i (04:20:57) zoom out 34.3436 22.9793 -\i (04:20:57) trapsize 275 -\i (04:20:57) zoom out 1 -\i (04:20:57) setwindow pcb -\i (04:20:57) zoom out 34.3436 22.9793 -\i (04:20:57) trapsize 550 -\i (04:20:57) zoom out 1 -\i (04:20:57) setwindow pcb -\i (04:20:57) zoom out 34.3545 22.9353 -\i (04:20:57) trapsize 1100 -\i (04:20:57) zoom in 1 -\i (04:20:57) setwindow pcb -\i (04:20:57) zoom in 33.4742 26.5226 -\i (04:20:57) trapsize 550 -\i (04:20:58) zoom in 1 -\i (04:20:58) setwindow pcb -\i (04:20:58) zoom in 34.8717 23.7717 -\i (04:20:58) trapsize 275 -\i (04:21:36) help -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 36.1042 24.5970 -\i (04:22:22) trapsize 550 -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 36.1041 24.5090 -\i (04:22:22) trapsize 1100 -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 36.1701 24.3990 -\i (04:22:22) trapsize 2201 -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 37.1825 23.6948 -\i (04:22:22) trapsize 4402 -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 46.2497 31.2655 -\i (04:22:22) trapsize 8803 -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 85.7451 31.2656 -\i (04:22:22) trapsize 17606 -\i (04:22:23) zoom in 1 -\i (04:22:23) setwindow pcb -\i (04:22:23) zoom in 13.7359 82.0478 -\i (04:22:23) trapsize 8803 -\i (04:22:26) zoom in 1 -\i (04:22:26) setwindow pcb -\i (04:22:26) zoom in 33.2788 57.5752 -\i (04:22:26) trapsize 4402 -\i (04:22:26) zoom in 1 -\i (04:22:26) setwindow pcb -\i (04:22:26) zoom in 33.2788 57.5753 -\i (04:22:26) trapsize 2201 -\i (04:22:27) zoom out 1 -\i (04:22:27) setwindow pcb -\i (04:22:27) zoom out 36.7560 59.1599 -\i (04:22:27) trapsize 4402 -\i (04:22:27) zoom out 1 -\i (04:22:27) setwindow pcb -\i (04:22:27) zoom out 36.7559 59.1599 -\i (04:22:27) trapsize 8803 -\i (04:22:27) zoom in 1 -\i (04:22:27) setwindow pcb -\i (04:22:27) zoom in 2.7760 75.0054 -\i (04:22:27) trapsize 4402 -\i (04:22:32) zoom out 1 -\i (04:22:32) setwindow pcb -\i (04:22:32) zoom out 69.6795 77.9985 -\i (04:22:32) trapsize 8803 -\i (04:22:34) zoom in 1 -\i (04:22:34) setwindow pcb -\i (04:22:34) zoom in 73.5968 80.6394 -\i (04:22:34) trapsize 4402 -\i (04:22:34) zoom in 1 -\i (04:22:34) setwindow pcb -\i (04:22:34) zoom in 73.5968 80.6395 -\i (04:22:34) trapsize 2201 -\i (04:22:34) zoom in 1 -\i (04:22:34) setwindow pcb -\i (04:22:34) zoom in 71.6601 81.1677 -\i (04:22:34) trapsize 1100 -\i (04:22:35) zoom in 1 -\i (04:22:35) setwindow pcb -\i (04:22:35) zoom in 72.6285 80.9257 -\i (04:22:35) trapsize 550 -\i (04:22:35) zoom in 1 -\i (04:22:35) setwindow pcb -\i (04:22:35) zoom in 72.6285 80.9257 -\i (04:22:35) trapsize 275 -\i (04:23:52) zoom out 1 -\i (04:23:52) setwindow pcb -\i (04:23:52) zoom out 70.3892 79.9464 -\i (04:23:52) trapsize 550 -\i (04:23:55) zoom in 1 -\i (04:23:55) setwindow pcb -\i (04:23:55) zoom in 66.5489 80.1885 -\i (04:23:55) trapsize 275 -\i (04:23:55) zoom in 1 -\i (04:23:55) setwindow pcb -\i (04:23:55) zoom in 66.0538 80.2106 -\i (04:23:55) trapsize 138 -\i (04:23:55) zoom in 1 -\i (04:23:55) setwindow pcb -\i (04:23:55) zoom in 66.0538 80.2106 -\i (04:23:55) trapsize 69 -\i (04:23:55) zoom out 1 -\i (04:23:55) setwindow pcb -\i (04:23:55) zoom out 66.1597 80.2492 -\i (04:23:55) trapsize 138 -\i (04:23:55) zoom out 1 -\i (04:23:55) setwindow pcb -\i (04:23:55) zoom out 66.1597 80.2492 -\i (04:23:55) trapsize 275 -\i (04:23:56) zoom out 1 -\i (04:23:56) setwindow pcb -\i (04:23:56) zoom out 66.5283 80.3812 -\i (04:23:56) trapsize 550 -\i (04:23:58) zoom in 1 -\i (04:23:58) setwindow pcb -\i (04:23:58) zoom in 71.8655 80.6564 -\i (04:23:58) trapsize 275 -\i (04:23:59) zoom out 1 -\i (04:23:59) setwindow pcb -\i (04:23:59) zoom out 71.7500 80.5023 -\i (04:23:59) trapsize 550 -\i (04:28:30) zoom out 1 -\i (04:28:30) setwindow pcb -\i (04:28:30) zoom out 73.0154 79.4459 -\i (04:28:30) trapsize 1100 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 72.3551 79.1158 -\i (04:28:31) trapsize 2201 -\i (04:28:31) zoom in 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom in 70.6824 76.9588 -\i (04:28:31) trapsize 1100 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 70.0882 77.3990 -\i (04:28:31) trapsize 2201 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 69.7801 77.3990 -\i (04:28:31) trapsize 4402 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 55.2541 77.8392 -\i (04:28:31) trapsize 8804 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 54.1977 69.5637 -\i (04:28:31) trapsize 17607 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 108.1170 57.9431 -\i (04:28:31) trapsize 35214 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 319.7555 52.1262 -\i (04:28:31) trapsize 70429 -\i (04:28:46) xdehilite -\i (04:28:46) xrefdes U5 -\i (04:28:46) xname_flush -\i (04:28:46) done -\i (04:28:46) generaledit -\i (04:29:34) xNet Pb10_Usart3_Tx -\i (04:29:34) xname_flush -\i (04:29:34) trapsize 710 -\i (04:39:25) xNet Pb9 -\i (04:39:25) xname_flush -\i (04:39:25) trapsize 580 -\i (04:42:22) xNet Pb10_Usart3_Tx -\i (04:42:22) xname_flush -\i (04:42:22) trapsize 710 -\i (04:42:36) xNet N3579505 -\i (04:42:36) xname_flush -\i (04:42:36) trapsize 137 -\i (04:43:09) xNet N3579545 -\i (04:43:09) xname_flush -\i (04:43:09) trapsize 290 -\i (04:43:17) xNet N3579545 -\i (04:43:17) xname_flush -\i (04:43:17) trapsize 290 -\i (04:43:23) xNet Pa9_Usart1_Tx -\i (04:43:23) xname_flush -\i (04:43:23) trapsize 2757 -\i (06:32:33) exit -\e (06:32:33) Do you want to save the changes you made to HC_DFCD_Protocol_V3_0.brd? -\i (06:32:34) fillin yes -\t (06:32:34) Journal end - Wed Aug 26 17:53:03 2026 +\i (00:00:21) zoom out 58.1402 66.3021 +\i (00:00:21) trapsize 5515 +\i (00:10:52) exit +\t (00:10:53) Journal end - Fri Sep 11 15:47:54 2026 diff --git a/docs/allegro.jrl,1 b/docs/allegro.jrl,1 index b56c5ce..f472350 100644 --- a/docs/allegro.jrl,1 +++ b/docs/allegro.jrl,1 @@ -1,2519 +1,953 @@ -\t (00:00:05) Allegro 17.2 S079 Windows SPB 64-bit Edition -\t (00:00:05) Journal start - Tue Aug 25 19:43:26 2026 -\t (00:00:05) Host=DESKTOP-5RA9F3K User=Adminuser Pid=39932 CPUs=20 -\t (00:00:05) CmdLine= D:\Cadence\SPB_17.2\tools\bin\Allegro.exe D:\HC-PMP-SW\Power_ControlPannel\MP_Control_sw_405\MP_SW_Chrg\chrg\docs\HC_DFCD_Protocol_V3_0.brd -\t (00:00:05) - (00:00:05) Loading axlcore.cxt -\t (00:00:06) Opening existing design... -\i (00:00:06) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged HC_DFCD_Protocol_V3_0 -\d (00:00:06) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd -\i (00:00:06) trapsize 8975 -\i (00:00:06) trapsize 9251 -\i (00:00:06) trapsize 9375 -\i (00:00:07) trapsize 8018 -\i (00:00:07) trapsize 8018 -\i (00:00:07) generaledit -\i (00:00:10) zoom out 1 -\i (00:00:10) setwindow pcb -\i (00:00:10) zoom out 138.1616 64.8823 -\i (00:00:10) trapsize 16037 -\i (00:00:10) zoom out 1 -\i (00:00:10) setwindow pcb -\i (00:00:10) zoom out 201.4873 63.2786 -\i (00:00:10) trapsize 32073 -\i (00:00:10) zoom out 1 -\i (00:00:10) setwindow pcb -\i (00:00:10) zoom out 502.3331 132.2094 -\i (00:00:10) trapsize 64146 -\i (00:00:11) zoom in 1 -\i (00:00:11) setwindow pcb -\i (00:00:11) zoom in -32.0050 32.1412 -\i (00:00:11) trapsize 32073 -\i (00:00:11) zoom in 1 -\i (00:00:11) setwindow pcb -\i (00:00:11) zoom in -32.0050 32.1412 -\i (00:00:11) trapsize 16037 -\i (00:00:11) zoom in 1 -\i (00:00:11) setwindow pcb -\i (00:00:11) zoom in -32.0049 32.1412 -\i (00:00:11) trapsize 8018 -\i (00:00:11) zoom in 1 -\i (00:00:11) setwindow pcb -\i (00:00:11) zoom in -32.8068 31.0187 -\i (00:00:11) trapsize 4009 -\i (00:00:11) zoom out 1 -\i (00:00:11) setwindow pcb -\i (00:00:11) zoom out 8.5676 58.6818 -\i (00:00:11) trapsize 8018 -\i (00:00:11) zoom out 1 -\i (00:00:11) setwindow pcb -\i (00:00:11) zoom out 8.4072 58.2007 -\i (00:00:11) trapsize 16037 -\i (00:00:11) zoom in 1 -\i (00:00:11) setwindow pcb -\i (00:00:11) zoom in 80.5716 56.2764 -\i (00:00:11) trapsize 8018 -\i (00:00:12) zoom out 1 -\i (00:00:12) setwindow pcb -\i (00:00:12) zoom out 26.5284 75.0392 -\i (00:00:12) trapsize 16037 -\i (00:00:13) zoom in 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom in 7.2846 90.8350 -\i (00:00:13) trapsize 8018 -\i (00:00:13) zoom in 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom in 7.2846 90.8350 -\i (00:00:13) trapsize 4009 -\i (00:00:14) zoom out 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom out 38.3956 49.0598 -\i (00:00:14) trapsize 8018 -\i (00:00:14) zoom in 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom in 38.3955 49.2202 -\i (00:00:14) trapsize 4009 -\i (00:00:14) zoom out 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom out 38.2352 49.3004 -\i (00:00:14) trapsize 8018 -\i (00:00:15) zoom in 1 -\i (00:00:15) setwindow pcb -\i (00:00:15) zoom in 44.3291 43.6876 -\i (00:00:15) trapsize 4009 -\i (00:00:15) zoom in 1 -\i (00:00:15) setwindow pcb -\i (00:00:15) zoom in 44.3291 43.6876 -\i (00:00:15) trapsize 2005 -\i (00:00:15) zoom out 1 -\i (00:00:15) setwindow pcb -\i (00:00:15) zoom out 41.4425 44.9305 -\i (00:00:15) trapsize 4009 -\i (00:00:16) zoom out 1 -\i (00:00:16) setwindow pcb -\i (00:00:16) zoom out 35.8297 45.3314 -\i (00:00:16) trapsize 8018 -\i (00:00:16) zoom out 1 -\i (00:00:16) setwindow pcb -\i (00:00:16) zoom out 33.7449 44.0484 -\i (00:00:16) trapsize 16037 -\i (00:00:16) zoom out 1 -\i (00:00:16) setwindow pcb -\i (00:00:16) zoom out 37.2732 25.7668 -\i (00:00:16) trapsize 32073 -\i (00:00:16) zoom out 1 -\i (00:00:16) setwindow pcb -\i (00:00:16) zoom out 173.2635 25.1253 -\i (00:00:16) trapsize 64146 -\i (00:00:16) zoom out 1 -\i (00:00:16) setwindow pcb -\i (00:00:16) zoom out 413.1708 40.5204 -\i (00:00:16) trapsize 128293 -\i (00:00:16) zoom out 1 -\i (00:00:16) setwindow pcb -\i (00:00:16) zoom out 859.6295 35.3887 -\i (00:00:16) trapsize 256585 -\i (00:00:17) zoom out 1 -\i (00:00:17) setwindow pcb -\i (00:00:17) zoom out 402.9074 158.5498 -\i (00:00:17) trapsize 513171 -\i (00:00:17) zoom out 1 -\i (00:00:17) setwindow pcb -\i (00:00:17) zoom out 895.5514 382.3806 -\i (00:00:17) trapsize 723589 -\i (00:00:17) zoom out 1 -\i (00:00:17) setwindow pcb -\i (00:00:17) zoom out 1303.7627 580.1737 -\i (00:00:17) trapsize 723589 -\i (00:00:18) zoom in 1 -\i (00:00:18) setwindow pcb -\i (00:00:18) zoom in 30.2460 -56.5847 -\i (00:00:18) trapsize 361795 -\i (00:00:18) zoom in 1 -\i (00:00:18) setwindow pcb -\i (00:00:18) zoom in 30.2460 -56.5846 -\i (00:00:18) trapsize 180897 -\i (00:00:18) zoom in 1 -\i (00:00:18) setwindow pcb -\i (00:00:18) zoom in 30.2460 -56.5846 -\i (00:00:18) trapsize 90449 -\i (00:00:18) zoom in 1 -\i (00:00:18) setwindow pcb -\i (00:00:18) zoom in 28.4371 -60.2025 -\i (00:00:18) trapsize 45224 -\i (00:00:18) zoom out 1 -\i (00:00:18) setwindow pcb -\i (00:00:18) zoom out 24.8191 -9.5513 -\i (00:00:18) trapsize 90449 -\i (00:00:18) zoom out 1 -\i (00:00:18) setwindow pcb -\i (00:00:18) zoom out 32.0551 1.3025 -\i (00:00:18) trapsize 180897 -\i (00:00:19) zoom out 1 -\i (00:00:19) setwindow pcb -\i (00:00:19) zoom out 17.5833 59.1896 -\i (00:00:19) trapsize 361795 -\i (00:00:19) zoom out 1 -\i (00:00:19) setwindow pcb -\i (00:00:19) zoom out 10.3474 211.1433 -\i (00:00:19) trapsize 723589 -\i (00:00:19) zoom in 1 -\i (00:00:19) setwindow pcb -\i (00:00:19) zoom in -13.1693 15.7742 -\i (00:00:19) trapsize 361795 -\i (00:00:20) zoom in 1 -\i (00:00:20) setwindow pcb -\i (00:00:20) zoom in -13.1693 15.7742 -\i (00:00:20) trapsize 180897 -\i (00:00:20) zoom in 1 -\i (00:00:20) setwindow pcb -\i (00:00:20) zoom in -13.1692 15.7743 -\i (00:00:20) trapsize 90449 +\t (00:00:02) allegro 17.2 S079 Windows SPB 64-bit Edition +\t (00:00:02) Journal start - Wed Aug 26 11:20:30 2026 +\t (00:00:02) Host=DESKTOP-5RA9F3K User=Adminuser Pid=37292 CPUs=20 +\t (00:00:02) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe +\t (00:00:02) + (00:00:02) Loading axlcore.cxt +\t (00:00:03) Starting new design... +\i (00:00:04) trapsize 29310 +\i (00:00:04) generaledit +\i (00:00:16) open +\i (00:00:19) fillin "HC_DFCD_Protocol_V3_0.brd" +\i (00:00:19) trapsize 1230 +\i (00:00:19) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed +\t (00:00:19) Opening existing design... +\i (00:00:20) trapsize 8018 +\d (00:00:20) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd +\i (00:00:20) generaledit +\i (00:00:21) zoom in 1 +\i (00:00:21) setwindow pcb +\i (00:00:21) zoom in 9.3881 57.0243 +\i (00:00:21) trapsize 4009 +\i (00:00:21) zoom in 1 +\i (00:00:21) setwindow pcb +\i (00:00:21) zoom in 9.3881 57.1046 +\i (00:00:21) trapsize 2005 \i (00:00:21) zoom out 1 \i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 3.1116 1.3025 -\i (00:00:21) trapsize 180897 +\i (00:00:21) zoom out 11.3926 53.3761 +\i (00:00:21) trapsize 4009 \i (00:00:21) zoom out 1 \i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 3.1116 15.7743 -\i (00:00:21) trapsize 361795 +\i (00:00:21) zoom out 11.3926 53.3762 +\i (00:00:21) trapsize 8018 \i (00:00:21) zoom out 1 \i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 15.7742 15.7743 -\i (00:00:21) trapsize 723589 +\i (00:00:21) zoom out 11.3925 53.3762 +\i (00:00:21) trapsize 16037 \i (00:00:22) zoom in 1 \i (00:00:22) setwindow pcb -\i (00:00:22) zoom in 1.3025 -42.1129 -\i (00:00:22) trapsize 361795 +\i (00:00:22) zoom in -23.2465 36.3774 +\i (00:00:22) trapsize 8018 \i (00:00:22) zoom in 1 \i (00:00:22) setwindow pcb -\i (00:00:22) zoom in 1.3025 -42.1128 -\i (00:00:22) trapsize 180897 -\i (00:00:23) zoom in 1 -\i (00:00:23) setwindow pcb -\i (00:00:23) zoom in 1.3025 -24.0231 -\i (00:00:23) trapsize 90449 -\i (00:00:23) zoom in 1 -\i (00:00:23) setwindow pcb -\i (00:00:23) zoom in 1.3025 -24.0230 -\i (00:00:23) trapsize 45224 -\i (00:00:24) zoom in 1 -\i (00:00:24) setwindow pcb -\i (00:00:24) zoom in 4.0160 1.3026 -\i (00:00:24) trapsize 22612 -\i (00:00:24) zoom out 1 -\i (00:00:24) setwindow pcb -\i (00:00:24) zoom out 3.5638 28.4372 -\i (00:00:24) trapsize 45224 -\i (00:00:24) zoom out 1 -\i (00:00:24) setwindow pcb -\i (00:00:24) zoom out -1.8631 25.7237 -\i (00:00:24) trapsize 90449 -\i (00:00:25) zoom in 1 -\i (00:00:25) setwindow pcb -\i (00:00:25) zoom in -7.2901 53.7627 -\i (00:00:25) trapsize 45224 -\i (00:00:25) zoom in 1 -\i (00:00:25) setwindow pcb -\i (00:00:25) zoom in -2.7677 50.1448 -\i (00:00:25) trapsize 22612 -\i (00:00:25) zoom in 1 -\i (00:00:25) setwindow pcb -\i (00:00:25) zoom in -2.7677 50.1448 -\i (00:00:25) trapsize 11306 -\i (00:00:25) zoom in 1 -\i (00:00:25) setwindow pcb -\i (00:00:25) zoom in -2.7677 50.1448 -\i (00:00:25) trapsize 5653 +\i (00:00:22) zoom in 1.2895 29.4817 +\i (00:00:22) trapsize 4009 \i (00:00:26) zoom out 1 \i (00:00:26) setwindow pcb -\i (00:00:26) zoom out 25.1583 52.9713 -\i (00:00:26) trapsize 11306 +\i (00:00:26) zoom out 34.8060 21.2229 +\i (00:00:26) trapsize 8018 \i (00:00:27) zoom out 1 \i (00:00:27) setwindow pcb -\i (00:00:27) zoom out 13.8523 41.6653 -\i (00:00:27) trapsize 22612 +\i (00:00:27) zoom out 28.8724 21.5436 +\i (00:00:27) trapsize 16037 \i (00:00:27) zoom out 1 \i (00:00:27) setwindow pcb -\i (00:00:27) zoom out 12.9477 40.7608 -\i (00:00:27) trapsize 45224 -\i (00:00:27) zoom in 1 +\i (00:00:27) zoom out -0.5732 30.8448 +\i (00:00:27) trapsize 32073 +\i (00:00:27) zoom out 1 \i (00:00:27) setwindow pcb -\i (00:00:27) zoom in 19.3922 20.8622 -\i (00:00:27) trapsize 22612 +\i (00:00:27) zoom out 91.7976 36.6180 +\i (00:00:27) trapsize 64146 \i (00:00:28) zoom in 1 \i (00:00:28) setwindow pcb -\i (00:00:28) zoom in 22.5579 11.3651 -\i (00:00:28) trapsize 11306 +\i (00:00:28) zoom in -3.7805 8.3937 +\i (00:00:28) trapsize 32073 \i (00:00:28) zoom in 1 \i (00:00:28) setwindow pcb -\i (00:00:28) zoom in 22.5579 11.3651 -\i (00:00:28) trapsize 5653 +\i (00:00:28) zoom in -6.9878 8.3937 +\i (00:00:28) trapsize 16037 \i (00:00:28) zoom in 1 \i (00:00:28) setwindow pcb -\i (00:00:28) zoom in 22.5579 11.3652 -\i (00:00:28) trapsize 2827 -\i (00:00:29) zoom out 1 +\i (00:00:28) zoom in -4.1012 1.0169 +\i (00:00:28) trapsize 8018 +\i (00:00:29) zoom in 1 \i (00:00:29) setwindow pcb -\i (00:00:29) zoom out 29.3416 34.6558 -\i (00:00:29) trapsize 5653 +\i (00:00:29) zoom in -4.1012 1.0169 +\i (00:00:29) trapsize 4009 \i (00:00:30) zoom in 1 \i (00:00:30) setwindow pcb -\i (00:00:30) zoom in 27.5326 45.7357 -\i (00:00:30) trapsize 2827 +\i (00:00:30) zoom in 32.5425 24.1097 +\i (00:00:30) trapsize 2005 \i (00:00:30) zoom in 1 \i (00:00:30) setwindow pcb -\i (00:00:30) zoom in 28.4936 46.3576 -\i (00:00:30) trapsize 1413 -\i (00:00:31) zoom in 1 -\i (00:00:31) setwindow pcb -\i (00:00:31) zoom in 28.4937 45.3400 -\i (00:00:31) trapsize 707 -\i (00:00:31) zoom in 1 -\i (00:00:31) setwindow pcb -\i (00:00:31) zoom in 28.4654 45.2977 -\i (00:00:31) trapsize 353 -\i (00:00:31) zoom out 1 -\i (00:00:31) setwindow pcb -\i (00:00:31) zoom out 29.2992 45.4531 -\i (00:00:31) trapsize 707 -\i (00:00:32) zoom out 1 -\i (00:00:32) setwindow pcb -\i (00:00:32) zoom out 29.2993 45.4108 -\i (00:00:32) trapsize 1413 -\i (00:00:32) zoom in 1 -\i (00:00:32) setwindow pcb -\i (00:00:32) zoom in 30.0341 47.7003 -\i (00:00:32) trapsize 707 -\i (00:00:32) zoom in 1 -\i (00:00:32) setwindow pcb -\i (00:00:32) zoom in 30.0341 47.7003 -\i (00:00:32) trapsize 353 -\i (00:00:33) zoom out 1 -\i (00:00:33) setwindow pcb -\i (00:00:33) zoom out 29.7868 46.8523 -\i (00:00:33) trapsize 707 -\i (00:00:33) zoom out 1 -\i (00:00:33) setwindow pcb -\i (00:00:33) zoom out 29.7869 46.8524 -\i (00:00:33) trapsize 1413 -\i (00:00:33) zoom in 1 -\i (00:00:33) setwindow pcb -\i (00:00:33) zoom in 29.4194 39.9840 -\i (00:00:33) trapsize 707 -\i (00:00:33) zoom in 1 -\i (00:00:33) setwindow pcb -\i (00:00:33) zoom in 29.4336 40.3232 -\i (00:00:33) trapsize 353 -\i (00:00:34) zoom out 1 -\i (00:00:34) setwindow pcb -\i (00:00:34) zoom out 29.5396 40.5988 -\i (00:00:34) trapsize 707 -\i (00:00:34) zoom out 1 -\i (00:00:34) setwindow pcb -\i (00:00:34) zoom out 29.8506 42.9449 -\i (00:00:34) trapsize 1413 -\i (00:00:34) zoom out 1 -\i (00:00:34) setwindow pcb -\i (00:00:34) zoom out 29.8506 42.9448 -\i (00:00:34) trapsize 2827 -\i (00:00:35) zoom in 1 -\i (00:00:35) setwindow pcb -\i (00:00:35) zoom in 30.6985 48.5414 -\i (00:00:35) trapsize 1413 -\i (00:00:35) zoom in 1 -\i (00:00:35) setwindow pcb -\i (00:00:35) zoom in 30.6985 48.5414 -\i (00:00:35) trapsize 707 -\i (00:00:35) zoom in 1 -\i (00:00:35) setwindow pcb -\i (00:00:35) zoom in 30.1191 48.5697 -\i (00:00:35) trapsize 353 -\i (00:00:36) zoom out 1 -\i (00:00:36) setwindow pcb -\i (00:00:36) zoom out 29.5962 48.0963 -\i (00:00:36) trapsize 707 -\i (00:00:36) zoom in 1 -\i (00:00:36) setwindow pcb -\i (00:00:36) zoom in 29.6811 44.6762 -\i (00:00:36) trapsize 353 -\i (00:00:37) zoom in 1 -\i (00:00:37) setwindow pcb -\i (00:00:37) zoom in 29.8154 44.8741 -\i (00:00:37) trapsize 177 -\i (00:00:37) zoom out 1 -\i (00:00:37) setwindow pcb -\i (00:00:37) zoom out 29.8154 44.8918 -\i (00:00:37) trapsize 353 -\i (00:00:37) zoom out 1 -\i (00:00:37) setwindow pcb -\i (00:00:37) zoom out 29.8013 44.8918 -\i (00:00:37) trapsize 707 -\i (00:00:37) zoom out 1 -\i (00:00:37) setwindow pcb -\i (00:00:37) zoom out 29.6741 45.0756 -\i (00:00:37) trapsize 1413 -\i (00:00:37) zoom out 1 -\i (00:00:37) setwindow pcb -\i (00:00:37) zoom out 29.6740 45.0756 -\i (00:00:37) trapsize 2827 -\i (00:00:38) zoom out 1 -\i (00:00:38) setwindow pcb -\i (00:00:38) zoom out 29.6741 45.5278 -\i (00:00:38) trapsize 5653 -\i (00:00:38) zoom in 1 -\i (00:00:38) setwindow pcb -\i (00:00:38) zoom in 29.6741 45.5277 -\i (00:00:38) trapsize 2827 -\i (00:00:38) zoom in 1 -\i (00:00:38) setwindow pcb -\i (00:00:38) zoom in 29.6741 45.3016 -\i (00:00:38) trapsize 1413 -\i (00:00:38) zoom in 1 -\i (00:00:38) setwindow pcb -\i (00:00:38) zoom in 29.7024 45.6973 -\i (00:00:38) trapsize 707 -\i (00:00:39) zoom in 1 -\i (00:00:39) setwindow pcb -\i (00:00:39) zoom in 29.5187 45.9376 -\i (00:00:39) trapsize 353 -\i (00:00:39) zoom in 1 -\i (00:00:39) setwindow pcb -\i (00:00:39) zoom in 29.5328 45.9023 -\i (00:00:39) trapsize 177 -\i (00:00:39) zoom out 1 -\i (00:00:39) setwindow pcb -\i (00:00:39) zoom out 29.6671 45.7186 -\i (00:00:39) trapsize 353 -\i (00:00:40) zoom out 1 -\i (00:00:40) setwindow pcb -\i (00:00:40) zoom out 29.9426 44.7011 -\i (00:00:40) trapsize 707 -\i (00:00:41) zoom out 1 -\i (00:00:41) setwindow pcb -\i (00:00:41) zoom out 29.6317 43.7825 -\i (00:00:41) trapsize 1413 -\i (00:00:41) zoom out 1 -\i (00:00:41) setwindow pcb -\i (00:00:41) zoom out 30.3384 42.8214 -\i (00:00:41) trapsize 2827 -\i (00:00:41) zoom out 1 -\i (00:00:41) setwindow pcb -\i (00:00:41) zoom out 30.1688 42.7083 -\i (00:00:41) trapsize 5653 -\i (00:00:41) zoom out 1 -\i (00:00:41) setwindow pcb -\i (00:00:41) zoom out 30.1689 42.7083 -\i (00:00:41) trapsize 11306 -\i (00:00:42) zoom out 1 -\i (00:00:42) setwindow pcb -\i (00:00:42) zoom out 26.0987 42.4822 -\i (00:00:42) trapsize 22612 -\i (00:00:42) zoom out 1 -\i (00:00:42) setwindow pcb -\i (00:00:42) zoom out 54.2149 41.5778 -\i (00:00:42) trapsize 45224 -\i (00:00:42) zoom out 1 -\i (00:00:42) setwindow pcb -\i (00:00:42) zoom out 208.4298 45.1957 -\i (00:00:42) trapsize 90449 -\i (00:00:42) zoom in 1 -\i (00:00:42) setwindow pcb -\i (00:00:42) zoom in 10.3473 3.5893 -\i (00:00:42) trapsize 45224 -\i (00:00:42) zoom in 1 -\i (00:00:42) setwindow pcb -\i (00:00:42) zoom in 10.3474 3.5893 -\i (00:00:42) trapsize 22612 -\i (00:00:42) zoom in 1 -\i (00:00:42) setwindow pcb -\i (00:00:42) zoom in 10.3474 3.5893 -\i (00:00:42) trapsize 11306 -\i (00:00:43) zoom in 1 -\i (00:00:43) setwindow pcb -\i (00:00:43) zoom in 10.3474 3.5894 -\i (00:00:43) trapsize 5653 -\i (00:00:43) zoom in 1 -\i (00:00:43) setwindow pcb -\i (00:00:43) zoom in 10.3474 3.5894 -\i (00:00:43) trapsize 2827 -\i (00:00:44) zoom out 1 -\i (00:00:44) setwindow pcb -\i (00:00:44) zoom out 12.0434 18.1178 -\i (00:00:44) trapsize 5653 -\i (00:00:44) zoom out 1 -\i (00:00:44) setwindow pcb -\i (00:00:44) zoom out 12.0433 18.0046 -\i (00:00:44) trapsize 11306 -\i (00:00:44) zoom in 1 -\i (00:00:44) setwindow pcb -\i (00:00:44) zoom in 19.0531 53.5058 -\i (00:00:44) trapsize 5653 -\i (00:00:45) zoom in 1 -\i (00:00:45) setwindow pcb -\i (00:00:45) zoom in 27.1935 45.5915 -\i (00:00:45) trapsize 2827 -\i (00:00:45) zoom in 1 -\i (00:00:45) setwindow pcb -\i (00:00:45) zoom in 27.1935 45.5916 -\i (00:00:45) trapsize 1413 -\i (00:00:46) zoom in 1 -\i (00:00:46) setwindow pcb -\i (00:00:46) zoom in 28.7481 45.3089 -\i (00:00:46) trapsize 707 -\i (00:03:01) zoom out 1 -\i (00:03:01) setwindow pcb -\i (00:03:01) zoom out 30.9669 43.6271 -\i (00:03:01) trapsize 1413 -\i (00:03:01) zoom out 1 -\i (00:03:01) setwindow pcb -\i (00:03:01) zoom out 30.6561 43.0619 -\i (00:03:01) trapsize 2827 -\i (00:03:01) zoom out 1 -\i (00:03:01) setwindow pcb -\i (00:03:01) zoom out 30.0342 41.6486 -\i (00:03:01) trapsize 5653 -\i (00:03:02) zoom in 1 -\i (00:03:02) setwindow pcb -\i (00:03:02) zoom in 14.8840 27.2898 -\i (00:03:02) trapsize 2827 -\i (00:03:02) zoom in 1 -\i (00:03:02) setwindow pcb -\i (00:03:02) zoom in 14.8840 27.2898 -\i (00:03:02) trapsize 1413 -\i (00:03:03) zoom out 1 -\i (00:03:03) setwindow pcb -\i (00:03:03) zoom out 15.1667 26.6680 -\i (00:03:03) trapsize 2827 -\i (00:03:03) zoom out 1 -\i (00:03:03) setwindow pcb -\i (00:03:03) zoom out 17.1452 27.7987 -\i (00:03:03) trapsize 5653 -\i (00:03:03) zoom out 1 -\i (00:03:03) setwindow pcb -\i (00:03:03) zoom out 17.1451 27.7986 -\i (00:03:03) trapsize 11306 -\i (00:03:06) zoom in 1 -\i (00:03:06) setwindow pcb -\i (00:03:06) zoom in 15.3362 29.1554 -\i (00:03:06) trapsize 5653 -\i (00:03:06) zoom in 1 -\i (00:03:06) setwindow pcb -\i (00:03:06) zoom in 15.5624 28.4770 -\i (00:03:06) trapsize 2827 -\i (00:03:06) zoom in 1 -\i (00:03:06) setwindow pcb -\i (00:03:06) zoom in 18.1062 28.3075 -\i (00:03:06) trapsize 1413 -\i (00:03:06) zoom in 1 -\i (00:03:06) setwindow pcb -\i (00:03:06) zoom in 18.2476 28.4489 -\i (00:03:06) trapsize 707 -\i (00:03:07) zoom out 1 -\i (00:03:07) setwindow pcb -\i (00:03:07) zoom out 18.9684 29.2686 -\i (00:03:07) trapsize 1413 -\i (00:03:07) zoom out 1 -\i (00:03:07) setwindow pcb -\i (00:03:07) zoom out 18.9684 29.2686 -\i (00:03:07) trapsize 2827 -\i (00:03:07) zoom out 1 -\i (00:03:07) setwindow pcb -\i (00:03:07) zoom out 21.1731 31.2472 -\i (00:03:07) trapsize 5653 -\i (00:03:08) zoom in 1 -\i (00:03:08) setwindow pcb -\i (00:03:08) zoom in 22.6430 41.1966 -\i (00:03:08) trapsize 2827 -\i (00:03:08) zoom in 1 -\i (00:03:08) setwindow pcb -\i (00:03:08) zoom in 24.7347 41.9315 -\i (00:03:08) trapsize 1413 -\i (00:03:09) zoom in 1 -\i (00:03:09) setwindow pcb -\i (00:03:09) zoom in 26.5154 42.4403 -\i (00:03:09) trapsize 707 -\i (00:03:09) zoom in 1 -\i (00:03:09) setwindow pcb -\i (00:03:09) zoom in 28.7202 42.9632 -\i (00:03:09) trapsize 353 -\i (00:03:10) zoom in 1 -\i (00:03:10) setwindow pcb -\i (00:03:10) zoom in 29.7448 42.5816 -\i (00:03:10) trapsize 177 -\i (00:03:10) zoom out 1 -\i (00:03:10) setwindow pcb -\i (00:03:10) zoom out 29.7130 42.5569 -\i (00:03:10) trapsize 353 -\i (00:03:17) zoom in 1 -\i (00:03:17) setwindow pcb -\i (00:03:17) zoom in 29.8615 43.1151 -\i (00:03:17) trapsize 177 -\i (00:03:17) zoom in 1 -\i (00:03:17) setwindow pcb -\i (00:03:17) zoom in 29.8615 43.1151 -\i (00:03:17) trapsize 88 -\i (00:03:17) zoom in 1 -\i (00:03:17) setwindow pcb -\i (00:03:17) zoom in 29.8615 43.1151 -\i (00:03:17) trapsize 44 -\i (00:03:17) zoom in 1 -\i (00:03:17) setwindow pcb -\i (00:03:17) zoom in 29.8615 43.1151 -\i (00:03:17) trapsize 22 -\i (00:03:17) zoom out 1 -\i (00:03:17) setwindow pcb -\i (00:03:17) zoom out 29.8606 43.1151 -\i (00:03:17) trapsize 44 -\i (00:03:17) zoom out 1 -\i (00:03:17) setwindow pcb -\i (00:03:17) zoom out 29.8526 43.1151 -\i (00:03:17) trapsize 88 -\i (00:03:17) zoom out 1 -\i (00:03:17) setwindow pcb -\i (00:03:17) zoom out 29.8525 43.1151 -\i (00:03:17) trapsize 177 -\i (00:03:17) zoom in 1 -\i (00:03:17) setwindow pcb -\i (00:03:17) zoom in 29.8525 43.1151 -\i (00:03:17) trapsize 88 -\i (00:03:17) zoom out 1 -\i (00:03:17) setwindow pcb -\i (00:03:17) zoom out 29.8525 43.1151 -\i (00:03:17) trapsize 177 -\i (00:03:18) zoom out 1 -\i (00:03:18) setwindow pcb -\i (00:03:18) zoom out 29.5840 43.1469 -\i (00:03:18) trapsize 353 -\i (00:03:18) zoom out 1 -\i (00:03:18) setwindow pcb -\i (00:03:18) zoom out 29.5841 43.1468 -\i (00:03:18) trapsize 707 -\i (00:03:19) zoom out 1 -\i (00:03:19) setwindow pcb -\i (00:03:19) zoom out 29.5841 43.1468 -\i (00:03:19) trapsize 1413 -\i (00:03:19) zoom in 1 -\i (00:03:19) setwindow pcb -\i (00:03:19) zoom in 29.0188 48.5735 -\i (00:03:19) trapsize 707 -\i (00:03:20) zoom in 1 -\i (00:03:20) setwindow pcb -\i (00:03:20) zoom in 29.1036 48.5736 -\i (00:03:20) trapsize 353 -\i (00:03:20) zoom out 1 -\i (00:03:20) setwindow pcb -\i (00:03:20) zoom out 29.8244 48.1284 -\i (00:03:20) trapsize 707 -\i (00:03:20) zoom out 1 -\i (00:03:20) setwindow pcb -\i (00:03:20) zoom out 29.8102 48.1002 -\i (00:03:20) trapsize 1413 -\i (00:03:20) zoom out 1 -\i (00:03:20) setwindow pcb -\i (00:03:20) zoom out 29.7820 47.9871 -\i (00:03:20) trapsize 2826 -\i (00:03:20) zoom out 1 -\i (00:03:20) setwindow pcb -\i (00:03:20) zoom out 25.5425 39.1688 -\i (00:03:20) trapsize 5653 -\i (00:03:20) zoom out 1 -\i (00:03:20) setwindow pcb -\i (00:03:20) zoom out 25.5424 38.2643 -\i (00:03:20) trapsize 11306 -\i (00:03:21) zoom in 1 -\i (00:03:21) setwindow pcb -\i (00:03:21) zoom in 14.8648 24.0193 -\i (00:03:21) trapsize 5653 -\i (00:03:21) zoom in 1 -\i (00:03:21) setwindow pcb -\i (00:03:21) zoom in 14.8648 24.0193 -\i (00:03:21) trapsize 2826 -\i (00:03:22) zoom in 1 -\i (00:03:22) setwindow pcb -\i (00:03:22) zoom in 13.3385 30.3504 -\i (00:03:22) trapsize 1413 -\i (00:03:22) zoom in 1 -\i (00:03:22) setwindow pcb -\i (00:03:22) zoom in 13.5929 30.4918 -\i (00:03:22) trapsize 707 -\i (00:03:22) zoom out 1 -\i (00:03:22) setwindow pcb -\i (00:03:22) zoom out 14.0169 31.5235 -\i (00:03:22) trapsize 1413 -\i (00:03:22) zoom out 1 -\i (00:03:22) setwindow pcb -\i (00:03:22) zoom out 14.0170 31.4952 -\i (00:03:22) trapsize 2826 -\i (00:03:22) zoom out 1 -\i (00:03:22) setwindow pcb -\i (00:03:22) zoom out 14.1865 30.8734 -\i (00:03:22) trapsize 5653 -\i (00:03:22) zoom out 1 -\i (00:03:22) setwindow pcb -\i (00:03:22) zoom out 14.4126 30.5342 -\i (00:03:22) trapsize 11306 -\i (00:03:23) zoom in 1 -\i (00:03:23) setwindow pcb -\i (00:03:23) zoom in 19.3871 42.0659 -\i (00:03:23) trapsize 5653 -\i (00:03:23) zoom in 1 -\i (00:03:23) setwindow pcb -\i (00:03:23) zoom in 19.1610 41.3876 -\i (00:03:23) trapsize 2826 -\i (00:03:24) zoom in 1 -\i (00:03:24) setwindow pcb -\i (00:03:24) zoom in 19.7263 38.7308 -\i (00:03:24) trapsize 1413 -\i (00:03:29) zoom out 1 -\i (00:03:29) setwindow pcb -\i (00:03:29) zoom out 30.6079 43.8749 -\i (00:03:29) trapsize 2826 -\i (00:03:29) zoom out 1 -\i (00:03:29) setwindow pcb -\i (00:03:29) zoom out 30.6079 43.8749 -\i (00:03:29) trapsize 5653 -\i (00:03:30) zoom in 1 -\i (00:03:30) setwindow pcb -\i (00:03:30) zoom in 34.5649 51.5628 -\i (00:03:30) trapsize 2826 -\i (00:03:30) zoom in 1 -\i (00:03:30) setwindow pcb -\i (00:03:30) zoom in 34.5649 51.5628 -\i (00:03:30) trapsize 1413 -\i (00:03:31) zoom in 1 -\i (00:03:31) setwindow pcb -\i (00:03:31) zoom in 30.4949 47.8885 -\i (00:03:31) trapsize 707 -\i (00:03:31) zoom in 1 -\i (00:03:31) setwindow pcb -\i (00:03:31) zoom in 30.1699 47.6342 -\i (00:03:31) trapsize 353 -\i (00:03:31) zoom in 1 -\i (00:03:31) setwindow pcb -\i (00:03:31) zoom in 30.1699 47.6342 -\i (00:03:31) trapsize 177 -\i (00:03:32) zoom out 1 -\i (00:03:32) setwindow pcb -\i (00:03:32) zoom out 30.1593 47.5812 -\i (00:03:32) trapsize 353 -\i (00:03:32) zoom out 1 -\i (00:03:32) setwindow pcb -\i (00:03:32) zoom out 30.1523 47.5600 -\i (00:03:32) trapsize 707 -\i (00:04:44) zoom out 1 -\i (00:04:44) setwindow pcb -\i (00:04:44) zoom out 24.4713 44.8467 -\i (00:04:44) trapsize 1413 -\i (00:04:45) zoom out 1 -\i (00:04:45) setwindow pcb -\i (00:04:45) zoom out 24.1886 45.2141 -\i (00:04:45) trapsize 2826 -\i (00:04:45) zoom out 1 -\i (00:04:45) setwindow pcb -\i (00:04:45) zoom out 24.1320 45.2141 -\i (00:04:45) trapsize 5653 -\i (00:04:45) zoom in 1 -\i (00:04:45) setwindow pcb -\i (00:04:45) zoom in 19.3836 42.7268 -\i (00:04:45) trapsize 2826 -\i (00:04:46) zoom in 1 -\i (00:04:46) setwindow pcb -\i (00:04:46) zoom in 19.2706 41.4267 -\i (00:04:46) trapsize 1413 -\i (00:04:46) zoom in 1 -\i (00:04:46) setwindow pcb -\i (00:04:46) zoom in 33.0634 45.1858 -\i (00:04:46) trapsize 707 -\i (00:04:47) zoom in 1 -\i (00:04:47) setwindow pcb -\i (00:04:47) zoom in 33.0634 45.1858 -\i (00:04:47) trapsize 353 -\i (00:04:47) zoom out 1 -\i (00:04:47) setwindow pcb -\i (00:04:47) zoom out 31.0920 45.7581 -\i (00:04:47) trapsize 707 -\i (00:04:47) zoom out 1 -\i (00:04:47) setwindow pcb -\i (00:04:47) zoom out 31.0921 45.7582 -\i (00:04:47) trapsize 1413 -\i (00:04:48) zoom in 1 -\i (00:04:48) setwindow pcb -\i (00:04:48) zoom in 28.0678 48.5563 -\i (00:04:48) trapsize 707 -\i (00:04:48) zoom in 1 -\i (00:04:48) setwindow pcb -\i (00:04:48) zoom in 27.3047 48.6694 -\i (00:04:48) trapsize 353 -\i (00:06:16) zoom out 1 -\i (00:06:16) setwindow pcb -\i (00:06:16) zoom out 29.7001 47.4399 -\i (00:06:16) trapsize 707 -\i (00:06:16) zoom in 1 -\i (00:06:16) setwindow pcb -\i (00:06:16) zoom in 29.7001 47.4400 -\i (00:06:16) trapsize 353 -\i (00:06:16) zoom out 1 -\i (00:06:16) setwindow pcb -\i (00:06:16) zoom out 29.7001 47.4400 -\i (00:06:16) trapsize 707 -\i (00:06:16) zoom out 1 -\i (00:06:16) setwindow pcb -\i (00:06:16) zoom out 29.7001 47.4401 -\i (00:06:16) trapsize 1413 -\i (00:06:16) zoom in 1 -\i (00:06:16) setwindow pcb -\i (00:06:16) zoom in 27.1845 45.6029 -\i (00:06:16) trapsize 707 -\i (00:06:16) zoom in 1 -\i (00:06:16) setwindow pcb -\i (00:06:16) zoom in 27.4248 45.7018 -\i (00:06:16) trapsize 353 -\i (00:06:16) zoom in 1 -\i (00:06:16) setwindow pcb -\i (00:06:16) zoom in 27.5803 45.9774 -\i (00:06:16) trapsize 177 -\i (00:06:17) zoom out 1 -\i (00:06:17) setwindow pcb -\i (00:06:17) zoom out 28.9829 45.9774 -\i (00:06:17) trapsize 353 -\i (00:06:17) zoom out 1 -\i (00:06:17) setwindow pcb -\i (00:06:17) zoom out 28.9971 45.9775 -\i (00:06:17) trapsize 707 -\i (00:06:17) zoom in 1 -\i (00:06:17) setwindow pcb -\i (00:06:17) zoom in 30.6506 47.9277 -\i (00:06:17) trapsize 353 -\i (00:06:17) zoom in 1 -\i (00:06:17) setwindow pcb -\i (00:06:17) zoom in 30.6506 47.9347 -\i (00:06:17) trapsize 177 -\i (00:06:18) zoom out 1 -\i (00:06:18) setwindow pcb -\i (00:06:18) zoom out 30.1596 48.0372 -\i (00:06:18) trapsize 353 +\i (00:00:30) zoom in 32.8232 23.3480 +\i (00:00:30) trapsize 1002 +\i (00:00:30) zoom in 1 +\i (00:00:30) setwindow pcb +\i (00:00:30) zoom in 33.2241 22.9672 +\i (00:00:30) trapsize 501 +\i (00:01:29) zoom out 1 +\i (00:01:29) setwindow pcb +\i (00:01:29) zoom out 31.5303 24.9216 +\i (00:01:29) trapsize 1002 +\i (00:01:30) zoom out 1 +\i (00:01:30) setwindow pcb +\i (00:01:30) zoom out 30.3075 24.9016 +\i (00:01:30) trapsize 2005 +\i (00:01:30) zoom out 1 +\i (00:01:30) setwindow pcb +\i (00:01:30) zoom out 29.9467 24.7012 +\i (00:01:30) trapsize 4009 +\i (00:01:30) zoom out 1 +\i (00:01:30) setwindow pcb +\i (00:01:30) zoom out 29.7062 24.6211 +\i (00:01:30) trapsize 8018 +\i (00:01:30) zoom out 1 +\i (00:01:30) setwindow pcb +\i (00:01:30) zoom out 28.4233 35.8467 +\i (00:01:30) trapsize 16037 +\i (00:01:30) zoom out 1 +\i (00:01:30) setwindow pcb +\i (00:01:30) zoom out 28.1026 71.2708 +\i (00:01:30) trapsize 32073 +\i (00:01:30) zoom out 1 +\i (00:01:30) setwindow pcb +\i (00:01:30) zoom out 98.2122 245.1074 +\i (00:01:30) trapsize 64146 +\i (00:01:30) zoom out 1 +\i (00:01:30) setwindow pcb +\i (00:01:30) zoom out 296.4245 590.2147 +\i (00:01:30) trapsize 128293 +\i (00:01:31) zoom in 1 +\i (00:01:31) setwindow pcb +\i (00:01:31) zoom in -97.4341 64.2147 +\i (00:01:31) trapsize 64146 +\i (00:01:31) zoom in 1 +\i (00:01:31) setwindow pcb +\i (00:01:31) zoom in -97.4341 64.2147 +\i (00:01:31) trapsize 32073 +\i (00:01:31) zoom in 1 +\i (00:01:31) setwindow pcb +\i (00:01:31) zoom in -97.4340 64.8562 +\i (00:01:31) trapsize 16037 +\i (00:01:31) zoom in 1 +\i (00:01:31) setwindow pcb +\i (00:01:31) zoom in -78.5108 74.7989 +\i (00:01:31) trapsize 8018 +\i (00:01:32) zoom in 1 +\i (00:01:32) setwindow pcb +\i (00:01:32) zoom in 38.0752 90.8355 +\i (00:01:32) trapsize 4009 +\i (00:01:32) zoom in 1 +\i (00:01:32) setwindow pcb +\i (00:01:32) zoom in 36.0707 90.8356 +\i (00:01:32) trapsize 2005 +\i (00:01:32) zoom in 1 +\i (00:01:32) setwindow pcb +\i (00:01:32) zoom in 30.8187 90.1942 +\i (00:01:32) trapsize 1002 +\i (00:01:33) zoom in 1 +\i (00:01:33) setwindow pcb +\i (00:01:33) zoom in 21.8583 91.4170 +\i (00:01:33) trapsize 501 +\i (00:01:33) zoom out 1 +\i (00:01:33) setwindow pcb +\i (00:01:33) zoom out 21.9585 91.5072 +\i (00:01:33) trapsize 1002 +\i (00:01:34) zoom in 1 +\i (00:01:34) setwindow pcb +\i (00:01:34) zoom in 18.3102 91.2667 +\i (00:01:34) trapsize 501 +\i (00:01:35) zoom out 1 +\i (00:01:35) setwindow pcb +\i (00:01:35) zoom out 18.3403 91.3670 +\i (00:01:35) trapsize 1002 +\i (00:01:35) zoom out 1 +\i (00:01:35) setwindow pcb +\i (00:01:35) zoom out 18.3604 91.2667 +\i (00:01:35) trapsize 2005 +\i (00:01:35) zoom out 1 +\i (00:01:35) setwindow pcb +\i (00:01:35) zoom out 18.2803 90.5050 +\i (00:01:35) trapsize 4009 +\i (00:01:35) zoom out 1 +\i (00:01:35) setwindow pcb +\i (00:01:35) zoom out 18.2803 90.1842 +\i (00:01:35) trapsize 8018 +\i (00:01:36) zoom out 1 +\i (00:01:36) setwindow pcb +\i (00:01:36) zoom out 19.2424 88.9014 +\i (00:01:36) trapsize 16037 +\i (00:01:36) zoom out 1 +\i (00:01:36) setwindow pcb +\i (00:01:36) zoom out 19.2424 88.5806 +\i (00:01:36) trapsize 32073 +\i (00:01:36) zoom out 1 +\i (00:01:36) setwindow pcb +\i (00:01:36) zoom out 19.2425 60.9977 +\i (00:01:36) trapsize 64146 +\i (00:01:37) zoom out 1 +\i (00:01:37) setwindow pcb +\i (00:01:37) zoom out 17.9595 115.5317 +\i (00:01:37) trapsize 128293 +\i (00:01:37) zoom out 1 +\i (00:01:37) setwindow pcb +\i (00:01:37) zoom out 17.9595 323.3659 +\i (00:01:37) trapsize 256585 +\i (00:01:37) zoom in 1 +\i (00:01:37) setwindow pcb +\i (00:01:37) zoom in -79.5429 23.1610 +\i (00:01:37) trapsize 128293 +\i (00:01:37) zoom in 1 +\i (00:01:37) setwindow pcb +\i (00:01:37) zoom in -79.5429 23.1610 +\i (00:01:37) trapsize 64146 +\i (00:01:37) zoom in 1 +\i (00:01:37) setwindow pcb +\i (00:01:37) zoom in -79.5429 23.1610 +\i (00:01:37) trapsize 32073 +\i (00:01:37) zoom in 1 +\i (00:01:37) setwindow pcb +\i (00:01:37) zoom in -76.9770 37.2732 +\i (00:01:37) trapsize 16037 +\i (00:01:37) zoom in 1 +\i (00:01:37) setwindow pcb +\i (00:01:37) zoom in -75.0526 41.7635 +\i (00:01:37) trapsize 8018 +\i (00:01:38) zoom in 1 +\i (00:01:38) setwindow pcb +\i (00:01:38) zoom in -3.0483 90.8355 +\i (00:01:38) trapsize 4009 +\i (00:01:38) zoom in 1 +\i (00:01:38) setwindow pcb +\i (00:01:38) zoom in -0.7229 92.4392 +\i (00:01:38) trapsize 2005 +\i (00:01:39) zoom in 1 +\i (00:01:39) setwindow pcb +\i (00:01:39) zoom in 22.9712 93.2811 +\i (00:01:39) trapsize 1002 +\i (00:01:39) zoom in 1 +\i (00:01:39) setwindow pcb +\i (00:01:39) zoom in 22.9712 93.2811 +\i (00:01:39) trapsize 501 +\i (00:01:54) zoom out 1 +\i (00:01:54) setwindow pcb +\i (00:01:54) zoom out 19.1125 92.5294 +\i (00:01:54) trapsize 1002 +\i (00:07:02) zoom in 1 +\i (00:07:02) setwindow pcb +\i (00:07:02) zoom in 18.4710 93.8724 +\i (00:07:02) trapsize 501 +\i (00:07:04) zoom out 1 +\i (00:07:04) setwindow pcb +\i (00:07:04) zoom out 19.5334 91.9480 +\i (00:07:04) trapsize 1002 +\i (00:07:09) zoom in 1 +\i (00:07:09) setwindow pcb +\i (00:07:09) zoom in 18.4911 91.9882 +\i (00:07:09) trapsize 501 +\i (00:07:10) zoom out 1 +\i (00:07:10) setwindow pcb +\i (00:07:10) zoom out 19.2128 91.7075 +\i (00:07:10) trapsize 1002 +\i (00:07:25) zoom out 1 +\i (00:07:25) setwindow pcb +\i (00:07:25) zoom out 18.4110 90.8857 +\i (00:07:25) trapsize 2005 +\i (00:07:25) zoom in 1 +\i (00:07:25) setwindow pcb +\i (00:07:25) zoom in 19.7340 89.8032 +\i (00:07:25) trapsize 1002 +\i (00:07:25) zoom in 1 +\i (00:07:25) setwindow pcb +\i (00:07:25) zoom in 20.3755 89.3422 +\i (00:07:25) trapsize 501 +\i (00:07:29) drag_start grid 20.6361 90.3947 +\i (00:07:29) drag_stop 20.6361 90.5751 +\i (00:07:51) zoom out 1 +\i (00:07:51) setwindow pcb +\i (00:07:51) zoom out 21.4980 90.2343 +\i (00:07:51) trapsize 1002 \i (00:07:57) zoom out 1 \i (00:07:57) setwindow pcb -\i (00:07:57) zoom out 26.9728 45.2108 -\i (00:07:57) trapsize 707 +\i (00:07:57) zoom out 26.5496 91.6375 +\i (00:07:57) trapsize 2005 \i (00:07:57) zoom out 1 \i (00:07:57) setwindow pcb -\i (00:07:57) zoom out 26.9728 45.2107 -\i (00:07:57) trapsize 1413 -\i (00:11:49) zoom out 1 -\i (00:11:49) setwindow pcb -\i (00:11:49) zoom out 18.6067 51.6549 -\i (00:11:49) trapsize 2826 -\i (00:11:49) zoom in 1 -\i (00:11:49) setwindow pcb -\i (00:11:49) zoom in 18.1544 50.8071 -\i (00:11:49) trapsize 1413 -\i (00:11:49) zoom out 1 -\i (00:11:49) setwindow pcb -\i (00:11:49) zoom out 18.1545 50.8071 -\i (00:11:49) trapsize 2826 -\i (00:11:49) zoom out 1 -\i (00:11:49) setwindow pcb -\i (00:11:49) zoom out 18.0979 50.6375 -\i (00:11:49) trapsize 5653 -\i (00:11:49) zoom out 1 -\i (00:11:49) setwindow pcb -\i (00:11:49) zoom out 17.5326 52.4464 -\i (00:11:49) trapsize 11306 -\i (00:11:50) zoom in 1 -\i (00:11:50) setwindow pcb -\i (00:11:50) zoom in -8.6964 92.6943 -\i (00:11:50) trapsize 5653 -\i (00:11:50) zoom in 1 -\i (00:11:50) setwindow pcb -\i (00:11:50) zoom in -9.4878 93.4857 -\i (00:11:50) trapsize 2826 -\i (00:11:50) zoom in 1 -\i (00:11:50) setwindow pcb -\i (00:11:50) zoom in -9.6008 93.5988 -\i (00:11:50) trapsize 1413 -\i (00:11:50) zoom out 1 -\i (00:11:50) setwindow pcb -\i (00:11:50) zoom out 5.9161 87.2394 -\i (00:11:50) trapsize 2826 -\i (00:11:50) zoom out 1 -\i (00:11:50) setwindow pcb -\i (00:11:50) zoom out 5.9726 86.9002 -\i (00:11:50) trapsize 5653 -\i (00:11:51) zoom in 1 -\i (00:11:51) setwindow pcb -\i (00:11:51) zoom in 13.9996 86.7872 -\i (00:11:51) trapsize 2826 -\i (00:11:51) zoom in 1 -\i (00:11:51) setwindow pcb -\i (00:11:51) zoom in 14.3388 87.6916 -\i (00:11:51) trapsize 1413 -\i (00:11:51) zoom in 1 -\i (00:11:51) setwindow pcb -\i (00:11:51) zoom in 13.7170 87.9178 -\i (00:11:51) trapsize 707 -\i (00:11:51) zoom out 1 -\i (00:11:51) setwindow pcb -\i (00:11:51) zoom out 8.3328 90.2778 -\i (00:11:51) trapsize 1413 -\i (00:11:52) zoom out 1 -\i (00:11:52) setwindow pcb -\i (00:11:52) zoom out 8.3610 90.2496 -\i (00:11:52) trapsize 2826 -\i (00:11:52) zoom in 1 -\i (00:11:52) setwindow pcb -\i (00:11:52) zoom in 8.1914 95.0545 -\i (00:11:52) trapsize 1413 -\i (00:11:52) zoom in 1 -\i (00:11:52) setwindow pcb -\i (00:11:52) zoom in 7.9653 94.7719 -\i (00:11:52) trapsize 707 -\i (00:11:52) zoom in 1 -\i (00:11:52) setwindow pcb -\i (00:11:52) zoom in 8.3893 94.1360 -\i (00:11:52) trapsize 353 -\i (00:11:53) zoom in 1 -\i (00:11:53) setwindow pcb -\i (00:11:53) zoom in 9.9862 92.0304 -\i (00:11:53) trapsize 177 -\i (00:11:53) zoom out 1 -\i (00:11:53) setwindow pcb -\i (00:11:53) zoom out 9.5906 92.0374 -\i (00:11:53) trapsize 353 -\i (00:11:53) zoom out 1 -\i (00:11:53) setwindow pcb -\i (00:11:53) zoom out 9.5905 91.9951 -\i (00:11:53) trapsize 707 -\i (00:11:54) zoom in 1 -\i (00:11:54) setwindow pcb -\i (00:11:54) zoom in 9.8167 89.5220 -\i (00:11:54) trapsize 353 -\i (00:11:54) zoom in 1 -\i (00:11:54) setwindow pcb -\i (00:11:54) zoom in 9.8167 89.4161 -\i (00:11:54) trapsize 177 -\i (00:11:55) zoom out 1 -\i (00:11:55) setwindow pcb -\i (00:11:55) zoom out 9.6436 89.6210 -\i (00:11:55) trapsize 353 -\i (00:12:04) zoom out 1 -\i (00:12:04) setwindow pcb -\i (00:12:04) zoom out 9.8979 91.1402 -\i (00:12:04) trapsize 707 -\i (00:12:04) zoom out 1 -\i (00:12:04) setwindow pcb -\i (00:12:04) zoom out 9.8838 91.1402 -\i (00:12:04) trapsize 1413 -\i (00:12:04) zoom out 1 -\i (00:12:04) setwindow pcb -\i (00:12:04) zoom out 9.8838 91.1401 -\i (00:12:04) trapsize 2826 -\i (00:12:05) zoom out 1 -\i (00:12:05) setwindow pcb -\i (00:12:05) zoom out 10.8448 79.7215 -\i (00:12:05) trapsize 5653 -\i (00:12:05) zoom out 1 -\i (00:12:05) setwindow pcb -\i (00:12:05) zoom out 11.2970 79.4953 -\i (00:12:05) trapsize 11306 -\i (00:12:05) zoom in 1 -\i (00:12:05) setwindow pcb -\i (00:12:05) zoom in 5.8204 58.9192 -\i (00:12:05) trapsize 5653 -\i (00:12:06) zoom in 1 -\i (00:12:06) setwindow pcb -\i (00:12:06) zoom in 3.8984 65.3634 -\i (00:12:06) trapsize 2826 -\i (00:12:06) zoom in 1 -\i (00:12:06) setwindow pcb -\i (00:12:06) zoom in 8.1380 67.3419 -\i (00:12:06) trapsize 1413 -\i (00:12:07) zoom in 1 -\i (00:12:07) setwindow pcb -\i (00:12:07) zoom in 12.1798 69.3769 -\i (00:12:07) trapsize 707 -\i (00:12:07) zoom in 1 -\i (00:12:07) setwindow pcb -\i (00:12:07) zoom in 12.0667 71.0587 -\i (00:12:07) trapsize 353 -\i (00:12:57) zoom out 1 -\i (00:12:57) setwindow pcb -\i (00:12:57) zoom out 10.7948 71.5745 -\i (00:12:57) trapsize 707 -\i (00:12:57) zoom out 1 -\i (00:12:57) setwindow pcb -\i (00:12:57) zoom out 10.3851 71.3060 -\i (00:12:57) trapsize 1413 -\i (00:12:57) zoom out 1 -\i (00:12:57) setwindow pcb -\i (00:12:57) zoom out 9.9611 71.1081 -\i (00:12:57) trapsize 2826 -\i (00:12:58) zoom in 1 -\i (00:12:58) setwindow pcb -\i (00:12:58) zoom in 1.8210 67.8296 -\i (00:12:58) trapsize 1413 -\i (00:12:58) zoom in 1 -\i (00:12:58) setwindow pcb -\i (00:12:58) zoom in 1.7363 67.6600 -\i (00:12:58) trapsize 707 -\i (00:12:58) zoom in 1 -\i (00:12:58) setwindow pcb -\i (00:12:58) zoom in 1.8352 68.8188 -\i (00:12:58) trapsize 353 -\i (00:12:58) zoom in 1 -\i (00:12:58) setwindow pcb -\i (00:12:58) zoom in 1.8352 68.8189 -\i (00:12:58) trapsize 177 -\i (00:12:59) zoom out 1 -\i (00:12:59) setwindow pcb -\i (00:12:59) zoom out 2.6442 69.4195 -\i (00:12:59) trapsize 353 -\i (00:12:59) zoom out 1 -\i (00:12:59) setwindow pcb -\i (00:12:59) zoom out 2.6372 69.4054 -\i (00:12:59) trapsize 707 -\i (00:12:59) zoom out 1 -\i (00:12:59) setwindow pcb -\i (00:12:59) zoom out 3.3015 69.1794 -\i (00:12:59) trapsize 1413 -\i (00:12:59) zoom out 1 -\i (00:12:59) setwindow pcb -\i (00:12:59) zoom out 3.6407 68.3315 -\i (00:12:59) trapsize 2826 -\i (00:12:59) zoom out 1 -\i (00:12:59) setwindow pcb -\i (00:12:59) zoom out 3.6406 68.3315 -\i (00:12:59) trapsize 5653 -\i (00:13:00) zoom out 1 -\i (00:13:00) setwindow pcb -\i (00:13:00) zoom out 16.5290 88.2293 -\i (00:13:00) trapsize 11306 -\i (00:13:00) zoom in 1 -\i (00:13:00) setwindow pcb -\i (00:13:00) zoom in 57.1478 77.3761 -\i (00:13:00) trapsize 5653 -\i (00:13:00) zoom in 1 -\i (00:13:00) setwindow pcb -\i (00:13:00) zoom in 56.5825 75.4541 -\i (00:13:00) trapsize 2826 -\i (00:13:00) zoom in 1 -\i (00:13:00) setwindow pcb -\i (00:13:00) zoom in 56.2998 75.3410 -\i (00:13:00) trapsize 1413 -\i (00:13:00) zoom out 1 -\i (00:13:00) setwindow pcb -\i (00:13:00) zoom out 44.2876 74.6627 -\i (00:13:00) trapsize 2826 -\i (00:13:00) zoom out 1 -\i (00:13:00) setwindow pcb -\i (00:13:00) zoom out 44.2877 74.6628 -\i (00:13:00) trapsize 5653 -\i (00:13:00) zoom out 1 -\i (00:13:00) setwindow pcb -\i (00:13:00) zoom out 44.5137 73.5322 -\i (00:13:00) trapsize 11306 -\i (00:13:01) zoom in 1 -\i (00:13:01) setwindow pcb -\i (00:13:01) zoom in 3.3614 84.6117 -\i (00:13:01) trapsize 5653 -\i (00:13:01) zoom in 1 -\i (00:13:01) setwindow pcb -\i (00:13:01) zoom in 3.2483 84.6117 -\i (00:13:01) trapsize 2826 -\i (00:13:01) zoom in 1 -\i (00:13:01) setwindow pcb -\i (00:13:01) zoom in 3.1918 84.6118 -\i (00:13:01) trapsize 1413 -\i (00:13:02) zoom in 1 -\i (00:13:02) setwindow pcb -\i (00:13:02) zoom in 10.3143 72.6279 -\i (00:13:02) trapsize 707 -\i (00:13:02) zoom in 1 -\i (00:13:02) setwindow pcb -\i (00:13:02) zoom in 10.2720 72.2464 -\i (00:13:02) trapsize 353 -\i (00:13:03) zoom out 1 -\i (00:13:03) setwindow pcb -\i (00:13:03) zoom out 12.8722 72.1263 -\i (00:13:03) trapsize 707 -\i (00:13:06) zoom out 1 -\i (00:13:06) setwindow pcb -\i (00:13:06) zoom out 11.2613 74.0766 -\i (00:13:06) trapsize 1413 -\i (00:13:06) zoom out 1 -\i (00:13:06) setwindow pcb -\i (00:13:06) zoom out 9.4806 73.7374 -\i (00:13:06) trapsize 2826 -\i (00:13:06) zoom out 1 -\i (00:13:06) setwindow pcb -\i (00:13:06) zoom out 8.8589 73.5677 -\i (00:13:06) trapsize 5653 -\i (00:13:06) zoom out 1 -\i (00:13:06) setwindow pcb -\i (00:13:06) zoom out 6.5977 72.7764 -\i (00:13:06) trapsize 11306 -\i (00:13:07) zoom in 1 -\i (00:13:07) setwindow pcb -\i (00:13:07) zoom in -9.7814 89.2825 -\i (00:13:08) trapsize 5653 -\i (00:13:08) zoom in 1 -\i (00:13:08) setwindow pcb -\i (00:13:08) zoom in 9.6642 89.9609 -\i (00:13:08) trapsize 2826 -\i (00:13:08) zoom in 1 -\i (00:13:08) setwindow pcb -\i (00:13:08) zoom in 9.3251 89.2826 -\i (00:13:08) trapsize 1413 -\i (00:13:09) zoom in 1 -\i (00:13:09) setwindow pcb -\i (00:13:09) zoom in 11.5863 92.5895 -\i (00:13:09) trapsize 707 -\i (00:13:11) zoom in 1 -\i (00:13:11) setwindow pcb -\i (00:13:11) zoom in 10.4416 91.7558 -\i (00:13:11) trapsize 353 -\i (00:13:12) zoom out 1 -\i (00:13:12) setwindow pcb -\i (00:13:12) zoom out 9.7703 91.2188 -\i (00:13:12) trapsize 707 -\i (00:13:12) zoom out 1 -\i (00:13:12) setwindow pcb -\i (00:13:12) zoom out 9.7704 91.2188 -\i (00:13:12) trapsize 1413 -\i (00:13:16) zoom out 1 -\i (00:13:16) setwindow pcb -\i (00:13:16) zoom out 20.3411 87.6859 -\i (00:13:16) trapsize 2826 -\i (00:13:16) zoom out 1 -\i (00:13:16) setwindow pcb -\i (00:13:16) zoom out 20.5673 87.4597 -\i (00:13:16) trapsize 5653 -\i (00:13:16) zoom out 1 -\i (00:13:16) setwindow pcb -\i (00:13:16) zoom out 28.8203 77.8499 -\i (00:13:16) trapsize 11306 -\i (00:13:16) zoom out 1 -\i (00:13:16) setwindow pcb -\i (00:13:16) zoom out 108.0229 77.8500 -\i (00:13:16) trapsize 22611 -\i (00:13:17) zoom in 1 -\i (00:13:17) setwindow pcb -\i (00:13:17) zoom in 38.3805 37.1498 -\i (00:13:17) trapsize 11306 -\i (00:13:17) zoom in 1 -\i (00:13:17) setwindow pcb -\i (00:13:17) zoom in 38.1544 37.1498 -\i (00:13:17) trapsize 5653 -\i (00:13:19) zoom out 1 -\i (00:13:19) setwindow pcb -\i (00:13:19) zoom out 40.1895 53.5429 -\i (00:13:19) trapsize 11306 -\i (00:13:20) zoom in 1 -\i (00:13:20) setwindow pcb -\i (00:13:20) zoom in 25.2660 68.4663 -\i (00:13:20) trapsize 5653 -\i (00:13:20) zoom out 1 -\i (00:13:20) setwindow pcb -\i (00:13:20) zoom out 11.0209 73.6669 -\i (00:13:20) trapsize 11306 -\i (00:13:22) zoom in 1 -\i (00:13:22) setwindow pcb -\i (00:13:22) zoom in -14.7559 94.9214 -\i (00:13:22) trapsize 5653 -\i (00:13:22) zoom in 1 -\i (00:13:22) setwindow pcb -\i (00:13:22) zoom in -14.7558 94.8084 -\i (00:13:22) trapsize 2826 -\i (00:13:22) zoom in 1 -\i (00:13:22) setwindow pcb -\i (00:13:22) zoom in -14.7558 94.8084 -\i (00:13:22) trapsize 1413 -\i (00:13:23) zoom in 1 -\i (00:13:23) setwindow pcb -\i (00:13:23) zoom in 14.6670 89.9753 -\i (00:13:23) trapsize 707 -\i (00:13:23) zoom out 1 -\i (00:13:23) setwindow pcb -\i (00:13:23) zoom out 14.5823 89.9753 -\i (00:13:23) trapsize 1413 -\i (00:13:23) zoom out 1 -\i (00:13:23) setwindow pcb -\i (00:13:23) zoom out 14.5822 89.9754 -\i (00:13:23) trapsize 2826 -\i (00:13:24) zoom in 1 -\i (00:13:24) setwindow pcb -\i (00:13:24) zoom in 17.6912 90.6536 -\i (00:13:24) trapsize 1413 -\i (00:13:24) zoom in 1 -\i (00:13:24) setwindow pcb -\i (00:13:24) zoom in 11.4166 91.1058 -\i (00:13:24) trapsize 707 -\i (00:13:25) zoom in 1 -\i (00:13:25) setwindow pcb -\i (00:13:25) zoom in 10.4274 91.1200 -\i (00:13:25) trapsize 353 -\i (00:13:37) zoom out 1 -\i (00:13:37) setwindow pcb -\i (00:13:37) zoom out 7.3042 91.9679 -\i (00:13:37) trapsize 707 -\i (00:13:37) zoom out 1 -\i (00:13:37) setwindow pcb -\i (00:13:37) zoom out 7.3749 91.7842 -\i (00:13:37) trapsize 1413 -\i (00:13:38) zoom in 1 -\i (00:13:38) setwindow pcb -\i (00:13:38) zoom in 15.7128 90.5123 -\i (00:13:38) trapsize 707 -\i (00:13:38) zoom in 1 -\i (00:13:38) setwindow pcb -\i (00:13:38) zoom in 15.4585 90.2862 -\i (00:13:38) trapsize 353 -\i (00:13:39) zoom out 1 -\i (00:13:39) setwindow pcb -\i (00:13:39) zoom out 13.0278 90.6466 -\i (00:13:39) trapsize 707 -\i (00:13:59) zoom in 1 -\i (00:13:59) setwindow pcb -\i (00:13:59) zoom in 18.7796 87.8202 -\i (00:13:59) trapsize 353 -\i (00:13:59) zoom out 1 -\i (00:13:59) setwindow pcb -\i (00:13:59) zoom out 18.7796 87.8202 -\i (00:13:59) trapsize 707 -\i (00:14:18) zoom out 1 -\i (00:14:18) setwindow pcb -\i (00:14:18) zoom out 20.5178 89.3464 -\i (00:14:18) trapsize 1413 -\i (00:14:18) zoom out 1 -\i (00:14:18) setwindow pcb -\i (00:14:18) zoom out 20.5178 89.3464 -\i (00:14:18) trapsize 2826 -\i (00:14:18) zoom out 1 -\i (00:14:18) setwindow pcb -\i (00:14:18) zoom out 20.5178 89.3465 -\i (00:14:18) trapsize 5653 -\i (00:14:18) zoom out 1 -\i (00:14:18) setwindow pcb -\i (00:14:18) zoom out 20.5178 89.3464 -\i (00:14:18) trapsize 11306 -\i (00:14:19) zoom out 1 -\i (00:14:19) setwindow pcb -\i (00:14:19) zoom out 37.0238 62.2130 -\i (00:14:19) trapsize 22611 -\i (00:14:20) zoom in 1 -\i (00:14:20) setwindow pcb -\i (00:14:20) zoom in 17.1260 21.0606 -\i (00:14:20) trapsize 11306 -\i (00:14:20) zoom in 1 -\i (00:14:20) setwindow pcb -\i (00:14:20) zoom in 17.1260 20.8345 -\i (00:14:20) trapsize 5653 -\i (00:14:20) zoom in 1 -\i (00:14:20) setwindow pcb -\i (00:14:20) zoom in 17.1260 20.8346 -\i (00:14:20) trapsize 2826 -\i (00:14:20) zoom in 1 -\i (00:14:20) setwindow pcb -\i (00:14:20) zoom in 19.5002 23.7741 -\i (00:14:20) trapsize 1413 -\i (00:14:21) zoom out 1 -\i (00:14:21) setwindow pcb -\i (00:14:21) zoom out 15.0911 25.2438 -\i (00:14:21) trapsize 2826 -\i (00:14:21) zoom out 1 -\i (00:14:21) setwindow pcb -\i (00:14:21) zoom out 15.0911 25.2438 -\i (00:14:21) trapsize 5653 -\i (00:14:21) zoom out 1 -\i (00:14:21) setwindow pcb -\i (00:14:21) zoom out 15.0910 25.2439 -\i (00:14:21) trapsize 11306 -\i (00:14:22) zoom out 1 -\i (00:14:22) setwindow pcb -\i (00:14:22) zoom out 15.0909 25.2438 -\i (00:14:22) trapsize 22611 -\i (00:14:23) zoom in 1 -\i (00:14:23) setwindow pcb -\i (00:14:23) zoom in -31.0359 19.8172 -\i (00:14:23) trapsize 11306 -\i (00:14:23) zoom in 1 -\i (00:14:23) setwindow pcb -\i (00:14:23) zoom in -31.0359 19.8172 -\i (00:14:23) trapsize 5653 -\i (00:14:26) zoom in 1 -\i (00:14:26) setwindow pcb -\i (00:14:26) zoom in 43.8071 20.6086 -\i (00:14:26) trapsize 2826 -\i (00:14:26) zoom in 1 -\i (00:14:26) setwindow pcb -\i (00:14:26) zoom in 43.8071 20.6086 -\i (00:14:26) trapsize 1413 -\i (00:14:26) zoom in 1 -\i (00:14:26) setwindow pcb -\i (00:14:26) zoom in 37.9847 22.4740 -\i (00:14:26) trapsize 707 -\i (00:14:26) zoom in 1 -\i (00:14:26) setwindow pcb -\i (00:14:26) zoom in 34.7627 23.2371 -\i (00:14:26) trapsize 353 -\i (00:14:27) zoom in 1 -\i (00:14:27) setwindow pcb -\i (00:14:27) zoom in 34.7627 23.2442 -\i (00:14:27) trapsize 177 -\i (00:14:28) zoom out 1 -\i (00:14:28) setwindow pcb -\i (00:14:28) zoom out 35.8756 23.5798 -\i (00:14:28) trapsize 353 -\i (00:14:29) zoom in 1 -\i (00:14:29) setwindow pcb -\i (00:14:29) zoom in 35.9534 24.8518 -\i (00:14:29) trapsize 177 -\i (00:14:34) zoom out 1 -\i (00:14:34) setwindow pcb -\i (00:14:34) zoom out 35.6743 24.3077 -\i (00:14:34) trapsize 353 -\i (00:14:34) zoom out 1 -\i (00:14:34) setwindow pcb -\i (00:14:34) zoom out 35.6955 24.3006 -\i (00:14:34) trapsize 707 -\i (00:14:34) zoom out 1 -\i (00:14:34) setwindow pcb -\i (00:14:34) zoom out 37.2500 23.9333 -\i (00:14:34) trapsize 1413 -\i (00:14:34) zoom out 1 -\i (00:14:34) setwindow pcb -\i (00:14:34) zoom out 37.3630 23.8485 -\i (00:14:34) trapsize 2826 -\i (00:14:34) zoom out 1 -\i (00:14:34) setwindow pcb -\i (00:14:34) zoom out 39.9633 24.0180 -\i (00:14:34) trapsize 5653 -\i (00:14:38) zoom out 1 -\i (00:14:38) setwindow pcb -\i (00:14:38) zoom out 52.9648 39.7328 -\i (00:14:38) trapsize 11306 -\i (00:14:39) zoom in 1 -\i (00:14:39) setwindow pcb -\i (00:14:39) zoom in 60.9917 57.1434 -\i (00:14:39) trapsize 5653 -\i (00:14:40) zoom in 1 -\i (00:14:40) setwindow pcb -\i (00:14:40) zoom in 55.6781 61.3265 -\i (00:14:40) trapsize 2826 -\i (00:14:40) zoom in 1 -\i (00:14:40) setwindow pcb -\i (00:14:40) zoom in 56.1868 61.4395 -\i (00:14:40) trapsize 1413 -\i (00:14:40) zoom in 1 -\i (00:14:40) setwindow pcb -\i (00:14:40) zoom in 58.3914 55.7868 -\i (00:14:40) trapsize 707 -\i (00:14:40) zoom in 1 -\i (00:14:40) setwindow pcb -\i (00:14:40) zoom in 58.4762 56.3662 -\i (00:14:40) trapsize 353 -\i (00:14:41) zoom out 1 -\i (00:14:41) setwindow pcb -\i (00:14:41) zoom out 58.1794 57.2636 -\i (00:14:41) trapsize 707 -\i (00:14:42) zoom out 1 -\i (00:14:42) setwindow pcb -\i (00:14:42) zoom out 57.2327 58.0268 -\i (00:14:42) trapsize 1413 -\i (00:14:42) zoom in 1 -\i (00:14:42) setwindow pcb -\i (00:14:42) zoom in 57.1761 59.5531 -\i (00:14:42) trapsize 707 -\i (00:14:42) zoom in 1 -\i (00:14:42) setwindow pcb -\i (00:14:42) zoom in 57.1761 59.5673 -\i (00:14:42) trapsize 353 -\i (00:14:43) zoom out 1 -\i (00:14:43) setwindow pcb -\i (00:14:43) zoom out 56.7521 58.7901 -\i (00:14:43) trapsize 707 -\i (00:14:43) zoom out 1 -\i (00:14:43) setwindow pcb -\i (00:14:43) zoom out 57.1761 59.3130 -\i (00:14:43) trapsize 1413 -\i (00:14:44) zoom in 1 -\i (00:14:44) setwindow pcb -\i (00:14:44) zoom in 58.1937 59.8217 -\i (00:14:44) trapsize 707 -\i (00:14:45) zoom in 1 -\i (00:14:45) setwindow pcb -\i (00:14:45) zoom in 54.6607 58.3520 -\i (00:14:45) trapsize 353 -\i (00:14:46) zoom out 1 -\i (00:14:46) setwindow pcb -\i (00:14:46) zoom out 56.5756 57.3557 -\i (00:14:46) trapsize 707 -\i (00:14:46) zoom out 1 -\i (00:14:46) setwindow pcb -\i (00:14:46) zoom out 56.5756 57.3558 -\i (00:14:46) trapsize 1413 -\i (00:14:50) zoom in 1 -\i (00:14:50) setwindow pcb -\i (00:14:50) zoom in 57.5365 58.5994 -\i (00:14:50) trapsize 707 -\i (00:14:51) zoom in 1 -\i (00:14:51) setwindow pcb -\i (00:14:51) zoom in 58.4269 57.3275 -\i (00:14:51) trapsize 353 -\i (00:14:52) zoom in 1 -\i (00:14:52) setwindow pcb -\i (00:14:52) zoom in 59.6563 57.2851 -\i (00:14:52) trapsize 177 -\i (00:14:52) zoom out 1 -\i (00:14:52) setwindow pcb -\i (00:14:52) zoom out 59.6387 57.2675 -\i (00:14:52) trapsize 353 -\i (00:15:56) zoom in 1 -\i (00:15:56) setwindow pcb -\i (00:15:56) zoom in 55.7666 57.3381 -\i (00:15:56) trapsize 177 -\i (00:15:57) zoom in 1 -\i (00:15:57) setwindow pcb -\i (00:15:57) zoom in 55.9327 57.4618 -\i (00:15:57) trapsize 88 -\i (00:15:57) zoom out 1 -\i (00:15:57) setwindow pcb -\i (00:15:57) zoom out 55.9945 57.4230 -\i (00:15:57) trapsize 177 -\i (00:15:58) zoom out 1 -\i (00:15:58) setwindow pcb -\i (00:15:58) zoom out 55.9945 57.4229 -\i (00:15:58) trapsize 353 -\i (00:15:58) zoom out 1 -\i (00:15:58) setwindow pcb -\i (00:15:58) zoom out 55.9946 57.4230 -\i (00:15:58) trapsize 707 -\i (00:15:59) zoom in 1 -\i (00:15:59) setwindow pcb -\i (00:15:59) zoom in 55.9946 57.4513 -\i (00:15:59) trapsize 353 -\i (00:15:59) zoom in 1 -\i (00:15:59) setwindow pcb -\i (00:15:59) zoom in 56.0228 57.6068 -\i (00:15:59) trapsize 177 -\i (00:16:00) zoom in 1 -\i (00:16:00) setwindow pcb -\i (00:16:00) zoom in 56.0229 57.6068 -\i (00:16:00) trapsize 88 -\i (00:16:02) zoom out 1 -\i (00:16:02) setwindow pcb -\i (00:16:02) zoom out 56.0229 57.6069 -\i (00:16:02) trapsize 177 -\i (00:16:02) zoom out 1 -\i (00:16:02) setwindow pcb -\i (00:16:02) zoom out 56.0193 57.5962 -\i (00:16:02) trapsize 353 -\i (00:16:03) zoom out 1 -\i (00:16:03) setwindow pcb -\i (00:16:03) zoom out 55.9628 57.5186 -\i (00:16:03) trapsize 707 -\i (00:16:03) zoom out 1 -\i (00:16:03) setwindow pcb -\i (00:16:03) zoom out 55.9064 57.4620 -\i (00:16:03) trapsize 1413 -\i (00:16:03) zoom out 1 -\i (00:16:03) setwindow pcb -\i (00:16:03) zoom out 55.1150 54.0421 -\i (00:16:03) trapsize 2826 -\i (00:16:04) zoom out 1 -\i (00:16:04) setwindow pcb -\i (00:16:04) zoom out 50.5927 52.9680 -\i (00:16:04) trapsize 5653 -\i (00:16:04) zoom out 1 -\i (00:16:04) setwindow pcb -\i (00:16:04) zoom out 50.1404 52.5158 -\i (00:16:04) trapsize 11306 -\i (00:16:04) zoom out 1 -\i (00:16:04) setwindow pcb -\i (00:16:04) zoom out 28.2075 28.7740 -\i (00:16:04) trapsize 22611 -\i (00:16:04) zoom out 1 -\i (00:16:04) setwindow pcb -\i (00:16:04) zoom out 22.7809 22.8951 -\i (00:16:04) trapsize 45222 -\i (00:16:04) zoom out 1 -\i (00:16:04) setwindow pcb -\i (00:16:04) zoom out 108.9274 10.2329 -\i (00:16:04) trapsize 90445 -\i (00:16:05) zoom in 1 -\i (00:16:05) setwindow pcb -\i (00:16:05) zoom in -18.5997 28.4315 -\i (00:16:05) trapsize 45222 -\i (00:16:05) zoom in 1 -\i (00:16:05) setwindow pcb -\i (00:16:05) zoom in -18.5997 28.4316 -\i (00:16:05) trapsize 22611 -\i (00:16:05) zoom in 1 -\i (00:16:05) setwindow pcb -\i (00:16:05) zoom in -18.5996 28.4316 -\i (00:16:05) trapsize 11306 -\i (00:16:05) zoom in 1 -\i (00:16:05) setwindow pcb -\i (00:16:05) zoom in -18.5996 28.4316 -\i (00:16:05) trapsize 5653 -\i (00:16:05) zoom in 1 -\i (00:16:05) setwindow pcb -\i (00:16:05) zoom in 7.9686 29.4492 -\i (00:16:05) trapsize 2826 -\i (00:16:06) zoom out 1 -\i (00:16:06) setwindow pcb -\i (00:16:06) zoom out 13.8475 31.0320 -\i (00:16:06) trapsize 5653 -\i (00:16:07) drag_start grid 36.0065 29.7884 -\i (00:16:07) drag_stop 32.3887 39.7373 -\i (00:16:08) drag_start grid -18.0342 33.1801 -\i (00:16:08) drag_stop -15.9992 47.0860 -\i (00:16:09) zoom in 1 -\i (00:16:09) setwindow pcb -\i (00:16:09) zoom in 35.1021 20.4048 -\i (00:16:09) trapsize 2826 -\i (00:16:09) zoom in 1 -\i (00:16:09) setwindow pcb -\i (00:16:09) zoom in 35.1021 20.4048 -\i (00:16:09) trapsize 1413 -\i (00:16:09) zoom in 1 -\i (00:16:09) setwindow pcb -\i (00:16:09) zoom in 35.1304 20.8005 -\i (00:16:09) trapsize 707 -\i (00:16:09) zoom in 1 -\i (00:16:09) setwindow pcb -\i (00:16:09) zoom in 35.2717 21.7756 -\i (00:16:09) trapsize 353 -\i (00:16:09) zoom in 1 -\i (00:16:09) setwindow pcb -\i (00:16:09) zoom in 35.2718 21.7756 -\i (00:16:09) trapsize 177 -\i (00:16:10) zoom out 1 -\i (00:16:10) setwindow pcb -\i (00:16:10) zoom out 35.3107 22.9026 -\i (00:16:10) trapsize 353 -\i (00:16:10) zoom out 1 -\i (00:16:10) setwindow pcb -\i (00:16:10) zoom out 35.2895 22.8956 -\i (00:16:10) trapsize 707 -\i (00:16:10) zoom in 1 -\i (00:16:10) setwindow pcb -\i (00:16:10) zoom in 37.1408 24.2805 -\i (00:16:10) trapsize 353 -\i (00:16:10) zoom in 1 -\i (00:16:10) setwindow pcb -\i (00:16:10) zoom in 37.1408 24.2805 -\i (00:16:10) trapsize 177 -\i (00:16:11) zoom in 1 -\i (00:16:11) setwindow pcb -\i (00:16:11) zoom in 36.2081 23.8848 -\i (00:16:11) trapsize 88 -\i (00:16:13) zoom out 1 -\i (00:16:13) setwindow pcb -\i (00:16:13) zoom out 36.3495 23.8407 -\i (00:16:13) trapsize 177 -\i (00:16:15) zoom out 1 -\i (00:16:15) setwindow pcb -\i (00:16:15) zoom out 36.3353 23.7559 -\i (00:16:15) trapsize 353 -\i (00:16:15) zoom out 1 -\i (00:16:15) setwindow pcb -\i (00:16:15) zoom out 36.3353 23.7559 -\i (00:16:15) trapsize 707 -\i (00:16:15) zoom out 1 -\i (00:16:15) setwindow pcb -\i (00:16:15) zoom out 35.9679 24.7876 -\i (00:16:15) trapsize 1413 -\i (00:16:16) zoom out 1 -\i (00:16:16) setwindow pcb -\i (00:16:16) zoom out 33.8199 27.5009 -\i (00:16:16) trapsize 2826 -\i (00:16:17) zoom in 1 -\i (00:16:17) setwindow pcb -\i (00:16:17) zoom in 34.9505 36.9411 -\i (00:16:17) trapsize 1413 -\i (00:16:17) zoom in 1 -\i (00:16:17) setwindow pcb -\i (00:16:17) zoom in 35.1766 36.7715 -\i (00:16:17) trapsize 707 -\i (00:16:17) zoom out 1 -\i (00:16:17) setwindow pcb -\i (00:16:17) zoom out 35.3038 32.6026 -\i (00:16:17) trapsize 1413 -\i (00:16:17) zoom out 1 -\i (00:16:17) setwindow pcb -\i (00:16:17) zoom out 35.3038 32.5178 -\i (00:16:17) trapsize 2826 -\i (00:16:18) zoom in 1 -\i (00:16:18) setwindow pcb -\i (00:16:18) zoom in 34.0037 22.1731 -\i (00:16:18) trapsize 1413 -\i (00:16:18) zoom in 1 -\i (00:16:18) setwindow pcb -\i (00:16:18) zoom in 34.2864 23.6994 -\i (00:16:18) trapsize 707 -\i (00:16:19) zoom in 1 -\i (00:16:19) setwindow pcb -\i (00:16:19) zoom in 34.3429 23.9256 -\i (00:16:19) trapsize 353 -\i (00:16:19) zoom out 1 -\i (00:16:19) setwindow pcb -\i (00:16:19) zoom out 31.8557 23.7631 -\i (00:16:19) trapsize 707 -\i (00:16:20) zoom out 1 -\i (00:16:20) setwindow pcb -\i (00:16:20) zoom out 31.9829 25.1621 -\i (00:16:20) trapsize 1413 -\i (00:16:20) zoom out 1 -\i (00:16:20) setwindow pcb -\i (00:16:20) zoom out 32.3787 25.3034 -\i (00:16:20) trapsize 2826 -\i (00:16:27) zoom out 1 -\i (00:16:27) setwindow pcb -\i (00:16:27) zoom out 40.4056 12.6977 -\i (00:16:27) trapsize 5653 -\i (00:16:27) zoom out 1 -\i (00:16:27) setwindow pcb -\i (00:16:27) zoom out 51.1460 15.9763 -\i (00:16:27) trapsize 11306 -\i (00:16:28) zoom in 1 -\i (00:16:28) setwindow pcb -\i (00:16:28) zoom in 19.9424 21.8553 -\i (00:16:28) trapsize 5653 -\i (00:16:28) zoom in 1 -\i (00:16:28) setwindow pcb -\i (00:16:28) zoom in 24.6908 21.8553 -\i (00:16:28) trapsize 2826 -\i (00:16:29) zoom in 1 -\i (00:16:29) setwindow pcb -\i (00:16:29) zoom in 29.9479 17.0505 -\i (00:16:29) trapsize 1413 -\i (00:16:30) zoom in 1 -\i (00:16:30) setwindow pcb -\i (00:16:30) zoom in 25.9910 17.3614 -\i (00:16:30) trapsize 707 -\i (00:16:30) zoom in 1 -\i (00:16:30) setwindow pcb -\i (00:16:30) zoom in 26.4997 17.6441 -\i (00:16:30) trapsize 353 -\i (00:16:31) zoom out 1 -\i (00:16:31) setwindow pcb -\i (00:16:31) zoom out 25.3692 18.3012 -\i (00:16:31) trapsize 707 -\i (00:16:32) zoom out 1 -\i (00:16:32) setwindow pcb -\i (00:16:32) zoom out 27.5737 18.0045 -\i (00:16:32) trapsize 1413 -\i (00:16:33) zoom out 1 -\i (00:16:33) setwindow pcb -\i (00:16:33) zoom out 34.6680 17.9196 -\i (00:16:33) trapsize 2826 -\i (00:16:33) zoom out 1 -\i (00:16:33) setwindow pcb -\i (00:16:33) zoom out 34.6680 17.9197 -\i (00:16:33) trapsize 5653 -\i (00:16:34) zoom in 1 -\i (00:16:34) setwindow pcb -\i (00:16:34) zoom in 19.2924 23.1202 -\i (00:16:34) trapsize 2826 -\i (00:16:35) zoom in 1 -\i (00:16:35) setwindow pcb -\i (00:16:35) zoom in 19.2924 23.1768 -\i (00:16:35) trapsize 1413 -\i (00:16:35) zoom out 1 -\i (00:16:35) setwindow pcb -\i (00:16:35) zoom out 20.4230 23.3747 -\i (00:16:35) trapsize 2826 -\i (00:16:36) zoom in 1 -\i (00:16:36) setwindow pcb -\i (00:16:36) zoom in 36.9291 24.2791 -\i (00:16:36) trapsize 1413 -\i (00:16:36) zoom in 1 -\i (00:16:36) setwindow pcb -\i (00:16:36) zoom in 36.9291 24.2508 -\i (00:16:36) trapsize 707 -\i (00:16:47) zoom out 1 -\i (00:16:47) setwindow pcb -\i (00:16:47) zoom out 37.7205 24.2650 -\i (00:16:47) trapsize 1413 -\i (00:16:48) zoom out 1 -\i (00:16:48) setwindow pcb -\i (00:16:48) zoom out 37.4096 25.5369 -\i (00:16:48) trapsize 2826 -\i (00:16:53) zoom in 1 -\i (00:16:53) setwindow pcb -\i (00:16:53) zoom in 34.6963 23.6715 -\i (00:16:53) trapsize 1413 -\i (00:16:53) zoom in 1 -\i (00:16:53) setwindow pcb -\i (00:16:53) zoom in 34.6963 23.6715 -\i (00:16:53) trapsize 707 -\i (00:16:54) zoom in 1 -\i (00:16:54) setwindow pcb -\i (00:16:54) zoom in 34.8659 23.6856 -\i (00:16:54) trapsize 353 -\i (00:18:46) zoom out 1 -\i (00:18:46) setwindow pcb -\i (00:18:46) zoom out 33.3609 23.1274 -\i (00:18:46) trapsize 707 -\i (00:18:46) zoom out 1 -\i (00:18:46) setwindow pcb -\i (00:18:46) zoom out 33.2337 23.1133 -\i (00:18:46) trapsize 1413 -\i (00:18:46) zoom out 1 -\i (00:18:46) setwindow pcb -\i (00:18:46) zoom out 33.0359 23.0002 -\i (00:18:46) trapsize 2826 -\i (00:18:47) zoom out 1 -\i (00:18:47) setwindow pcb -\i (00:18:47) zoom out 32.8662 24.0176 -\i (00:18:47) trapsize 5653 -\i (00:18:47) zoom out 1 -\i (00:18:47) setwindow pcb -\i (00:18:47) zoom out 32.8663 24.0177 -\i (00:18:47) trapsize 11306 -\i (00:18:47) zoom out 1 -\i (00:18:47) setwindow pcb -\i (00:18:47) zoom out 32.8662 24.0177 -\i (00:18:47) trapsize 22611 -\i (00:18:47) zoom in 1 -\i (00:18:47) setwindow pcb -\i (00:18:47) zoom in -37.5931 84.6156 -\i (00:18:47) trapsize 11306 -\i (00:18:47) zoom in 1 -\i (00:18:47) setwindow pcb -\i (00:18:47) zoom in -14.0774 83.2590 -\i (00:18:47) trapsize 5653 -\i (00:18:47) zoom in 1 -\i (00:18:47) setwindow pcb -\i (00:18:47) zoom in -5.5982 83.4851 -\i (00:18:47) trapsize 2826 -\i (00:18:48) zoom in 1 -\i (00:18:48) setwindow pcb -\i (00:18:48) zoom in 32.5017 85.5202 -\i (00:18:48) trapsize 1413 -\i (00:18:48) zoom in 1 -\i (00:18:48) setwindow pcb -\i (00:18:48) zoom in 26.2836 85.1811 -\i (00:18:48) trapsize 707 -\i (00:18:48) zoom out 1 -\i (00:18:48) setwindow pcb -\i (00:18:48) zoom out 22.3408 86.5661 -\i (00:18:48) trapsize 1413 -\i (00:18:49) zoom out 1 -\i (00:18:49) setwindow pcb -\i (00:18:49) zoom out 20.1928 87.4988 -\i (00:18:49) trapsize 2826 -\i (00:18:49) zoom out 1 -\i (00:18:49) setwindow pcb -\i (00:18:49) zoom out 20.1928 87.4987 -\i (00:18:49) trapsize 5653 -\i (00:18:50) zoom in 1 -\i (00:18:50) setwindow pcb -\i (00:18:50) zoom in 16.8012 94.9604 -\i (00:18:50) trapsize 2826 -\i (00:18:50) zoom in 1 -\i (00:18:50) setwindow pcb -\i (00:18:50) zoom in 16.8012 94.9604 -\i (00:18:50) trapsize 1413 -\i (00:18:51) zoom in 1 -\i (00:18:51) setwindow pcb -\i (00:18:51) zoom in 18.1296 92.1906 -\i (00:18:51) trapsize 707 -\i (00:18:51) zoom in 1 -\i (00:18:51) setwindow pcb -\i (00:18:51) zoom in 18.1014 92.1623 -\i (00:18:51) trapsize 353 -\i (00:18:52) zoom out 1 -\i (00:18:52) setwindow pcb -\i (00:18:52) zoom out 19.1260 91.2367 -\i (00:18:52) trapsize 707 -\i (00:28:15) zoom out 1 -\i (00:28:15) setwindow pcb -\i (00:28:15) zoom out 20.6240 92.1411 -\i (00:28:15) trapsize 1413 -\i (00:28:15) zoom out 1 -\i (00:28:15) setwindow pcb -\i (00:28:15) zoom out 20.1718 91.5193 -\i (00:28:15) trapsize 2826 -\i (00:28:15) zoom out 1 -\i (00:28:15) setwindow pcb -\i (00:28:15) zoom out 23.4504 89.6538 -\i (00:28:15) trapsize 5653 -\i (00:28:15) zoom out 1 -\i (00:28:15) setwindow pcb -\i (00:28:15) zoom out 23.5635 88.9756 -\i (00:28:15) trapsize 11306 -\i (00:28:16) zoom in 1 -\i (00:28:16) setwindow pcb -\i (00:28:16) zoom in 60.3133 82.1922 -\i (00:28:16) trapsize 5653 -\i (00:28:17) zoom in 1 -\i (00:28:17) setwindow pcb -\i (00:28:17) zoom in 8.9860 87.2797 -\i (00:28:17) trapsize 2826 -\i (00:28:17) zoom in 1 -\i (00:28:17) setwindow pcb -\i (00:28:17) zoom in 7.3467 86.9405 -\i (00:28:17) trapsize 1413 -\i (00:28:17) zoom in 1 -\i (00:28:17) setwindow pcb -\i (00:28:17) zoom in 7.3468 87.0254 -\i (00:28:17) trapsize 707 -\i (00:28:19) zoom out 1 -\i (00:28:19) setwindow pcb -\i (00:28:19) zoom out 7.5164 87.1526 -\i (00:28:19) trapsize 1413 -\i (00:28:20) zoom in 1 -\i (00:28:20) setwindow pcb -\i (00:28:20) zoom in 13.3105 90.0638 -\i (00:28:20) trapsize 707 -\i (00:28:21) zoom in 1 -\i (00:28:21) setwindow pcb -\i (00:28:21) zoom in 15.6989 89.1028 -\i (00:28:21) trapsize 353 -\i (00:28:23) zoom out 1 -\i (00:28:23) setwindow pcb -\i (00:28:23) zoom out 15.5505 88.9545 -\i (00:28:23) trapsize 707 -\i (00:28:23) zoom in 1 -\i (00:28:23) setwindow pcb -\i (00:28:23) zoom in 15.5505 88.9545 -\i (00:28:23) trapsize 353 -\i (00:28:24) zoom in 1 -\i (00:28:24) setwindow pcb -\i (00:28:24) zoom in 15.5505 88.9545 -\i (00:28:24) trapsize 177 -\i (00:28:25) zoom out 1 -\i (00:28:25) setwindow pcb -\i (00:28:25) zoom out 15.5505 88.9545 -\i (00:28:25) trapsize 353 -\i (00:28:26) zoom in 1 -\i (00:28:26) setwindow pcb -\i (00:28:26) zoom in 13.1763 89.3573 -\i (00:28:26) trapsize 177 -\i (00:28:26) zoom out 1 -\i (00:28:26) setwindow pcb -\i (00:28:26) zoom out 12.7170 89.4456 -\i (00:28:26) trapsize 353 -\i (00:28:26) zoom in 1 -\i (00:28:26) setwindow pcb -\i (00:28:26) zoom in 12.7170 89.4457 -\i (00:28:26) trapsize 177 -\i (00:28:26) zoom in 1 -\i (00:28:26) setwindow pcb -\i (00:28:26) zoom in 12.7170 89.4457 -\i (00:28:26) trapsize 88 -\i (00:28:27) zoom out 1 -\i (00:28:27) setwindow pcb -\i (00:28:27) zoom out 12.7170 89.4457 -\i (00:28:27) trapsize 177 -\i (00:28:28) zoom in 1 -\i (00:28:28) setwindow pcb -\i (00:28:28) zoom in 12.7170 89.4457 -\i (00:28:28) trapsize 88 -\i (00:28:28) zoom out 1 -\i (00:28:28) setwindow pcb -\i (00:28:28) zoom out 12.7170 89.4457 -\i (00:28:28) trapsize 177 -\i (00:28:28) zoom out 1 -\i (00:28:28) setwindow pcb -\i (00:28:28) zoom out 12.7170 89.4422 -\i (00:28:28) trapsize 353 -\i (00:28:29) zoom out 1 -\i (00:28:29) setwindow pcb -\i (00:28:29) zoom out 12.7170 89.4069 -\i (00:28:29) trapsize 707 -\i (00:28:29) zoom out 1 -\i (00:28:29) setwindow pcb -\i (00:28:29) zoom out 12.6747 89.0960 -\i (00:28:29) trapsize 1413 -\i (00:28:29) zoom out 1 -\i (00:28:29) setwindow pcb -\i (00:28:29) zoom out 12.5334 88.5307 -\i (00:28:29) trapsize 2826 -\i (00:28:29) zoom out 1 -\i (00:28:29) setwindow pcb -\i (00:28:29) zoom out 12.5334 87.2871 -\i (00:28:29) trapsize 5653 -\i (00:28:29) zoom out 1 -\i (00:28:29) setwindow pcb -\i (00:28:29) zoom out 18.6384 82.4257 -\i (00:28:29) trapsize 11306 -\i (00:28:29) zoom out 1 -\i (00:28:29) setwindow pcb -\i (00:28:29) zoom out 19.5427 74.9640 -\i (00:28:29) trapsize 22611 -\i (00:28:30) zoom in 1 -\i (00:28:30) setwindow pcb -\i (00:28:30) zoom in -8.9474 10.7482 -\i (00:28:30) trapsize 11306 -\i (00:28:30) zoom in 1 -\i (00:28:30) setwindow pcb -\i (00:28:30) zoom in -8.9474 10.7482 -\i (00:28:30) trapsize 5653 -\i (00:36:11) zoom in 1 -\i (00:36:11) setwindow pcb -\i (00:36:11) zoom in 5.1846 56.7619 -\i (00:36:11) trapsize 2826 -\i (00:36:11) zoom in 1 -\i (00:36:11) setwindow pcb -\i (00:36:11) zoom in 5.1846 56.7620 -\i (00:36:11) trapsize 1413 -\i (00:36:11) zoom in 1 -\i (00:36:11) setwindow pcb -\i (00:36:11) zoom in 5.1847 56.7620 -\i (00:36:11) trapsize 707 -\i (00:36:11) zoom in 1 -\i (00:36:11) setwindow pcb -\i (00:36:11) zoom in 10.1733 56.5641 -\i (00:36:11) trapsize 353 -\i (00:38:18) zoom out 1 -\i (00:38:18) setwindow pcb -\i (00:38:18) zoom out 9.2759 56.6489 -\i (00:38:18) trapsize 707 -\i (00:38:18) zoom out 1 -\i (00:38:18) setwindow pcb -\i (00:38:18) zoom out 9.2619 56.5359 -\i (00:38:18) trapsize 1413 -\i (00:38:18) zoom out 1 -\i (00:38:18) setwindow pcb -\i (00:38:18) zoom out 9.1488 56.3945 -\i (00:38:18) trapsize 2826 -\i (00:38:18) zoom out 1 -\i (00:38:18) setwindow pcb -\i (00:38:18) zoom out 9.1488 56.2815 -\i (00:38:18) trapsize 5653 -\i (00:38:18) zoom out 1 -\i (00:38:18) setwindow pcb -\i (00:38:18) zoom out 9.1488 56.2815 -\i (00:38:18) trapsize 11306 -\i (00:38:19) zoom out 1 -\i (00:38:19) setwindow pcb -\i (00:38:19) zoom out 14.5754 75.0488 -\i (00:38:19) trapsize 22611 -\i (00:38:19) zoom out 1 -\i (00:38:19) setwindow pcb -\i (00:38:19) zoom out 116.1630 183.0921 -\i (00:38:19) trapsize 45222 -\i (00:38:19) zoom out 1 -\i (00:38:19) setwindow pcb -\i (00:38:19) zoom out 336.8482 449.9041 -\i (00:38:19) trapsize 90445 -\i (00:38:20) zoom in 1 -\i (00:38:20) setwindow pcb -\i (00:38:20) zoom in -31.2620 98.9785 -\i (00:38:20) trapsize 45222 -\i (00:38:21) zoom in 1 -\i (00:38:21) setwindow pcb -\i (00:38:21) zoom in -33.0709 67.3229 -\i (00:38:21) trapsize 22611 -\i (00:38:21) zoom in 1 -\i (00:38:21) setwindow pcb -\i (00:38:21) zoom in -33.0708 67.3229 -\i (00:38:21) trapsize 11306 -\i (00:38:22) zoom in 1 -\i (00:38:22) setwindow pcb -\i (00:38:22) zoom in 27.7533 89.2557 -\i (00:38:22) trapsize 5653 -\i (00:38:22) zoom in 1 -\i (00:38:22) setwindow pcb -\i (00:38:22) zoom in 25.9445 88.6904 -\i (00:38:22) trapsize 2826 -\i (00:38:22) zoom out 1 -\i (00:38:22) setwindow pcb -\i (00:38:22) zoom out 25.4923 87.6730 -\i (00:38:22) trapsize 5653 -\i (00:38:23) zoom in 1 -\i (00:38:23) setwindow pcb -\i (00:38:23) zoom in 47.6512 90.7254 -\i (00:38:23) trapsize 2826 -\i (00:38:23) zoom in 1 -\i (00:38:23) setwindow pcb -\i (00:38:23) zoom in 51.5517 91.8560 -\i (00:38:23) trapsize 1413 -\i (00:38:23) zoom in 1 -\i (00:38:23) setwindow pcb -\i (00:38:23) zoom in 51.5517 91.8843 -\i (00:38:23) trapsize 707 -\i (00:38:24) zoom out 1 -\i (00:38:24) setwindow pcb -\i (00:38:24) zoom out 50.3082 91.2908 -\i (00:38:24) trapsize 1413 -\i (00:38:24) zoom out 1 -\i (00:38:24) setwindow pcb -\i (00:38:24) zoom out 50.2233 91.1777 -\i (00:38:24) trapsize 2826 -\i (00:38:25) zoom out 1 -\i (00:38:25) setwindow pcb -\i (00:38:25) zoom out 31.5126 88.5773 -\i (00:38:25) trapsize 5653 -\i (00:38:25) zoom out 1 -\i (00:38:25) setwindow pcb -\i (00:38:25) zoom out 20.4331 90.7254 -\i (00:38:25) trapsize 11306 -\i (00:38:26) zoom out 1 -\i (00:38:26) setwindow pcb -\i (00:38:26) zoom out 20.4329 88.0121 -\i (00:38:26) trapsize 22611 -\i (00:38:26) zoom out 1 -\i (00:38:26) setwindow pcb -\i (00:38:26) zoom out 20.4329 87.5599 -\i (00:38:26) trapsize 45222 -\i (00:38:26) zoom out 1 -\i (00:38:26) setwindow pcb -\i (00:38:26) zoom out 20.4329 87.5600 -\i (00:38:26) trapsize 90445 -\i (00:40:54) zoom in 1 -\i (00:40:54) setwindow pcb -\i (00:40:54) zoom in -15.7449 26.6227 -\i (00:40:54) trapsize 45222 -\i (00:40:54) zoom in 1 -\i (00:40:54) setwindow pcb -\i (00:40:54) zoom in -14.8405 26.6227 -\i (00:40:54) trapsize 22611 -\i (00:40:54) zoom in 1 -\i (00:40:54) setwindow pcb -\i (00:40:54) zoom in -14.3882 26.6228 -\i (00:40:54) trapsize 11306 -\i (00:40:54) zoom in 1 -\i (00:40:54) setwindow pcb -\i (00:40:54) zoom in -1.0476 49.0079 -\i (00:40:54) trapsize 5653 -\i (00:40:54) zoom in 1 -\i (00:40:54) setwindow pcb -\i (00:40:54) zoom in -1.0476 49.0079 -\i (00:40:54) trapsize 2826 -\i (00:40:55) zoom in 1 -\i (00:40:55) setwindow pcb -\i (00:40:55) zoom in 3.2486 55.5086 -\i (00:40:55) trapsize 1413 -\i (00:40:55) zoom out 1 -\i (00:40:55) setwindow pcb -\i (00:40:55) zoom out 5.3119 60.3983 -\i (00:40:55) trapsize 2826 -\i (00:40:55) zoom out 1 -\i (00:40:55) setwindow pcb -\i (00:40:55) zoom out 5.3119 60.3984 -\i (00:40:55) trapsize 5653 -\i (00:41:09) zoom in 1 -\i (00:41:09) setwindow pcb -\i (00:41:09) zoom in 11.1909 65.1467 -\i (00:41:09) trapsize 2826 -\i (00:41:10) zoom in 1 -\i (00:41:10) setwindow pcb -\i (00:41:10) zoom in 11.1909 65.1467 -\i (00:41:10) trapsize 1413 -\i (00:41:10) zoom in 1 -\i (00:41:10) setwindow pcb -\i (00:41:10) zoom in 9.4668 65.0619 -\i (00:41:10) trapsize 707 -\i (00:41:11) zoom in 1 -\i (00:41:11) setwindow pcb -\i (00:41:11) zoom in 9.2407 65.7686 -\i (00:41:11) trapsize 353 -\i (00:41:11) zoom in 1 -\i (00:41:11) setwindow pcb -\i (00:41:11) zoom in 11.2050 65.3093 -\i (00:41:11) trapsize 177 -\i (00:41:12) zoom out 1 -\i (00:41:12) setwindow pcb -\i (00:41:12) zoom out 11.3923 65.2528 -\i (00:41:12) trapsize 353 -\i (00:41:14) drag_start grid 10.7352 65.2246 -\i (00:41:14) drag_stop 10.9754 65.2246 -\i (00:41:14) zoom out 1 -\i (00:41:14) setwindow pcb -\i (00:41:14) zoom out 11.1521 65.1398 -\i (00:41:14) trapsize 707 -\i (00:41:15) zoom in 1 -\i (00:41:15) setwindow pcb -\i (00:41:15) zoom in 5.8809 65.5638 -\i (00:41:15) trapsize 353 -\i (00:41:16) zoom in 1 -\i (00:41:16) setwindow pcb -\i (00:41:16) zoom in 9.8166 65.4719 -\i (00:41:16) trapsize 177 -\i (00:43:11) zoom out 1 -\i (00:43:11) setwindow pcb -\i (00:43:11) zoom out 9.3291 65.8005 -\i (00:43:11) trapsize 353 -\i (00:52:31) zoom out 1 -\i (00:52:31) setwindow pcb -\i (00:52:31) zoom out 9.2655 65.2070 -\i (00:52:31) trapsize 707 -\i (00:52:31) zoom out 1 -\i (00:52:31) setwindow pcb -\i (00:52:31) zoom out 9.1525 65.0940 -\i (00:52:31) trapsize 1413 -\i (00:52:31) zoom in 1 -\i (00:52:31) setwindow pcb -\i (00:52:31) zoom in 8.4177 64.5571 -\i (00:52:31) trapsize 707 -\i (00:52:31) zoom out 1 -\i (00:52:31) setwindow pcb -\i (00:52:31) zoom out 8.3612 64.5147 -\i (00:52:31) trapsize 1413 -\i (00:52:32) zoom out 1 -\i (00:52:32) setwindow pcb -\i (00:52:32) zoom out 8.1068 62.5646 -\i (00:52:32) trapsize 2826 -\i (00:52:32) zoom out 1 -\i (00:52:32) setwindow pcb -\i (00:52:32) zoom out 9.4069 62.4515 -\i (00:52:32) trapsize 5653 -\i (00:52:32) zoom out 1 -\i (00:52:32) setwindow pcb -\i (00:52:32) zoom out 9.8591 63.0167 -\i (00:52:32) trapsize 11306 -\i (00:52:32) zoom out 1 -\i (00:52:32) setwindow pcb -\i (00:52:32) zoom out 25.7182 70.0262 -\i (00:52:32) trapsize 22611 -\i (00:52:32) zoom in 1 -\i (00:52:32) setwindow pcb -\i (00:52:32) zoom in 154.1498 87.2206 -\i (00:52:32) trapsize 11306 -\i (00:52:33) zoom out 1 -\i (00:52:33) setwindow pcb -\i (00:52:33) zoom out 38.3805 78.8545 -\i (00:52:33) trapsize 22611 -\i (00:52:33) zoom out 1 -\i (00:52:33) setwindow pcb -\i (00:52:33) zoom out 38.3805 77.4978 -\i (00:52:33) trapsize 45222 -\i (00:52:33) zoom out 1 -\i (00:52:33) setwindow pcb -\i (00:52:33) zoom out 38.3805 238.2634 -\i (00:52:33) trapsize 90445 -\i (00:52:34) zoom in 1 -\i (00:52:34) setwindow pcb -\i (00:52:34) zoom in -24.9309 60.9917 -\i (00:52:34) trapsize 45222 -\i (00:52:34) zoom in 1 -\i (00:52:34) setwindow pcb -\i (00:52:34) zoom in -14.9820 107.1186 -\i (00:52:34) trapsize 22611 -\i (00:52:34) zoom in 1 -\i (00:52:34) setwindow pcb -\i (00:52:34) zoom in -15.8864 102.1442 -\i (00:52:34) trapsize 11306 -\i (00:52:34) zoom in 1 -\i (00:52:34) setwindow pcb -\i (00:52:34) zoom in -15.8864 100.3353 -\i (00:52:34) trapsize 5653 -\i (00:52:35) zoom out 1 -\i (00:52:35) setwindow pcb -\i (00:52:35) zoom out 18.7087 95.4740 -\i (00:52:35) trapsize 11306 -\i (00:52:35) zoom out 1 -\i (00:52:35) setwindow pcb -\i (00:52:35) zoom out 18.0304 95.0217 -\i (00:52:35) trapsize 22611 -\i (00:52:35) zoom in 1 -\i (00:52:35) setwindow pcb -\i (00:52:35) zoom in 6.7248 77.8372 -\i (00:52:35) trapsize 11306 -\i (00:52:35) zoom in 1 -\i (00:52:35) setwindow pcb -\i (00:52:35) zoom in 6.7248 78.0634 -\i (00:52:35) trapsize 5653 -\i (00:52:36) zoom in 1 -\i (00:52:36) setwindow pcb -\i (00:52:36) zoom in 12.4906 83.9423 -\i (00:52:36) trapsize 2826 -\i (00:52:36) zoom in 1 -\i (00:52:36) setwindow pcb -\i (00:52:36) zoom in 12.4906 83.9989 -\i (00:52:36) trapsize 1413 -\i (00:52:36) zoom in 1 -\i (00:52:36) setwindow pcb -\i (00:52:36) zoom in 17.6630 88.6342 -\i (00:52:36) trapsize 707 -\i (00:52:59) zoom out 1 -\i (00:52:59) setwindow pcb -\i (00:52:59) zoom out 27.9229 89.8354 -\i (00:52:59) trapsize 1413 -\i (00:52:59) zoom out 1 -\i (00:52:59) setwindow pcb -\i (00:52:59) zoom out 26.4814 89.3549 -\i (00:52:59) trapsize 2826 -\i (00:52:59) zoom out 1 -\i (00:52:59) setwindow pcb -\i (00:52:59) zoom out 20.1502 91.7291 -\i (00:52:59) trapsize 5653 -\i (00:52:59) zoom out 1 -\i (00:52:59) setwindow pcb -\i (00:52:59) zoom out 20.6024 80.4236 -\i (00:52:59) trapsize 11306 -\i (00:53:03) zoom in 1 -\i (00:53:03) setwindow pcb -\i (00:53:03) zoom in -5.7113 94.6686 -\i (00:53:03) trapsize 5653 -\i (00:53:03) zoom in 1 -\i (00:53:03) setwindow pcb -\i (00:53:03) zoom in -5.5982 93.8772 -\i (00:53:03) trapsize 2826 -\i (00:53:04) zoom in 1 -\i (00:53:04) setwindow pcb -\i (00:53:04) zoom in 21.0830 90.2594 -\i (00:53:04) trapsize 1413 -\i (00:53:04) zoom in 1 -\i (00:53:04) setwindow pcb -\i (00:53:04) zoom in 21.3092 90.4573 -\i (00:53:04) trapsize 707 -\i (00:53:05) zoom in 1 -\i (00:53:05) setwindow pcb -\i (00:53:05) zoom in 24.7857 90.1464 -\i (00:53:05) trapsize 353 -\i (00:53:05) zoom out 1 -\i (00:53:05) setwindow pcb -\i (00:53:05) zoom out 24.7291 90.1252 -\i (00:53:05) trapsize 707 -\i (00:53:05) zoom out 1 -\i (00:53:05) setwindow pcb -\i (00:53:05) zoom out 24.7292 90.1253 -\i (00:53:05) trapsize 1413 -\i (00:53:06) zoom in 1 -\i (00:53:06) setwindow pcb -\i (00:53:06) zoom in 27.0469 90.1535 -\i (00:53:06) trapsize 707 -\i (00:53:07) zoom out 1 -\i (00:53:07) setwindow pcb -\i (00:53:07) zoom out 27.3437 90.3090 -\i (00:53:07) trapsize 1413 -\i (00:53:07) zoom out 1 -\i (00:53:07) setwindow pcb -\i (00:53:07) zoom out 27.6829 89.4610 -\i (00:53:07) trapsize 2826 -\i (00:53:08) zoom in 1 -\i (00:53:08) setwindow pcb -\i (00:53:08) zoom in 27.6830 89.4610 -\i (00:53:08) trapsize 1413 -\i (00:53:08) zoom in 1 -\i (00:53:08) setwindow pcb -\i (00:53:08) zoom in 27.7113 89.4610 -\i (00:53:08) trapsize 707 -\i (00:53:09) zoom out 1 -\i (00:53:09) setwindow pcb -\i (00:53:09) zoom out 27.0189 89.6730 -\i (00:53:09) trapsize 1413 -\i (00:53:09) zoom out 1 -\i (00:53:09) setwindow pcb -\i (00:53:09) zoom out 27.0189 89.6730 -\i (00:53:09) trapsize 2826 -\i (00:53:10) zoom out 1 -\i (00:53:10) setwindow pcb -\i (00:53:10) zoom out 29.3365 87.6379 -\i (00:53:10) trapsize 5653 -\i (00:53:11) zoom in 1 -\i (00:53:11) setwindow pcb -\i (00:53:11) zoom in 40.0763 88.3163 -\i (00:53:11) trapsize 2826 -\i (00:53:11) zoom in 1 -\i (00:53:11) setwindow pcb -\i (00:53:11) zoom in 37.3065 88.6555 -\i (00:53:11) trapsize 1413 -\i (00:53:11) zoom in 1 -\i (00:53:11) setwindow pcb -\i (00:53:11) zoom in 33.8583 89.6165 -\i (00:53:11) trapsize 707 -\i (00:53:13) zoom in 1 -\i (00:53:13) setwindow pcb -\i (00:53:13) zoom in 32.2756 90.1111 -\i (00:53:13) trapsize 353 -\i (00:53:13) zoom out 1 -\i (00:53:13) setwindow pcb -\i (00:53:13) zoom out 32.7702 89.9556 -\i (00:53:13) trapsize 707 -\i (00:53:14) zoom out 1 -\i (00:53:14) setwindow pcb -\i (00:53:14) zoom out 34.6922 90.2666 -\i (00:53:14) trapsize 1413 -\i (00:53:15) zoom out 1 -\i (00:53:15) setwindow pcb -\i (00:53:15) zoom out 36.8402 89.6731 -\i (00:53:15) trapsize 2826 -\i (00:53:16) zoom in 1 -\i (00:53:16) setwindow pcb -\i (00:53:16) zoom in 40.4015 89.1078 -\i (00:53:16) trapsize 1413 -\i (00:53:16) zoom in 1 -\i (00:53:16) setwindow pcb -\i (00:53:16) zoom in 40.4015 89.1079 -\i (00:53:16) trapsize 707 -\i (00:53:16) zoom in 1 -\i (00:53:16) setwindow pcb -\i (00:53:16) zoom in 40.4015 89.1079 -\i (00:53:16) trapsize 353 -\i (00:53:17) zoom out 1 -\i (00:53:17) setwindow pcb -\i (00:53:17) zoom out 40.0765 89.1927 -\i (00:53:17) trapsize 707 -\i (01:06:24) zoom out 1 -\i (01:06:24) setwindow pcb -\i (01:06:24) zoom out 36.0631 89.7722 -\i (01:06:24) trapsize 1413 -\i (01:06:24) zoom in 1 -\i (01:06:24) setwindow pcb -\i (01:06:24) zoom in 36.0348 89.7440 -\i (01:06:24) trapsize 707 -\i (01:06:24) zoom out 1 -\i (01:06:24) setwindow pcb -\i (01:06:24) zoom out 35.9924 89.6875 -\i (01:06:24) trapsize 1413 -\i (01:06:24) zoom out 1 -\i (01:06:24) setwindow pcb -\i (01:06:24) zoom out 35.5120 89.0374 -\i (01:06:24) trapsize 2826 -\i (01:06:24) zoom out 1 -\i (01:06:24) setwindow pcb -\i (01:06:24) zoom out 35.5120 89.0373 -\i (01:06:24) trapsize 5653 -\i (01:06:24) zoom out 1 -\i (01:06:24) setwindow pcb -\i (01:06:24) zoom out 23.9802 95.5946 -\i (01:06:24) trapsize 11306 -\i (01:06:24) zoom out 1 -\i (01:06:24) setwindow pcb -\i (01:06:24) zoom out 96.4912 87.0023 -\i (01:06:24) trapsize 22611 -\i (01:06:25) zoom out 1 -\i (01:06:25) setwindow pcb -\i (01:06:25) zoom out 300.6703 77.0534 -\i (01:06:25) trapsize 45222 -\i (01:06:25) zoom in 1 -\i (01:06:25) setwindow pcb -\i (01:06:25) zoom in -45.7331 36.5716 -\i (01:06:25) trapsize 22611 -\i (01:06:25) zoom in 1 -\i (01:06:25) setwindow pcb -\i (01:06:25) zoom in -44.3764 36.5716 -\i (01:06:25) trapsize 11306 -\i (01:06:26) zoom in 1 -\i (01:06:26) setwindow pcb -\i (01:06:26) zoom in -2.7718 36.3455 -\i (01:06:26) trapsize 5653 -\i (01:06:26) zoom in 1 -\i (01:06:26) setwindow pcb -\i (01:06:26) zoom in -5.3721 36.0063 -\i (01:06:26) trapsize 2826 -\i (01:06:26) zoom out 1 -\i (01:06:26) setwindow pcb -\i (01:06:26) zoom out 41.3766 42.5636 -\i (01:06:26) trapsize 5653 -\i (01:06:27) zoom in 1 -\i (01:06:27) setwindow pcb -\i (01:06:27) zoom in 58.3349 52.2863 -\i (01:06:27) trapsize 2826 -\i (01:06:28) zoom in 1 -\i (01:06:28) setwindow pcb -\i (01:06:28) zoom in 58.6176 55.5084 -\i (01:06:28) trapsize 1413 -\i (01:06:28) zoom in 1 -\i (01:06:28) setwindow pcb -\i (01:06:28) zoom in 58.8438 57.0065 -\i (01:06:28) trapsize 707 -\i (01:06:30) zoom in 1 -\i (01:06:30) setwindow pcb -\i (01:06:30) zoom in 54.3923 57.5576 -\i (01:06:30) trapsize 353 -\i (01:06:31) zoom in 1 -\i (01:06:31) setwindow pcb -\i (01:06:31) zoom in 54.1591 57.7131 -\i (01:06:31) trapsize 177 -\i (01:06:31) zoom out 1 -\i (01:06:31) setwindow pcb -\i (01:06:31) zoom out 54.1910 57.7167 -\i (01:06:31) trapsize 353 -\i (01:06:31) zoom out 1 -\i (01:06:31) setwindow pcb -\i (01:06:31) zoom out 54.1838 57.7025 -\i (01:06:31) trapsize 707 -\i (01:06:31) zoom out 1 -\i (01:06:31) setwindow pcb -\i (01:06:31) zoom out 54.1698 57.5895 -\i (01:06:31) trapsize 1413 -\i (01:06:32) zoom in 1 -\i (01:06:32) setwindow pcb -\i (01:06:32) zoom in 60.2466 57.7592 -\i (01:06:32) trapsize 707 -\i (01:06:32) zoom in 1 -\i (01:06:32) setwindow pcb -\i (01:06:32) zoom in 60.9956 58.0560 -\i (01:06:32) trapsize 353 -\i (01:06:32) zoom out 1 -\i (01:06:32) setwindow pcb -\i (01:06:32) zoom out 60.6281 57.6603 -\i (01:06:32) trapsize 707 -\i (01:06:32) zoom out 1 -\i (01:06:32) setwindow pcb -\i (01:06:32) zoom out 60.5858 57.4907 -\i (01:06:32) trapsize 1413 -\i (01:06:33) zoom out 1 -\i (01:06:33) setwindow pcb -\i (01:06:33) zoom out 59.0596 56.9255 -\i (01:06:33) trapsize 2826 -\i (01:06:33) zoom out 1 -\i (01:06:33) setwindow pcb -\i (01:06:33) zoom out 58.7770 56.3602 -\i (01:06:33) trapsize 5653 -\i (01:06:37) zoom out 1 -\i (01:06:37) setwindow pcb -\i (01:06:37) zoom out 72.2307 30.9226 -\i (01:06:37) trapsize 11306 -\i (01:06:37) zoom out 1 -\i (01:06:37) setwindow pcb -\i (01:06:37) zoom out 159.1242 30.9227 -\i (01:06:37) trapsize 22611 -\i (01:06:38) zoom in 1 -\i (01:06:38) setwindow pcb -\i (01:06:38) zoom in 98.0740 24.1393 -\i (01:06:38) trapsize 11306 -\i (01:06:39) zoom in 1 -\i (01:06:39) setwindow pcb -\i (01:06:39) zoom in 53.7561 22.1043 -\i (01:06:39) trapsize 5653 -\i (01:06:39) zoom in 1 -\i (01:06:39) setwindow pcb -\i (01:06:39) zoom in 53.7561 22.1043 -\i (01:06:39) trapsize 2826 -\i (01:06:40) zoom in 1 -\i (01:06:40) setwindow pcb -\i (01:06:40) zoom in 62.1788 33.0708 -\i (01:06:40) trapsize 1413 -\i (01:06:41) zoom out 1 -\i (01:06:41) setwindow pcb -\i (01:06:41) zoom out 65.7966 34.5123 -\i (01:06:41) trapsize 2826 -\i (01:06:41) zoom in 1 -\i (01:06:41) setwindow pcb -\i (01:06:41) zoom in 64.7226 42.2001 -\i (01:06:41) trapsize 1413 -\i (01:06:41) zoom in 1 -\i (01:06:41) setwindow pcb -\i (01:06:41) zoom in 66.4750 42.9915 -\i (01:06:41) trapsize 707 -\i (01:10:08) zoom out 1 -\i (01:10:08) setwindow pcb -\i (01:10:08) zoom out 63.0692 39.9814 -\i (01:10:08) trapsize 1413 -\i (01:10:08) zoom out 1 -\i (01:10:08) setwindow pcb -\i (01:10:08) zoom out 62.8713 39.9248 -\i (01:10:08) trapsize 2826 -\i (01:10:09) zoom out 1 -\i (01:10:09) setwindow pcb -\i (01:10:09) zoom out 49.8698 43.3165 -\i (01:10:09) trapsize 5653 -\i (01:10:09) zoom out 1 -\i (01:10:09) setwindow pcb -\i (01:10:09) zoom out 49.7568 43.3166 -\i (01:10:09) trapsize 11306 -\i (01:10:09) zoom out 1 -\i (01:10:09) setwindow pcb -\i (01:10:09) zoom out 49.7568 43.3166 -\i (01:10:09) trapsize 22611 -\i (01:10:09) zoom out 1 -\i (01:10:09) setwindow pcb -\i (01:10:09) zoom out 49.3045 101.2396 -\i (01:10:09) trapsize 45222 -\i (01:10:10) zoom in 1 -\i (01:10:10) setwindow pcb -\i (01:10:10) zoom in -13.1023 85.4117 -\i (01:10:10) trapsize 22611 -\i (01:10:10) zoom in 1 -\i (01:10:10) setwindow pcb -\i (01:10:10) zoom in -13.1023 85.4118 -\i (01:10:10) trapsize 11306 -\i (01:10:11) zoom in 1 -\i (01:10:11) setwindow pcb -\i (01:10:11) zoom in -1.5705 90.8385 -\i (01:10:11) trapsize 5653 -\i (01:10:11) zoom in 1 -\i (01:10:11) setwindow pcb -\i (01:10:11) zoom in -2.0227 90.6124 -\i (01:10:11) trapsize 2826 -\i (01:10:11) zoom in 1 -\i (01:10:11) setwindow pcb -\i (01:10:11) zoom in 19.1753 88.5209 -\i (01:10:11) trapsize 1413 -\i (01:10:12) zoom in 1 -\i (01:10:12) setwindow pcb -\i (01:10:12) zoom in 13.2116 89.4819 -\i (01:10:12) trapsize 707 -\i (01:10:12) zoom in 1 -\i (01:10:12) setwindow pcb -\i (01:10:12) zoom in 14.3988 89.9483 -\i (01:10:12) trapsize 353 -\i (01:10:13) zoom out 1 -\i (01:10:13) setwindow pcb -\i (01:10:13) zoom out 14.7874 90.0049 -\i (01:10:13) trapsize 707 -\i (13:16:02) zoom out 1 -\i (13:16:02) setwindow pcb -\i (13:16:02) zoom out 20.4120 90.6549 -\i (13:16:02) trapsize 1413 -\i (13:16:02) zoom out 1 -\i (13:16:02) setwindow pcb -\i (13:16:02) zoom out 20.4403 90.5702 -\i (13:16:02) trapsize 2826 -\i (13:16:02) zoom out 1 -\i (13:16:02) setwindow pcb -\i (13:16:02) zoom out 20.4404 90.5702 -\i (13:16:02) trapsize 5653 -\i (13:16:02) zoom out 1 -\i (13:16:02) setwindow pcb -\i (13:16:02) zoom out 20.4404 90.5702 -\i (13:16:02) trapsize 11306 -\i (13:16:03) zoom out 1 -\i (13:16:03) setwindow pcb -\i (13:16:03) zoom out 61.4439 29.9723 -\i (13:16:03) trapsize 22611 -\i (13:16:04) zoom out 1 -\i (13:16:04) setwindow pcb -\i (13:16:04) zoom out 4.4637 29.0678 -\i (13:16:04) trapsize 45222 -\i (13:16:04) zoom out 1 -\i (13:16:04) setwindow pcb -\i (13:16:04) zoom out 57.3739 40.8256 -\i (13:16:04) trapsize 90445 -\i (13:16:04) zoom out 1 -\i (13:16:04) setwindow pcb -\i (13:16:04) zoom out 77.2717 55.2968 -\i (13:16:04) trapsize 180890 -\i (13:16:05) zoom in 1 -\i (13:16:05) setwindow pcb -\i (13:16:05) zoom in 23.0049 -24.0264 -\i (13:16:05) trapsize 90445 -\i (13:16:05) zoom in 1 -\i (13:16:05) setwindow pcb -\i (13:16:05) zoom in 21.1960 -24.0264 -\i (13:16:05) trapsize 45222 -\i (13:16:07) zoom out 1 -\i (13:16:07) setwindow pcb -\i (13:16:07) zoom out -5.0329 13.9604 -\i (13:16:07) trapsize 90445 -\i (13:16:08) zoom in 1 -\i (13:16:08) setwindow pcb -\i (13:16:08) zoom in -8.6507 50.1383 -\i (13:16:08) trapsize 45222 -\i (13:16:08) zoom in 1 -\i (13:16:08) setwindow pcb -\i (13:16:08) zoom in -8.6507 50.1383 -\i (13:16:08) trapsize 22611 -\i (13:16:09) zoom in 1 -\i (13:16:09) setwindow pcb -\i (13:16:09) zoom in -8.6507 49.2339 -\i (13:16:09) trapsize 11306 -\i (13:16:09) zoom in 1 -\i (13:16:09) setwindow pcb -\i (13:16:09) zoom in -0.2845 50.1384 -\i (13:16:09) trapsize 5653 -\i (13:16:09) zoom in 1 -\i (13:16:09) setwindow pcb -\i (13:16:09) zoom in -0.2845 50.1385 -\i (13:16:09) trapsize 2826 -\i (13:16:32) exit -\t (13:16:32) Journal end - Wed Aug 26 08:59:54 2026 +\i (00:07:57) zoom out 26.5497 91.6375 +\i (00:07:57) trapsize 4009 +\i (00:07:57) zoom out 1 +\i (00:07:57) setwindow pcb +\i (00:07:57) zoom out 29.5966 88.4301 +\i (00:07:57) trapsize 8018 +\i (00:07:57) zoom out 1 +\i (00:07:57) setwindow pcb +\i (00:07:57) zoom out 94.8445 88.4302 +\i (00:07:57) trapsize 16037 +\i (00:07:58) zoom in 1 +\i (00:07:58) setwindow pcb +\i (00:07:58) zoom in 28.6134 86.8265 +\i (00:07:58) trapsize 8018 +\i (00:07:58) zoom in 1 +\i (00:07:58) setwindow pcb +\i (00:07:58) zoom in 39.8390 91.4771 +\i (00:07:58) trapsize 4009 +\i (00:07:58) zoom in 1 +\i (00:07:58) setwindow pcb +\i (00:07:58) zoom in 39.8391 91.3969 +\i (00:07:58) trapsize 2005 +\i (00:07:59) zoom in 1 +\i (00:07:59) setwindow pcb +\i (00:07:59) zoom in 38.3557 90.8757 +\i (00:07:59) trapsize 1002 +\i (00:07:59) zoom in 1 +\i (00:07:59) setwindow pcb +\i (00:07:59) zoom in 36.6719 90.9960 +\i (00:07:59) trapsize 501 +\i (00:08:03) zoom out 1 +\i (00:08:03) setwindow pcb +\i (00:08:03) zoom out 41.0920 90.8257 +\i (00:08:03) trapsize 1002 +\i (00:08:13) zoom out 1 +\i (00:08:13) setwindow pcb +\i (00:08:13) zoom out 47.9476 90.6251 +\i (00:08:13) trapsize 2005 +\i (00:08:14) zoom in 1 +\i (00:08:14) setwindow pcb +\i (00:08:14) zoom in 33.2742 88.2999 +\i (00:08:14) trapsize 1002 +\i (00:08:16) zoom out 1 +\i (00:08:16) setwindow pcb +\i (00:08:16) zoom out 20.1643 90.6653 +\i (00:08:16) trapsize 2005 +\i (00:08:16) zoom out 1 +\i (00:08:16) setwindow pcb +\i (00:08:16) zoom out 20.1241 90.6653 +\i (00:08:16) trapsize 4009 +\i (00:08:17) zoom in 1 +\i (00:08:17) setwindow pcb +\i (00:08:17) zoom in 15.1528 89.7031 +\i (00:08:17) trapsize 2005 +\i (00:08:17) zoom in 1 +\i (00:08:17) setwindow pcb +\i (00:08:17) zoom in 15.1529 89.7031 +\i (00:08:17) trapsize 1002 +\i (00:23:54) zoom out 1 +\i (00:23:54) setwindow pcb +\i (00:23:54) zoom out 36.2810 91.7077 +\i (00:23:54) trapsize 2005 +\i (00:23:55) zoom in 1 +\i (00:23:55) setwindow pcb +\i (00:23:55) zoom in 38.2858 92.3893 +\i (00:23:55) trapsize 1002 +\i (00:23:55) zoom in 1 +\i (00:23:55) setwindow pcb +\i (00:23:55) zoom in 38.2857 92.3893 +\i (00:23:55) trapsize 501 +\i (00:23:55) zoom out 1 +\i (00:23:55) setwindow pcb +\i (00:23:55) zoom out 38.8972 92.3492 +\i (00:23:55) trapsize 1002 +\i (00:23:55) zoom out 1 +\i (00:23:55) setwindow pcb +\i (00:23:55) zoom out 38.8971 92.3492 +\i (00:23:55) trapsize 2005 +\i (00:23:58) zoom out 1 +\i (00:23:58) setwindow pcb +\i (00:23:58) zoom out 39.6189 90.6253 +\i (00:23:58) trapsize 4009 +\i (00:23:58) zoom in 1 +\i (00:23:58) setwindow pcb +\i (00:23:58) zoom in 39.2180 90.0640 +\i (00:23:58) trapsize 2005 +\i (00:23:58) zoom in 1 +\i (00:23:58) setwindow pcb +\i (00:23:58) zoom in 39.2180 90.0641 +\i (00:23:58) trapsize 1002 +\i (00:23:59) zoom in 1 +\i (00:23:59) setwindow pcb +\i (00:23:59) zoom in 39.2180 90.0641 +\i (00:23:59) trapsize 501 +\i (00:24:00) zoom out 1 +\i (00:24:00) setwindow pcb +\i (00:24:00) zoom out 32.0116 89.7134 +\i (00:24:00) trapsize 1002 +\i (00:24:02) zoom out 1 +\i (00:24:02) setwindow pcb +\i (00:24:02) zoom out 23.3319 88.5707 +\i (00:24:02) trapsize 2005 +\i (00:24:02) zoom out 1 +\i (00:24:02) setwindow pcb +\i (00:24:02) zoom out 22.4498 88.2099 +\i (00:24:02) trapsize 4009 +\i (00:24:02) zoom out 1 +\i (00:24:02) setwindow pcb +\i (00:24:02) zoom out 22.3697 88.2100 +\i (00:24:02) trapsize 8018 +\i (00:24:02) zoom out 1 +\i (00:24:02) setwindow pcb +\i (00:24:02) zoom out 22.3697 88.2099 +\i (00:24:02) trapsize 16037 +\i (00:24:03) zoom in 1 +\i (00:24:03) setwindow pcb +\i (00:24:03) zoom in 23.0111 88.5306 +\i (00:24:03) trapsize 8018 +\i (00:24:03) zoom in 1 +\i (00:24:03) setwindow pcb +\i (00:24:03) zoom in 23.0111 88.5307 +\i (00:24:03) trapsize 4009 +\i (00:24:04) zoom out 1 +\i (00:24:04) setwindow pcb +\i (00:24:04) zoom out 20.8462 88.2902 +\i (00:24:04) trapsize 8018 +\i (00:24:04) zoom out 1 +\i (00:24:04) setwindow pcb +\i (00:24:04) zoom out 20.8462 88.2902 +\i (00:24:04) trapsize 16037 +\i (00:24:04) zoom out 1 +\i (00:24:04) setwindow pcb +\i (00:24:04) zoom out 17.9597 86.0450 +\i (00:24:04) trapsize 32073 +\i (00:24:04) zoom out 1 +\i (00:24:04) setwindow pcb +\i (00:24:04) zoom out 16.6768 83.4792 +\i (00:24:04) trapsize 64146 +\i (00:24:05) zoom in 1 +\i (00:24:05) setwindow pcb +\i (00:24:05) zoom in -2.5671 69.3464 +\i (00:24:05) trapsize 32073 +\i (00:24:05) zoom in 1 +\i (00:24:05) setwindow pcb +\i (00:24:05) zoom in -2.5671 69.3464 +\i (00:24:05) trapsize 16037 +\i (00:24:06) zoom in 1 +\i (00:24:06) setwindow pcb +\i (00:24:06) zoom in -0.0012 80.8927 +\i (00:24:06) trapsize 8018 +\i (00:24:06) zoom in 1 +\i (00:24:06) setwindow pcb +\i (00:24:06) zoom in -0.0011 80.8928 +\i (00:24:06) trapsize 4009 +\i (00:24:06) zoom in 1 +\i (00:24:06) setwindow pcb +\i (00:24:06) zoom in 8.4181 88.3498 +\i (00:24:06) trapsize 2005 +\i (00:24:06) zoom in 1 +\i (00:24:06) setwindow pcb +\i (00:24:06) zoom in 8.4181 88.3499 +\i (00:24:06) trapsize 1002 +\i (00:26:42) zoom out 1 +\i (00:26:42) setwindow pcb +\i (00:26:42) zoom out 12.4874 88.6506 +\i (00:26:42) trapsize 2005 +\i (00:26:43) zoom out 1 +\i (00:26:43) setwindow pcb +\i (00:26:43) zoom out 12.2870 87.2074 +\i (00:26:43) trapsize 4009 +\i (00:26:43) zoom out 1 +\i (00:26:43) setwindow pcb +\i (00:26:43) zoom out 12.2069 84.7216 +\i (00:26:43) trapsize 8018 +\i (00:26:43) zoom out 1 +\i (00:26:43) setwindow pcb +\i (00:26:43) zoom out 12.5276 82.4765 +\i (00:26:43) trapsize 16037 +\i (00:26:43) zoom in 1 +\i (00:26:43) setwindow pcb +\i (00:26:43) zoom in -19.5456 56.1766 +\i (00:26:43) trapsize 8018 +\i (00:26:43) zoom in 1 +\i (00:26:43) setwindow pcb +\i (00:26:43) zoom in -19.7060 56.1766 +\i (00:26:43) trapsize 4009 +\i (00:26:43) zoom in 1 +\i (00:26:43) setwindow pcb +\i (00:26:43) zoom in -19.7059 56.1767 +\i (00:26:43) trapsize 2005 +\i (00:26:44) zoom out 1 +\i (00:26:44) setwindow pcb +\i (00:26:44) zoom out 2.9458 64.2752 +\i (00:26:44) trapsize 4009 +\i (00:26:44) zoom in 1 +\i (00:26:44) setwindow pcb +\i (00:26:44) zoom in 2.7854 63.8743 +\i (00:26:44) trapsize 2005 +\i (00:26:44) zoom out 1 +\i (00:26:44) setwindow pcb +\i (00:26:44) zoom out 2.7854 63.8744 +\i (00:26:44) trapsize 4009 +\i (00:26:44) zoom out 1 +\i (00:26:44) setwindow pcb +\i (00:26:44) zoom out 2.7854 63.8743 +\i (00:26:44) trapsize 8018 +\i (00:26:44) zoom in 1 +\i (00:26:44) setwindow pcb +\i (00:26:44) zoom in 39.0372 93.7024 +\i (00:26:44) trapsize 4009 +\i (00:26:44) zoom in 1 +\i (00:26:44) setwindow pcb +\i (00:26:44) zoom in 34.3866 95.6268 +\i (00:26:44) trapsize 2005 +\i (00:26:44) zoom in 1 +\i (00:26:44) setwindow pcb +\i (00:26:44) zoom in 28.3328 95.3863 +\i (00:26:44) trapsize 1002 +\i (00:26:48) zoom in 1 +\i (00:26:48) setwindow pcb +\i (00:26:48) zoom in 31.0991 90.2947 +\i (00:26:48) trapsize 501 +\i (00:26:52) zoom out 1 +\i (00:26:52) setwindow pcb +\i (00:26:52) zoom out 24.5141 90.1143 +\i (00:26:52) trapsize 1002 +\i (00:26:53) zoom in 1 +\i (00:26:53) setwindow pcb +\i (00:26:53) zoom in 24.1733 91.3772 +\i (00:26:53) trapsize 501 +\i (00:26:54) zoom out 1 +\i (00:26:54) setwindow pcb +\i (00:26:54) zoom out 25.6667 91.2369 +\i (00:26:54) trapsize 1002 +\i (00:26:54) zoom out 1 +\i (00:26:54) setwindow pcb +\i (00:26:54) zoom out 25.6667 91.0967 +\i (00:26:54) trapsize 2005 +\i (00:26:55) zoom out 1 +\i (00:26:55) setwindow pcb +\i (00:26:55) zoom out 17.8489 90.8962 +\i (00:26:55) trapsize 4009 +\i (00:26:55) zoom in 1 +\i (00:26:55) setwindow pcb +\i (00:26:55) zoom in 15.8442 91.6981 +\i (00:26:55) trapsize 2005 +\i (00:26:56) zoom in 1 +\i (00:26:56) setwindow pcb +\i (00:26:56) zoom in 15.8443 91.6981 +\i (00:26:56) trapsize 1002 +\i (00:28:55) zoom out 1 +\i (00:28:55) setwindow pcb +\i (00:28:55) zoom out 24.3237 90.7159 +\i (00:28:55) trapsize 2005 +\i (00:28:55) zoom in 1 +\i (00:28:55) setwindow pcb +\i (00:28:55) zoom in 14.4612 92.3997 +\i (00:28:55) trapsize 1002 +\i (03:15:24) xrefdes K1 +\i (03:15:24) xname_flush +\i (03:15:24) trapsize 4733 +\i (03:15:26) xrefdes K3 +\i (03:15:26) xname_flush +\i (03:15:26) trapsize 4733 +\i (03:15:28) xrefdes K1 +\i (03:15:28) xname_flush +\i (03:15:28) trapsize 4733 +\i (03:15:56) xrefdes U21 +\i (03:15:56) xname_flush +\i (03:15:56) trapsize 1890 +\i (03:16:30) xNet Vbus+ +\i (03:16:30) xname_flush +\i (03:16:30) trapsize 7236 +\i (03:16:34) xNet Vbus+_Sw +\i (03:16:34) xname_flush +\i (03:16:34) trapsize 2674 +\i (03:16:38) xrefdes U5 +\i (03:16:38) xname_flush +\i (03:16:38) trapsize 2201 +\i (04:19:50) zoom out 1 +\i (04:19:50) setwindow pcb +\i (04:19:50) zoom out 28.4704 33.3770 +\i (04:19:50) trapsize 4401 +\i (04:19:50) zoom out 1 +\i (04:19:50) setwindow pcb +\i (04:19:50) zoom out 28.4704 33.3770 +\i (04:19:50) trapsize 8803 +\i (04:20:05) zoom in 1 +\i (04:20:05) setwindow pcb +\i (04:20:05) zoom in 67.9549 43.7641 +\i (04:20:05) trapsize 4401 +\i (04:20:07) zoom in 1 +\i (04:20:07) setwindow pcb +\i (04:20:07) zoom in 45.7722 39.8910 +\i (04:20:07) trapsize 2201 +\i (04:20:17) zoom out 1 +\i (04:20:17) setwindow pcb +\i (04:20:17) zoom out 51.8021 36.7661 +\i (04:20:17) trapsize 4401 +\i (04:20:18) zoom out 1 +\i (04:20:18) setwindow pcb +\i (04:20:18) zoom out 37.8939 32.3647 +\i (04:20:18) trapsize 8803 +\i (04:20:19) zoom out 1 +\i (04:20:19) setwindow pcb +\i (04:20:19) zoom out 13.0703 40.4631 +\i (04:20:19) trapsize 17605 +\i (04:20:20) zoom in 1 +\i (04:20:20) setwindow pcb +\i (04:20:20) zoom in 16.1952 5.2524 +\i (04:20:20) trapsize 8803 +\i (04:20:20) zoom in 1 +\i (04:20:20) setwindow pcb +\i (04:20:20) zoom in 15.4910 4.9004 +\i (04:20:20) trapsize 4401 +\i (04:20:22) zoom in 1 +\i (04:20:22) setwindow pcb +\i (04:20:22) zoom in 33.5365 21.7135 +\i (04:20:22) trapsize 2201 +\i (04:20:22) zoom in 1 +\i (04:20:22) setwindow pcb +\i (04:20:22) zoom in 34.5488 22.3737 +\i (04:20:22) trapsize 1100 +\i (04:20:22) zoom in 1 +\i (04:20:22) setwindow pcb +\i (04:20:22) zoom in 34.5488 22.3737 +\i (04:20:22) trapsize 550 +\i (04:20:23) zoom in 1 +\i (04:20:23) setwindow pcb +\i (04:20:23) zoom in 33.8446 23.6061 +\i (04:20:23) trapsize 275 +\i (04:20:23) zoom in 1 +\i (04:20:23) setwindow pcb +\i (04:20:23) zoom in 33.1183 23.8152 +\i (04:20:23) trapsize 138 +\i (04:20:23) zoom out 1 +\i (04:20:23) setwindow pcb +\i (04:20:23) zoom out 33.3383 23.8345 +\i (04:20:23) trapsize 275 +\i (04:20:23) zoom out 1 +\i (04:20:23) setwindow pcb +\i (04:20:23) zoom out 33.3438 23.7850 +\i (04:20:23) trapsize 550 +\i (04:20:33) zoom out 1 +\i (04:20:33) setwindow pcb +\i (04:20:33) zoom out 34.9944 23.6969 +\i (04:20:33) trapsize 1100 +\i (04:20:33) zoom out 1 +\i (04:20:33) setwindow pcb +\i (04:20:33) zoom out 35.2585 23.6970 +\i (04:20:33) trapsize 2201 +\i (04:20:34) zoom out 1 +\i (04:20:34) setwindow pcb +\i (04:20:34) zoom out 35.0825 22.9047 +\i (04:20:34) trapsize 4402 +\i (04:20:34) zoom out 1 +\i (04:20:34) setwindow pcb +\i (04:20:34) zoom out 35.0824 22.9047 +\i (04:20:34) trapsize 8803 +\i (04:20:35) zoom in 1 +\i (04:20:35) setwindow pcb +\i (04:20:35) zoom in 33.6739 48.2577 +\i (04:20:35) trapsize 4402 +\i (04:20:35) zoom in 1 +\i (04:20:35) setwindow pcb +\i (04:20:35) zoom in 36.9311 22.7287 +\i (04:20:35) trapsize 2201 +\i (04:20:35) zoom in 1 +\i (04:20:35) setwindow pcb +\i (04:20:35) zoom in 36.1389 22.1125 +\i (04:20:35) trapsize 1100 +\i (04:20:36) zoom in 1 +\i (04:20:36) setwindow pcb +\i (04:20:36) zoom in 31.9134 24.1592 +\i (04:20:36) trapsize 550 +\i (04:20:36) zoom in 1 +\i (04:20:36) setwindow pcb +\i (04:20:36) zoom in 31.9134 24.1592 +\i (04:20:36) trapsize 275 +\i (04:20:37) zoom out 1 +\i (04:20:37) setwindow pcb +\i (04:20:37) zoom out 34.8459 23.5815 +\i (04:20:37) trapsize 550 +\i (04:20:38) zoom in 1 +\i (04:20:38) setwindow pcb +\i (04:20:38) zoom in 36.3204 23.2514 +\i (04:20:38) trapsize 275 +\i (04:20:40) zoom out 1 +\i (04:20:40) setwindow pcb +\i (04:20:40) zoom out 35.9188 23.9722 +\i (04:20:40) trapsize 550 +\i (04:20:41) zoom out 1 +\i (04:20:41) setwindow pcb +\i (04:20:41) zoom out 37.6905 23.9502 +\i (04:20:41) trapsize 1100 +\i (04:20:41) zoom in 1 +\i (04:20:41) setwindow pcb +\i (04:20:41) zoom in 39.2309 23.4440 +\i (04:20:41) trapsize 550 +\i (04:20:42) zoom in 1 +\i (04:20:42) setwindow pcb +\i (04:20:42) zoom in 38.5377 23.6861 +\i (04:20:42) trapsize 275 +\i (04:20:42) zoom in 1 +\i (04:20:42) setwindow pcb +\i (04:20:42) zoom in 38.5377 23.6861 +\i (04:20:42) trapsize 138 +\i (04:20:43) zoom out 1 +\i (04:20:43) setwindow pcb +\i (04:20:43) zoom out 38.2736 23.7027 +\i (04:20:43) trapsize 275 +\i (04:20:45) zoom out 1 +\i (04:20:45) setwindow pcb +\i (04:20:45) zoom out 35.2366 23.8787 +\i (04:20:45) trapsize 550 +\i (04:20:46) zoom out 1 +\i (04:20:46) setwindow pcb +\i (04:20:46) zoom out 36.1169 24.6599 +\i (04:20:46) trapsize 1100 +\i (04:20:46) zoom out 1 +\i (04:20:46) setwindow pcb +\i (04:20:46) zoom out 36.1169 24.5499 +\i (04:20:46) trapsize 2201 +\i (04:20:46) zoom out 1 +\i (04:20:46) setwindow pcb +\i (04:20:46) zoom out 36.6011 24.6819 +\i (04:20:46) trapsize 4402 +\i (04:20:47) zoom out 1 +\i (04:20:47) setwindow pcb +\i (04:20:47) zoom out 35.1925 31.9005 +\i (04:20:47) trapsize 8803 +\i (04:20:47) zoom in 1 +\i (04:20:47) setwindow pcb +\i (04:20:47) zoom in 32.9036 29.6117 +\i (04:20:47) trapsize 4402 +\i (04:20:47) zoom out 1 +\i (04:20:47) setwindow pcb +\i (04:20:47) zoom out 32.7276 30.4920 +\i (04:20:47) trapsize 8803 +\i (04:20:47) zoom out 1 +\i (04:20:47) setwindow pcb +\i (04:20:47) zoom out 32.5515 30.4920 +\i (04:20:47) trapsize 17606 +\i (04:20:48) zoom in 1 +\i (04:20:48) setwindow pcb +\i (04:20:48) zoom in 18.3135 52.8216 +\i (04:20:48) trapsize 8803 +\i (04:20:48) zoom in 1 +\i (04:20:48) setwindow pcb +\i (04:20:48) zoom in 18.3135 52.8216 +\i (04:20:48) trapsize 4402 +\i (04:20:49) zoom in 1 +\i (04:20:49) setwindow pcb +\i (04:20:49) zoom in 34.3352 20.6903 +\i (04:20:49) trapsize 2201 +\i (04:20:50) zoom in 1 +\i (04:20:50) setwindow pcb +\i (04:20:50) zoom in 32.7506 19.7220 +\i (04:20:50) trapsize 1100 +\i (04:20:50) zoom in 1 +\i (04:20:50) setwindow pcb +\i (04:20:50) zoom in 33.0587 21.2626 +\i (04:20:50) trapsize 550 +\i (04:20:50) zoom in 1 +\i (04:20:50) setwindow pcb +\i (04:20:50) zoom in 33.0587 21.2626 +\i (04:20:50) trapsize 275 +\i (04:20:51) zoom out 1 +\i (04:20:51) setwindow pcb +\i (04:20:51) zoom out 33.0587 23.3203 +\i (04:20:51) trapsize 550 +\i (04:20:55) zoom in 1 +\i (04:20:55) setwindow pcb +\i (04:20:55) zoom in 34.3352 23.7385 +\i (04:20:55) trapsize 275 +\i (04:20:56) drag_start grid 34.3023 23.7275 +\i (04:20:56) zoom in 1 +\i (04:20:56) setwindow pcb +\i (04:20:56) zoom in 34.3408 23.0673 +\i (04:20:56) trapsize 138 +\i (04:20:56) drag_stop 34.3573 22.9353 +\i (04:20:57) zoom out 1 +\i (04:20:57) setwindow pcb +\i (04:20:57) zoom out 34.3436 22.9793 +\i (04:20:57) trapsize 275 +\i (04:20:57) zoom out 1 +\i (04:20:57) setwindow pcb +\i (04:20:57) zoom out 34.3436 22.9793 +\i (04:20:57) trapsize 550 +\i (04:20:57) zoom out 1 +\i (04:20:57) setwindow pcb +\i (04:20:57) zoom out 34.3545 22.9353 +\i (04:20:57) trapsize 1100 +\i (04:20:57) zoom in 1 +\i (04:20:57) setwindow pcb +\i (04:20:57) zoom in 33.4742 26.5226 +\i (04:20:57) trapsize 550 +\i (04:20:58) zoom in 1 +\i (04:20:58) setwindow pcb +\i (04:20:58) zoom in 34.8717 23.7717 +\i (04:20:58) trapsize 275 +\i (04:21:36) help +\i (04:22:22) zoom out 1 +\i (04:22:22) setwindow pcb +\i (04:22:22) zoom out 36.1042 24.5970 +\i (04:22:22) trapsize 550 +\i (04:22:22) zoom out 1 +\i (04:22:22) setwindow pcb +\i (04:22:22) zoom out 36.1041 24.5090 +\i (04:22:22) trapsize 1100 +\i (04:22:22) zoom out 1 +\i (04:22:22) setwindow pcb +\i (04:22:22) zoom out 36.1701 24.3990 +\i (04:22:22) trapsize 2201 +\i (04:22:22) zoom out 1 +\i (04:22:22) setwindow pcb +\i (04:22:22) zoom out 37.1825 23.6948 +\i (04:22:22) trapsize 4402 +\i (04:22:22) zoom out 1 +\i (04:22:22) setwindow pcb +\i (04:22:22) zoom out 46.2497 31.2655 +\i (04:22:22) trapsize 8803 +\i (04:22:22) zoom out 1 +\i (04:22:22) setwindow pcb +\i (04:22:22) zoom out 85.7451 31.2656 +\i (04:22:22) trapsize 17606 +\i (04:22:23) zoom in 1 +\i (04:22:23) setwindow pcb +\i (04:22:23) zoom in 13.7359 82.0478 +\i (04:22:23) trapsize 8803 +\i (04:22:26) zoom in 1 +\i (04:22:26) setwindow pcb +\i (04:22:26) zoom in 33.2788 57.5752 +\i (04:22:26) trapsize 4402 +\i (04:22:26) zoom in 1 +\i (04:22:26) setwindow pcb +\i (04:22:26) zoom in 33.2788 57.5753 +\i (04:22:26) trapsize 2201 +\i (04:22:27) zoom out 1 +\i (04:22:27) setwindow pcb +\i (04:22:27) zoom out 36.7560 59.1599 +\i (04:22:27) trapsize 4402 +\i (04:22:27) zoom out 1 +\i (04:22:27) setwindow pcb +\i (04:22:27) zoom out 36.7559 59.1599 +\i (04:22:27) trapsize 8803 +\i (04:22:27) zoom in 1 +\i (04:22:27) setwindow pcb +\i (04:22:27) zoom in 2.7760 75.0054 +\i (04:22:27) trapsize 4402 +\i (04:22:32) zoom out 1 +\i (04:22:32) setwindow pcb +\i (04:22:32) zoom out 69.6795 77.9985 +\i (04:22:32) trapsize 8803 +\i (04:22:34) zoom in 1 +\i (04:22:34) setwindow pcb +\i (04:22:34) zoom in 73.5968 80.6394 +\i (04:22:34) trapsize 4402 +\i (04:22:34) zoom in 1 +\i (04:22:34) setwindow pcb +\i (04:22:34) zoom in 73.5968 80.6395 +\i (04:22:34) trapsize 2201 +\i (04:22:34) zoom in 1 +\i (04:22:34) setwindow pcb +\i (04:22:34) zoom in 71.6601 81.1677 +\i (04:22:34) trapsize 1100 +\i (04:22:35) zoom in 1 +\i (04:22:35) setwindow pcb +\i (04:22:35) zoom in 72.6285 80.9257 +\i (04:22:35) trapsize 550 +\i (04:22:35) zoom in 1 +\i (04:22:35) setwindow pcb +\i (04:22:35) zoom in 72.6285 80.9257 +\i (04:22:35) trapsize 275 +\i (04:23:52) zoom out 1 +\i (04:23:52) setwindow pcb +\i (04:23:52) zoom out 70.3892 79.9464 +\i (04:23:52) trapsize 550 +\i (04:23:55) zoom in 1 +\i (04:23:55) setwindow pcb +\i (04:23:55) zoom in 66.5489 80.1885 +\i (04:23:55) trapsize 275 +\i (04:23:55) zoom in 1 +\i (04:23:55) setwindow pcb +\i (04:23:55) zoom in 66.0538 80.2106 +\i (04:23:55) trapsize 138 +\i (04:23:55) zoom in 1 +\i (04:23:55) setwindow pcb +\i (04:23:55) zoom in 66.0538 80.2106 +\i (04:23:55) trapsize 69 +\i (04:23:55) zoom out 1 +\i (04:23:55) setwindow pcb +\i (04:23:55) zoom out 66.1597 80.2492 +\i (04:23:55) trapsize 138 +\i (04:23:55) zoom out 1 +\i (04:23:55) setwindow pcb +\i (04:23:55) zoom out 66.1597 80.2492 +\i (04:23:55) trapsize 275 +\i (04:23:56) zoom out 1 +\i (04:23:56) setwindow pcb +\i (04:23:56) zoom out 66.5283 80.3812 +\i (04:23:56) trapsize 550 +\i (04:23:58) zoom in 1 +\i (04:23:58) setwindow pcb +\i (04:23:58) zoom in 71.8655 80.6564 +\i (04:23:58) trapsize 275 +\i (04:23:59) zoom out 1 +\i (04:23:59) setwindow pcb +\i (04:23:59) zoom out 71.7500 80.5023 +\i (04:23:59) trapsize 550 +\i (04:28:30) zoom out 1 +\i (04:28:30) setwindow pcb +\i (04:28:30) zoom out 73.0154 79.4459 +\i (04:28:30) trapsize 1100 +\i (04:28:31) zoom out 1 +\i (04:28:31) setwindow pcb +\i (04:28:31) zoom out 72.3551 79.1158 +\i (04:28:31) trapsize 2201 +\i (04:28:31) zoom in 1 +\i (04:28:31) setwindow pcb +\i (04:28:31) zoom in 70.6824 76.9588 +\i (04:28:31) trapsize 1100 +\i (04:28:31) zoom out 1 +\i (04:28:31) setwindow pcb +\i (04:28:31) zoom out 70.0882 77.3990 +\i (04:28:31) trapsize 2201 +\i (04:28:31) zoom out 1 +\i (04:28:31) setwindow pcb +\i (04:28:31) zoom out 69.7801 77.3990 +\i (04:28:31) trapsize 4402 +\i (04:28:31) zoom out 1 +\i (04:28:31) setwindow pcb +\i (04:28:31) zoom out 55.2541 77.8392 +\i (04:28:31) trapsize 8804 +\i (04:28:31) zoom out 1 +\i (04:28:31) setwindow pcb +\i (04:28:31) zoom out 54.1977 69.5637 +\i (04:28:31) trapsize 17607 +\i (04:28:31) zoom out 1 +\i (04:28:31) setwindow pcb +\i (04:28:31) zoom out 108.1170 57.9431 +\i (04:28:31) trapsize 35214 +\i (04:28:31) zoom out 1 +\i (04:28:31) setwindow pcb +\i (04:28:31) zoom out 319.7555 52.1262 +\i (04:28:31) trapsize 70429 +\i (04:28:46) xdehilite +\i (04:28:46) xrefdes U5 +\i (04:28:46) xname_flush +\i (04:28:46) done +\i (04:28:46) generaledit +\i (04:29:34) xNet Pb10_Usart3_Tx +\i (04:29:34) xname_flush +\i (04:29:34) trapsize 710 +\i (04:39:25) xNet Pb9 +\i (04:39:25) xname_flush +\i (04:39:25) trapsize 580 +\i (04:42:22) xNet Pb10_Usart3_Tx +\i (04:42:22) xname_flush +\i (04:42:22) trapsize 710 +\i (04:42:36) xNet N3579505 +\i (04:42:36) xname_flush +\i (04:42:36) trapsize 137 +\i (04:43:09) xNet N3579545 +\i (04:43:09) xname_flush +\i (04:43:09) trapsize 290 +\i (04:43:17) xNet N3579545 +\i (04:43:17) xname_flush +\i (04:43:17) trapsize 290 +\i (04:43:23) xNet Pa9_Usart1_Tx +\i (04:43:23) xname_flush +\i (04:43:23) trapsize 2757 +\i (06:32:33) exit +\e (06:32:33) Do you want to save the changes you made to HC_DFCD_Protocol_V3_0.brd? +\i (06:32:34) fillin yes +\t (06:32:34) Journal end - Wed Aug 26 17:53:03 2026 diff --git a/docs/修改日志.md b/docs/修改日志.md index 469c7b1..150bb0f 100644 --- a/docs/修改日志.md +++ b/docs/修改日志.md @@ -1,5 +1,57 @@ # 修改日志 +## V1.1.23 - 2026-09-11 + +### 负载初始化继电器时序调整 + +- 负载初始化先单独下发辅助继电器 `FU_REL_ON (0x01 0x02)`。 +- 只有收到匹配回码后，等待 `30ms` 才打开北向负载继电器。 +- 北向继电器打开后，再继续下发电流、模式、V_On等初始化参数。 +- 辅助继电器回码失败时只重发当前初始化阶段，不提前打开北向继电器。 +- 协议板版本号更新为 `V1.1.23`，固件版本寄存器更新为 `0x0127`。 + +### 待验证 + +- 上电初始化日志中确认先收到 `01 02`，约30ms后才出现北向继电器打开。 +- 辅助继电器无回码时确认北向继电器保持关闭。 + +## V1.1.22 - 2026-09-11 + +### 增加纹波滤波调试打印 + +- 记录每个通道主继电器闭合的 tick 和忽略帧配置。 +- 打印忽略帧的序号、原始纹波值及继电器闭合后的经过时间。 +- 打印实际进入滤波的帧序号、原始值、滤波值及经过时间。 +- 协议板版本号更新为 `V1.1.22`，固件版本寄存器更新为 `0x0126`。 +- 待验证：确认宏调整后忽略帧数量和实际进入滤波的时间同步变化。 + +## V1.1.21 - 2026-09-11 + +### 继电器切换纹波滤波 + +- 主继电器闭合回码成功后，忽略 `RIPPLE_RELAY_IGNORE_P1_COUNT` 个新P1采样帧；当前值为 `2U`，可在 `chrg_north.h` 中调整。 +- 后续纹波持续使用三点中值滤波，滤除单帧尖峰；连续异常纹波仍会正常显示。 +- LCD和上位机纹波寄存器统一使用滤波后的纹波值。 +- 协议板版本号更新为 `V1.1.21`，固件版本寄存器更新为 `0x0125`。 + +### 验证记录 + +- 待硬件验证：继电器闭合瞬间出现约500mV尖峰时，LCD和上位机不显示该尖峰；忽略2帧后再累计3帧并更新为稳定纹波。 +- 待硬件验证：持续三帧以上的高纹波仍能在LCD和上位机显示。 + +## V1.1.20 - 2026-09-10 + +### D+/D-上位机显示单位修正 + +- 上位机读取各通道 `D+`、`D-` 保持寄存器时，返回值由内部原始值放大 `10` 倍，适配上位机按 `0.001V` 解析。 +- LCD显示、北向回码解析及内部控制值保持原有 `0.01V` 单位，不受影响。 +- 增加16位寄存器上限保护，放大结果超过 `65535` 时返回 `65535`。 +- 协议板版本号更新为 `V1.1.20`，固件版本寄存器更新为 `0x0124`。 + +### 验证记录 + +- 待硬件验证：D+或D-内部值为 `260` 时，LCD继续显示 `2.60V`，上位机读取值为 `2600` 并显示 `2.600V`。 + ## V1.1.19 - 2026-09-10 ### 短路测试绕过 V_ON 门槛 diff --git a/docs/协议板Boot_UPK打包规则.md b/docs/协议板Boot_UPK打包规则.md index 2829092..faed8d6 100644 --- a/docs/协议板Boot_UPK打包规则.md +++ b/docs/协议板Boot_UPK打包规则.md @@ -20,6 +20,21 @@ - 上位机必须从偏移 0 开始以 `STX/1024` 发送；第一个 STX 是头区，真正 body 从第二个 STX 开始。 - YMODEM 最后一帧的 `0x1A` 补齐仅属于传输层，不能计入文件大小、`raw_size` 或 `pkg_size`。 +### YMODEM 1K 帧字节数 + +`STX/1024` 中的 `1024` 指数据区长度，不是串口线上完整帧长度。每个完整 STX 数据帧固定为 **1029 字节**： + +```text +STX 1 字节 +PacketNo 1 字节 +~PacketNo 1 字节 +Data 1024 字节 +CRC16 2 字节 +总计 1029 字节 +``` + +因此，UPK 首数据块和后续固件数据块的有效数据均为 1024 字节，实际串口发送时均应连续发送 1029 字节。YMODEM 元数据使用 SOH 帧，完整帧为 133 字节（128 字节数据区 + 5 字节控制/校验字段）。 + 界面中的“表头尺寸 `1024 (ymodem1k)`”应改名为“YMODEM 首数据块/头区尺寸”，并固定为 1024；UPK 逻辑头固定为 96，不能让用户修改。 ## 3. 输入、分区与版本 diff --git a/docs/协议板Boot_YMODEM上位机实现规则.md b/docs/协议板Boot_YMODEM上位机实现规则.md index 47da7b4..df0a561 100644 --- a/docs/协议板Boot_YMODEM上位机实现规则.md +++ b/docs/协议板Boot_YMODEM上位机实现规则.md @@ -56,8 +56,8 @@ CRC 覆盖 `Data` 的全部固定长度字节（128 或 1024），并按 **高 1. 元数据包必须使用 `SOH`，`PacketNo=0x00`，反码为 `0xFF`。 2. 首个文件数据包使用 `PacketNo=0x01`；每得到 ACK 后序号加 1，按 8 位自然回绕。 3. 本 Boot 的 `.upk` 使用 1K 首数据块布局，因此文件数据包必须使用 `STX`（1024 字节）；最后一包不足 1024 字节时仍应补齐到 1024 字节，建议补 `0x1A`。 -4. Boot 校验包号、包号反码、帧长度与 CRC。任一校验失败会回复 NAK。 -5. 收到 NAK 时，必须重发**原完整帧**，包号不得递增。该 Boot 不将“前一帧重复包”当作成功帧，因此不能依赖重复包自动 ACK。 +4. Boot 校验包号、包号反码、帧长度与 CRC。任一校验失败会立即回复 NAK；当前 Boot 随后会重置 YMODEM 包号和流程。 +5. 对于业务层处理失败产生的 NAK，可以重发**原完整帧**，包号不得递增。对于 CRC、包号或帧长度错误产生的 NAK，不能只重发当前帧，必须重新进入 Boot 并从元数据包开始完整传输。 ## 5. 元数据包规则 @@ -171,7 +171,7 @@ WAIT_END_ACK | 事件 | 上位机处理 | | --- | --- | | 收到 ACK | 仅推进到下一协议状态；数据包 ACK 后才递增包号 | -| 收到明确 NAK | 重发当前完整帧；建议最多连续 3 次 | +| 收到明确 NAK | 业务层 NAK 可重发当前完整帧；协议校验 NAK 应重新进入 Boot，从元数据包开始传输 | | 等待 ACK 超时 | 标记“传输结果不确定”，停止本次会话；重新进入 Boot 后从元数据包开始完整传输 | | 明确 NAK 重发耗尽 | 发送 CAN 两次，标记升级传输失败 | | 收到 CAN | 立即停止，标记 Boot 取消升级 | @@ -180,7 +180,7 @@ WAIT_END_ACK Boot 对单个 CAN 会进入取消流程并回 ACK；上位机仍建议按标准发送两个 CAN，并接受可能出现的 ACK。 -> **当前 Boot 的可靠性限制：** 成功接收一个数据包后，Boot 已把期望包号加一；若该包的 ACK 在串口上丢失，上位机重发同一包会被 Boot 判为“重复包”并回复 NAK，而不是再次回复 ACK。因此“ACK 超时后无条件重发当前包”不能可靠恢复。本文规则可在直连、稳定的串口环境中正常升级；若要支持 ACK 丢失后的可靠自动重发，需要修改 Boot，使其收到“期望包号减一”的重复帧且 CRC 正确时直接回复 ACK、不再次写入数据。 +> **当前 Boot 的可靠性限制：** 成功接收一个数据包后，Boot 已把期望包号加一；若该包的 ACK 在串口上丢失，上位机重发同一包会被 Boot 判为“重复包”并回复 NAK，同时触发 YMODEM 重置。因此“ACK 超时后无条件重发当前包”不能可靠恢复，必须重新进入 Boot 并从元数据包开始传输。若要支持当前会话内的可靠自动重发，需要修改 Boot，使其保留期望包号，并对 CRC 正确的重复帧直接回复 ACK、不再次写入数据。 `WAIT_*_ACK` 的建议超时为 3～10 秒，元数据后的 `WAIT_C_DATA`、结束阶段的 `WAIT_C_END` 建议为 10 秒。上位机可将串口接收设计为持续缓存并按字节解析，忽略调试文本或仅识别 `C/ACK/NAK/CAN` 控制字符，避免因分段到达造成误判。 From 8327cb3500d0f534e6890ace313997ba8070c5d4 Mon Sep 17 00:00:00 2001 From: wrh Date: Tue, 15 Sep 2026 20:51:50 +0800 Subject: [PATCH 4/4] =?UTF-8?q?=E5=BD=93=E5=89=8D=E7=89=88=E6=9C=AC?= =?UTF-8?q?=E5=AD=98=E5=9C=A8=E5=81=B6=E7=84=B6=E6=80=A7=E5=A4=B1=E8=B4=A5?= =?UTF-8?q?=E2=80=94=E2=80=94=E7=94=B5=E5=8E=8B=E5=88=B0=E4=BA=86=E4=B9=8B?= =?UTF-8?q?=E5=90=8E=E6=B2=A1=E7=94=B5=E6=B5=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1. apps/chrg/applications/thread/chrg_north.h: 更新版本号到V1.1.22 2. apps/chrg/applications/utils/chrg_eload.c: 清理冗余注释和调试打印代码 3. apps/chrg/applications/thread/chrg_comm.c: 更新版本号到V1.1.24，重构测试模式切换逻辑，新增优先级命令处理 4. apps/chrg/applications/thread/chrg_roll_sou.c: 新增优先级命令调度逻辑，优先处理测试停止/切换命令 5. apps/chrg/applications/utils/chrg_sink.c: 更新版本号到V1.1.24，重构初始化命令构建流程，新增初始化状态跟踪，增加调试打印开关 6. docs/Allegro.jrl和docs/allegro.jrl,1: 更新Allegro设计日志文件 --- apps/chrg/applications/thread/chrg_comm.c | 35 +- apps/chrg/applications/thread/chrg_north.h | 2 +- apps/chrg/applications/thread/chrg_roll_sou.c | 54 +- apps/chrg/applications/utils/chrg_eload.c | 18 +- apps/chrg/applications/utils/chrg_sink.c | 85 +- docs/Allegro.jrl | 144 +-- docs/allegro.jrl,1 | 1050 ++--------------- 7 files changed, 286 insertions(+), 1102 deletions(-) diff --git a/apps/chrg/applications/thread/chrg_comm.c b/apps/chrg/applications/thread/chrg_comm.c index b54d2bf..bc33f69 100644 --- a/apps/chrg/applications/thread/chrg_comm.c +++ b/apps/chrg/applications/thread/chrg_comm.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_comm.c 完成日期 : -当前版本号 : V1.1.23 +当前版本号 : V1.1.24 主要功能 : 实现对外通讯协议 MODBUS 服务端，以独立线程等待处理响应请求数据。 版本历史 : 创建原始版本 说明 : @@ -2571,6 +2571,7 @@ static eMBException chrg_comm_apply_sink_effect(rt_uint8_t ch, rt_uint16_t old_loadc = pReal->sink.loadc; rt_uint8_t old_on_work = pReal->sink.On_work; rt_uint8_t old_work_mode = pReal->sink.work_mode; + rt_bool_t old_test_or_load_active; rt_uint16_t sink_work = pShadow->sink.Now_State; chrg_param_diff_t diff_info; @@ -2610,9 +2611,31 @@ static eMBException chrg_comm_apply_sink_effect(rt_uint8_t ch, if (sink_work == 0x01) { curr_test = pReal->sink.test.test_mode; curr_test_old = pReal->sink.test.test_mode_old; - if (((curr_test_old == 0) && (curr_test != 0)) || - ((curr_test == 0) && (curr_test_old != 0))) { - if (curr_test_old == 0) { + old_test_or_load_active = (old_on_work == 1U) && + ((old_work_mode == SINK_WORK_RUNING) || + (old_work_mode == SINK_WORK_LOAD_STANDBY) || + (old_work_mode == SINK_WORK_ON_TEST_SHORT) || + (old_work_mode == SINK_WORK_ON_TEST_DYNA) || + (old_work_mode == SINK_WORK_ON_TEST_OCP)); + if (curr_test != curr_test_old) { + /* 测试模式切换优先清理旧批次，防止旧WORK_START插入新测试。 */ + if (chrg_sou_com_batch_cancel((eIDX_SOU_CH)ch) != 0) { + return MB_EX_SLAVE_BUSY; + } + if (curr_test == 0) { + /* Protocol-before-CC test flow is disabled in this version. */ + pReal->sub = IDX_SET_SINK_CC_BEFORE_PD; + pReal->sink.work_mode = SINK_WORK_INIT; + } else { + /* 普通负载或旧测试运行时，先停止电子负载再启动新测试。 */ + if (old_test_or_load_active) { + rt_uint16_t stop_reg = REG_WORK; + rt_uint16_t stop_val = WORK_STOP; + if (chrg_sou_com_batch_submit((eIDX_SOU_CH)ch, + &stop_reg, &stop_val, 1U) != 0) { + return MB_EX_SLAVE_BUSY; + } + } if (curr_test == SINK_TEST_DYNA) { pReal->sink.work_mode = SINK_WORK_ON_TEST_DYNA; } else if (curr_test == SINK_TEST_OCP) { @@ -2621,10 +2644,6 @@ static eMBException chrg_comm_apply_sink_effect(rt_uint8_t ch, pReal->sink.work_mode = SINK_WORK_ON_TEST_SHORT; } pReal->sink.test.test_mode_old = curr_test; - } else { - /* Protocol-before-CC test flow is disabled in this version. */ - pReal->sub = IDX_SET_SINK_CC_BEFORE_PD; - pReal->sink.work_mode = SINK_WORK_INIT; } } else if (pReal->sink.On_work == 0) { pReal->sink.On_work = 1; diff --git a/apps/chrg/applications/thread/chrg_north.h b/apps/chrg/applications/thread/chrg_north.h index 4c555e7..1201fa3 100644 --- a/apps/chrg/applications/thread/chrg_north.h +++ b/apps/chrg/applications/thread/chrg_north.h @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_north.h 完成日期 : -当前版本号 : V1.1.21 +当前版本号 : V1.1.22 主要功能 : 实现北向通信交互，包括接收命令解析，发送请求命令，切换通路。以独立线程处理。 版本历史 : 创建原始版本 说明 : diff --git a/apps/chrg/applications/thread/chrg_roll_sou.c b/apps/chrg/applications/thread/chrg_roll_sou.c index 3cf71bd..9546fdf 100644 --- a/apps/chrg/applications/thread/chrg_roll_sou.c +++ b/apps/chrg/applications/thread/chrg_roll_sou.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_roll_sou.c 完成日期 : -当前版本号 : V1.1.22 +当前版本号 : V1.1.23 主要功能 : 实现南向通信轮巡请求命令。以独立线程处理。 版本历史 : 创建原始版本 说明 : @@ -49,6 +49,37 @@ static rt_uint8_t g_sou_com_batch_rr_next_ch = 0U; static rt_uint8_t g_sou_com_batch_burst_ch = TOTAL_SOU_CHS; static rt_uint8_t g_sou_com_batch_burst_count = 0U; +static rt_bool_t sou_com_batch_is_priority(rt_uint8_t ch, + sou_com_batch_ch_t *pBatch) +{ + rt_uint16_t reg; + rt_uint16_t value; + + if ((ch >= TOTAL_SOU_CHS) || (pBatch == RT_NULL) || + (pBatch->cur_idx >= pBatch->reg_cnt)) { + return RT_FALSE; + } + reg = pBatch->reg_list[pBatch->cur_idx]; + value = pBatch->val_list[pBatch->cur_idx]; + if ((reg == REG_WORK) && (value == WORK_STOP)) { + return RT_TRUE; + } + if ((reg == ModbusRTU_ShortTest_CMD_MODE_FLAG) && + (value == ModbusRTU_DYNA_CMD_MODE_STOP)) { + return RT_TRUE; + } + if ((reg == REG_REL_ON) && (value == ALL_REL_OFF)) { + return RT_TRUE; + } + if ((reg == REG_WORK) && (value == WORK_START) && + (chrgnorth.sw[ch].sink.work_mode == SINK_WORK_ON_TEST_SHORT || + chrgnorth.sw[ch].sink.work_mode == SINK_WORK_ON_TEST_DYNA || + chrgnorth.sw[ch].sink.work_mode == SINK_WORK_ON_TEST_OCP)) { + return RT_TRUE; + } + return RT_FALSE; +} + struct chrg_rollsou_t chrgrollsou = { .run = RUN_AUTO, .ch = IDX_SOU_CH1, @@ -538,6 +569,25 @@ static int sou_com_batch_next(rt_uint8_t *ch, rt_uint16_t *reg, rt_uint16_t *val } now = rt_tick_get(); + /* 测试切换和停止命令先执行，避免被其它通道的长测试批次拖延。 */ + for (offset = 0; offset < TOTAL_SOU_CHS; offset++) { + idx = (rt_uint8_t)((g_sou_com_batch_rr_next_ch + offset) % + TOTAL_SOU_CHS); + sou_com_batch_ch_t *pBatch = &g_sou_com_batch.ch[idx]; + if ((pBatch->pending != RT_TRUE) || + (pBatch->cur_idx >= pBatch->reg_cnt) || + !sou_com_batch_is_priority(idx, pBatch) || + ((pBatch->next_send_tick != 0U) && + ((rt_int32_t)(now - pBatch->next_send_tick) < 0))) { + continue; + } + pBatch->next_send_tick = 0U; + *ch = idx; + *reg = pBatch->reg_list[pBatch->cur_idx]; + *value = pBatch->val_list[pBatch->cur_idx]; + rt_mutex_release(pTHR->mutex); + return 1; + } /* 短路保活的WORK_START达到周期后优先下发，避免长批次挤占30ms保活窗口。 */ for (offset = 0; offset < TOTAL_SOU_CHS; offset++) { idx = (rt_uint8_t)((g_sou_com_batch_rr_next_ch + offset) % @@ -927,7 +977,9 @@ void chrg_roll_sou_thread_entry (void *data) batch_ch = command_ch; command_valid = RT_TRUE; chrg_south_switch((eIDX_SOU_CH)command_ch); + #if SOUTH_COMMAND_DEBUG rt_kprintf("ch=%d",command_ch); + #endif chrg_eload_write_reg(ID_ELOAD, command_reg, command_value); } break; diff --git a/apps/chrg/applications/utils/chrg_eload.c b/apps/chrg/applications/utils/chrg_eload.c index 30f8a39..f3f6550 100644 --- a/apps/chrg/applications/utils/chrg_eload.c +++ b/apps/chrg/applications/utils/chrg_eload.c @@ -407,7 +407,6 @@ int chrg_eload_parse_version (rt_uint8_t idx, rt_uint8_t *data, rt_uint16_t len) { rt_uint16_t version; - /* A one-register Modbus 0x03 response is 7 bytes including CRC16. */ if ((idx >= TOTAL_SOU_CHS) || (data == RT_NULL) || (len != (MODBUSRTU_SW_VERSION_LEN * 2U + 5U)) || (data[0] != ID_ELOAD) || (data[1] != MB_REGISTER_RD) || @@ -416,7 +415,7 @@ int chrg_eload_parse_version (rt_uint8_t idx, rt_uint8_t *data, rt_uint16_t len) } version = u8v_to_u16(&data[3]); - /* HOLD_REG_CH0_VERSION is the per-channel south board version register. */ + usRegHoldBuf[HOLD_REG_CH0_VERSION + idx * TOTAL_HOLD_CH_REGS] = version; return 0; } @@ -443,9 +442,7 @@ int chrg_eload_parse (rt_uint8_t idx, rt_uint8_t pt, rt_uint8_t *data, rt_uint16 return -1; } struct eload_p1_t *pP1 = (struct eload_p1_t *)&data[3]; -// for(int i = 0;i<36;i++){ -// rt_kprintf("%02x ",data[i+3]); -// } + pLOAD->status1 = pP1->status1; pLOAD->status2 = pP1->status2; pLOAD->fault1 = pP1->fault1; @@ -465,6 +462,8 @@ int chrg_eload_parse (rt_uint8_t idx, rt_uint8_t pt, rt_uint8_t *data, rt_uint16 pLOAD->vpp = swap_u16(pP1->Vpp); pLOAD->Ripple = chrg_eload_ripple_filter_update(idx, swap_u16(pP1->Ripple)); +// if(idx == IDX_CH3) +// rt_kprintf("-----Ripple = %d-------\n",pLOAD->Ripple); /* 保留功率板返回的真实电流，供卸载保护判断使用。 */ pSW->Now_current = pLOAD->current; /* @@ -486,14 +485,6 @@ int chrg_eload_parse (rt_uint8_t idx, rt_uint8_t pt, rt_uint8_t *data, rt_uint16 /* 电压、电流均更新完成后再发布序号，避免状态机读取到半更新数据。 */ g_eload_sample_seq[idx]++; #if LCD_OPEN -// for(int i = 0;i<4;i++){ -// if(pNOR->sw[i].change_flag == 0x01){ -// pNOR->free_flag = 0x00; -// }else { -// pNOR->free_flag = 0x01; -// } -// } -// rt_kprintf("ch=%d,free_flag=%d,",idx,pNOR->free_flag); if(pNOR->free_flag==0x01){ LCD_SHOW(idx, pP1, pLOAD, pSW, pSOU->online[idx]); } @@ -525,7 +516,6 @@ int chrg_eload_parse (rt_uint8_t idx, rt_uint8_t pt, rt_uint8_t *data, rt_uint16 chrg_eload_dpdm_host_value(pSW->VZ); usRegHoldBuf[HOLD_REG_CH0_VF+idx*TOTAL_HOLD_CH_REGS] = chrg_eload_dpdm_host_value(pSW->VF); -// rt_kprintf("---------NOW VOLT END = %d\n----------",pSW->Now_voltage); return 0; } diff --git a/apps/chrg/applications/utils/chrg_sink.c b/apps/chrg/applications/utils/chrg_sink.c index 1e8d53d..fa2cdda 100644 --- a/apps/chrg/applications/utils/chrg_sink.c +++ b/apps/chrg/applications/utils/chrg_sink.c @@ -1,7 +1,7 @@ /**************************************************************************** 文件名称 : chrg_sink.c 完成日期 : -当前版本号 : V1.1.21 +当前版本号 : V1.1.24 主要功能 : 北向数据sink请求数据填充及发送。 版本历史 : 创建原始版本 说明 : @@ -33,6 +33,7 @@ static rt_uint8_t g_sink_init_stage[TOTAL_SOU_CHS] = {0}; static rt_tick_t g_sink_init_north_relay_tick[TOTAL_SOU_CHS] = {0}; +static rt_bool_t g_sink_init_in_progress[TOTAL_SOU_CHS] = {RT_FALSE}; /* 主继电器闭合跟踪：1=已提交ALL_REL_ON（主继电器应已闭合） 0=未闭合/已断开。 * 用于0V硬保护区分"首次开载/握手恢复"（主继电器未闭合，Now_voltage=0属正常） @@ -255,22 +256,22 @@ static rt_uint8_t chrg_sink_init_build_commands(struct chrg_switch_t *pSW, { rt_uint8_t count; + regs[0] = ModbusRTU_ShortTest_CMD_MODE_FLAG; + vals[0] = ModbusRTU_DYNA_CMD_MODE_STOP; if (pSW->sink.test.test_mode_old == SINK_TEST_SHORT) { - regs[0] = REG_REL_ON; vals[0] = ALL_REL_OFF; - regs[1] = REG_REL_ON; vals[1] = FU_REL_ON; - regs[2] = REG_CURRENT_OUT + 1; vals[2] = 0; - regs[3] = REG_MODE; vals[3] = pSW->CV_mode; - regs[4] = Eload_Start_V_ON; vals[4] = (pSW->sink.volt_on <= 500) ? 500 : pSW->sink.volt_on; - regs[5] = ModbusRTU_ShortTest_CMD_MODE_FLAG; - vals[5] = ModbusRTU_DYNA_CMD_MODE_STOP; + regs[1] = REG_REL_ON; vals[1] = ALL_REL_OFF; + regs[2] = REG_REL_ON; vals[2] = FU_REL_ON; + regs[3] = REG_CURRENT_OUT + 1; vals[3] = 0; + regs[4] = REG_MODE; vals[4] = pSW->CV_mode; + regs[5] = Eload_Start_V_ON; vals[5] = (pSW->sink.volt_on <= 500) ? 500 : pSW->sink.volt_on; count = 6U; } else { - regs[0] = REG_REL_ON; vals[0] = FU_REL_ON; - regs[1] = REG_CURRENT_OUT + 1; vals[1] = 0; - regs[2] = REG_MODE; vals[2] = pSW->CV_mode; - regs[3] = Eload_Start_V_ON; vals[3] = + regs[1] = REG_REL_ON; vals[1] = FU_REL_ON; + regs[2] = REG_CURRENT_OUT + 1; vals[2] = 0; + regs[3] = REG_MODE; vals[3] = pSW->CV_mode; + regs[4] = Eload_Start_V_ON; vals[4] = (pSW->sink.volt_on <= 500) ? 500 : pSW->sink.volt_on; - count = 4U; + count = 5U; if (pSW->sink.test.test_mode_old == SINK_TEST_OCP) { regs[count] = ModbusRTU_OCPTest_CMD_MODE_FLAG; vals[count++] = ModbusRTU_DYNA_CMD_MODE_STOP; @@ -290,14 +291,11 @@ static int chrg_sink_init_submit_stage(eIDX_SOU_CH idx, rt_uint8_t total; rt_uint8_t start; rt_uint8_t count; - rt_bool_t short_exit; if ((idx >= TOTAL_SOU_CHS) || (pSW == RT_NULL)) { return -1; } total = chrg_sink_init_build_commands(pSW, regs, vals); - short_exit = (pSW->sink.test.test_mode_old == SINK_TEST_SHORT) ? - RT_TRUE : RT_FALSE; switch (g_sink_init_stage[idx]) { case SINK_INIT_STAGE_CLEAR_RELAY: @@ -305,12 +303,12 @@ static int chrg_sink_init_submit_stage(eIDX_SOU_CH idx, count = 1U; break; case SINK_INIT_STAGE_AUX_RELAY: - start = short_exit ? 1U : 0U; + start = 1U; count = 1U; break; case SINK_INIT_STAGE_REST: - start = short_exit ? 2U : 1U; - count = (rt_uint8_t)(total - start); + start = 2U; + count = (rt_uint8_t)(total - 2U); break; default: return -1; @@ -320,23 +318,23 @@ static int chrg_sink_init_submit_stage(eIDX_SOU_CH idx, /***************************************************************** 函数名称： chrg_sink_work_init -函数描述： 执行负载INIT入口，先提交辅助继电器命令 +函数描述： 执行负载INIT入口，首帧先退出短路测试 输入参数： idx:南向功率通道编号 pSW:当前通道控制结构体 -输出参数： 进入INIT_AUX_WAIT后台等待辅助继电器回码 +输出参数： 进入INIT_AUX_WAIT后台等待南向回码 返回说明： 0:初始化命令提交成功 <0:参数或命令提交失败 其它说明： 收到01 02有效回码后等待30ms，再打开北向Sink继电器 *****************************************************************/ static int chrg_sink_work_init(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) { - rt_bool_t short_exit; - if ((idx >= TOTAL_SOU_CHS) || (pSW == RT_NULL)) { return -1; } - short_exit = (pSW->sink.test.test_mode_old == SINK_TEST_SHORT) ? - RT_TRUE : RT_FALSE; - g_sink_init_stage[idx] = short_exit ? SINK_INIT_STAGE_CLEAR_RELAY : - SINK_INIT_STAGE_AUX_RELAY; + /* 初始化必须优先于本通道尚未发送的旧命令，避免旧WORK_START插入初始化流程。 */ + if (chrg_sou_com_batch_cancel(idx) != 0) { + return -1; + } + g_sink_init_in_progress[idx] = RT_TRUE; + g_sink_init_stage[idx] = SINK_INIT_STAGE_CLEAR_RELAY; g_sink_init_north_relay_tick[idx] = 0U; if (chrg_sink_init_submit_stage(idx, pSW) != 0) { return -1; @@ -374,7 +372,9 @@ static int chrg_sink_work_init_aux_wait(eIDX_SOU_CH idx, return 0; } chrg_nor_sw_rel((eIDX_NOR_CH)idx, ID_SINK); + #if SOUTH_COMMAND_DEBUG rt_kprintf("-------D+D- OPEN------\n"); + #endif pNOR->enable[idx] = 1; pSW->sub = IDX_SET_SINK_CC_BEFORE_PD; g_sink_init_stage[idx] = SINK_INIT_STAGE_REST; @@ -399,6 +399,7 @@ static int chrg_sink_work_init_aux_wait(eIDX_SOU_CH idx, } /* 北向可能已推进到CC或电压查询，此处只更新南向完成状态。 */ + g_sink_init_in_progress[idx] = RT_FALSE; pSOU->online[idx] = 1; pSW->sink.test.test_mode_old = 0; pSW->sink.work_mode = SINK_WORK_WAIT; @@ -492,6 +493,9 @@ static int chrg_sink_work_volt_runing(eIDX_SOU_CH idx, struct chrg_switch_t *pSW } /* RUNING批次必须完整发送：ALL_REL_ON、目标负载值、WORK_START。 */ ret = chrg_sou_com_batch_submit(idx, regs, vals, 3U); + #if SOUTH_COMMAND_DEBUG + rt_kprintf("------ALL_REL_ON-------\n"); + #endif if (ret == 0) { g_sink_rel_main_closed[idx] = 1; } @@ -517,6 +521,7 @@ static int chrg_sink_work_load_stop(eIDX_SOU_CH idx, return -1; } /* 自动停止优先于同通道残留启动批次，禁止STOP后继续发送WORK_START。 */ + g_sink_init_in_progress[idx] = RT_FALSE; if (chrg_sou_com_batch_cancel(idx) != 0) { return -1; } @@ -568,6 +573,7 @@ static int chrg_sink_nor_work_low(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) return -1; } /* 低压保护优先级最高，先丢弃该通道残留的启动或设定命令。 */ + g_sink_init_in_progress[idx] = RT_FALSE; if (chrg_sou_com_batch_cancel(idx) != 0) { return -1; } @@ -629,6 +635,7 @@ static int chrg_sink_work_stop_prepare(eIDX_SOU_CH idx, if ((idx >= TOTAL_SOU_CHS) || (pSW == RT_NULL)) { return -1; } + g_sink_init_in_progress[idx] = RT_FALSE; if (chrg_sou_com_batch_cancel(idx) != 0) { return -1; } @@ -918,8 +925,9 @@ static int chrg_sink_TEST_DYNA_ON(rt_uint8_t ch, struct chrg_switch_t *pSW) *****************************************************************/ static int chrg_sink_TEST_SHORT_ON(rt_uint8_t ch, struct chrg_switch_t *pSW) { - rt_uint16_t regs[4] = {Eload_Start_V_ON, ModbusRTU_ShortTest_Hold_Time, - ModbusRTU_ShortTest_CMD_MODE_FLAG, REG_WORK}; + rt_uint16_t regs[4] = {Eload_Start_V_ON, + ModbusRTU_ShortTest_Hold_Time, ModbusRTU_ShortTest_CMD_MODE_FLAG, + REG_WORK}; rt_uint16_t vals[4] = {SINK_SHORT_TEST_VON_MV, 0, 0, 0}; /* 外部工程固定短路测试保持60秒且不带载。 */ vals[1] = 60000; @@ -995,6 +1003,18 @@ int chrg_sink_volt_judge(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) if ((idx >= TOTAL_SOU_CHS) || (pSW == RT_NULL)) { return -1; } + /* 初始化及短路退出批次完成前，禁止电压判定提前启动普通负载。 */ + if (g_sink_init_in_progress[idx] || + (pSW->sink.work_mode == SINK_WORK_INIT) || + (pSW->sink.work_mode == SINK_WORK_INIT_AUX_WAIT)) { + if (g_sink_init_in_progress[idx] && + (pSW->sink.work_mode != SINK_WORK_INIT) && + (pSW->sink.work_mode != SINK_WORK_INIT_AUX_WAIT)) { + pSW->sink.work_mode = SINK_WORK_INIT_AUX_WAIT; + } + return chrg_sink_work(idx, pSW); + } + #if SINK_VON_VOLTAGE_SOURCE == SINK_VON_VOLTAGE_FROM_PROTOCOL voltage_seq = pSW->Sink_voltage_seq; #else @@ -1171,6 +1191,13 @@ int chrg_sink_work(eIDX_SOU_CH idx, struct chrg_switch_t *pSW) } work_mode = pSW->sink.work_mode; workmode = work_mode; + /* 初始化事务独占该通道，防止其它路径改成RUNING后追加普通启动命令。 */ + if (g_sink_init_in_progress[idx] && + (work_mode != SINK_WORK_INIT) && + (work_mode != SINK_WORK_INIT_AUX_WAIT)) { + pSW->sink.work_mode = SINK_WORK_INIT_AUX_WAIT; + work_mode = SINK_WORK_INIT_AUX_WAIT; + } if (work_mode != SINK_WORK_ON_TEST_SHORT) { g_sink_short_start_tick[idx] = 0; } diff --git a/docs/Allegro.jrl b/docs/Allegro.jrl index b4d3f7f..6496f36 100644 --- a/docs/Allegro.jrl +++ b/docs/Allegro.jrl @@ -1,105 +1,49 @@ -\t (00:00:06) allegro 17.2 S079 Windows SPB 64-bit Edition -\t (00:00:06) Journal start - Fri Sep 11 15:37:07 2026 -\t (00:00:06) Host=DESKTOP-5RA9F3K User=Adminuser Pid=13160 CPUs=20 -\t (00:00:06) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe -\t (00:00:06) - (00:00:06) Loading axlcore.cxt -\t (00:00:06) Starting new design... -\i (00:00:07) trapsize 29310 -\i (00:00:08) generaledit -\i (00:00:11) open -\i (00:00:12) fillin "HC_DFCD_Protocol_V3_0.brd" -\i (00:00:12) trapsize 1230 -\i (00:00:12) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed -\t (00:00:12) Opening existing design... -\i (00:00:12) trapsize 2757 -\d (00:00:12) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd +\t (00:00:01) allegro 17.2 S079 Windows SPB 64-bit Edition +\t (00:00:01) Journal start - Tue Sep 15 20:16:48 2026 +\t (00:00:01) Host=DESKTOP-5RA9F3K User=Adminuser Pid=20076 CPUs=20 +\t (00:00:01) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe +\t (00:00:01) + (00:00:01) Loading axlcore.cxt +\t (00:00:02) Starting new design... +\i (00:00:04) trapsize 29310 +\i (00:00:05) generaledit +\i (00:00:12) open +\i (00:00:13) fillin "HC_DFCD_Protocol_V3_0.brd" +\i (00:00:13) trapsize 1230 +\i (00:00:13) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed +\t (00:00:13) Opening existing design... +\i (00:00:13) trapsize 2757 +\d (00:00:13) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd \i (00:00:13) generaledit -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 27.8998 58.3935 -\i (00:00:13) trapsize 5515 -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 27.7896 58.0627 -\i (00:00:13) trapsize 11030 -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 96.9925 57.6215 -\i (00:00:13) trapsize 22060 -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 299.2792 77.8006 -\i (00:00:13) trapsize 44119 -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 710.9119 236.1887 -\i (00:00:13) trapsize 88239 -\i (00:00:13) zoom out 1 -\i (00:00:13) setwindow pcb -\i (00:00:13) zoom out 1546.5306 547.6707 -\i (00:00:13) trapsize 176477 -\i (00:00:14) zoom in 1 +\i (00:00:14) zoom out 1 \i (00:00:14) setwindow pcb -\i (00:00:14) zoom in 101.1838 -64.7046 -\i (00:00:14) trapsize 88239 -\i (00:00:14) zoom in 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom in 99.4190 -62.9398 -\i (00:00:14) trapsize 44119 -\i (00:00:14) zoom in 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom in 92.3600 -31.1739 -\i (00:00:14) trapsize 22060 -\i (00:00:14) zoom in 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom in 92.3600 -30.7327 -\i (00:00:14) trapsize 11030 -\i (00:00:14) zoom in 1 -\i (00:00:14) setwindow pcb -\i (00:00:14) zoom in 92.3600 -30.5121 +\i (00:00:14) zoom out 17.5318 56.5185 \i (00:00:14) trapsize 5515 -\i (00:00:15) drag_start grid 110.6695 -6.4671 -\i (00:00:15) drag_stop 188.9811 -20.1441 -\i (00:00:15) zoom out 1 -\i (00:00:15) setwindow pcb -\i (00:00:15) zoom out 102.1765 2.3567 -\i (00:00:15) trapsize 11030 -\i (00:00:15) zoom out 1 -\i (00:00:15) setwindow pcb -\i (00:00:15) zoom out 102.3972 1.6950 -\i (00:00:15) trapsize 22060 -\i (00:00:15) zoom out 1 -\i (00:00:15) setwindow pcb -\i (00:00:15) zoom out 104.6031 47.3583 -\i (00:00:15) trapsize 44119 -\i (00:00:16) zoom in 1 -\i (00:00:16) setwindow pcb -\i (00:00:16) zoom in -19.8131 37.6521 -\i (00:00:16) trapsize 22060 -\i (00:00:16) zoom in 1 -\i (00:00:16) setwindow pcb -\i (00:00:16) zoom in -5.2538 42.5053 -\i (00:00:16) trapsize 11030 -\i (00:00:16) zoom in 1 -\i (00:00:16) setwindow pcb -\i (00:00:16) zoom in -5.2537 42.7259 -\i (00:00:16) trapsize 5515 -\i (00:00:17) zoom in 1 -\i (00:00:17) setwindow pcb -\i (00:00:17) zoom in 48.1306 62.4692 -\i (00:00:17) trapsize 2757 +\i (00:00:14) zoom out 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom out 21.9438 59.0553 +\i (00:00:14) trapsize 11030 +\i (00:00:14) zoom out 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom out 64.3442 57.9524 +\i (00:00:14) trapsize 22060 +\i (00:00:17) open +\i (00:00:20) fillin "menu_cancel" +\i (00:00:20) generaledit \i (00:00:20) zoom in 1 \i (00:00:20) setwindow pcb -\i (00:00:20) zoom in 64.2893 72.1203 -\i (00:00:20) trapsize 1379 -\i (00:00:21) zoom out 1 -\i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 61.4492 70.2728 -\i (00:00:21) trapsize 2757 -\i (00:00:21) zoom out 1 -\i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 58.1402 66.3021 -\i (00:00:21) trapsize 5515 -\i (00:10:52) exit -\t (00:10:53) Journal end - Fri Sep 11 15:47:54 2026 +\i (00:00:20) zoom in 19.5632 59.7117 +\i (00:00:20) trapsize 11030 +\i (00:00:20) zoom in 1 +\i (00:00:20) setwindow pcb +\i (00:00:20) zoom in 11.6217 57.0646 +\i (00:00:20) trapsize 5515 +\i (00:00:22) open +\i (00:00:26) fillin "menu_cancel" +\i (00:00:26) generaledit +\i (00:00:26) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "Start Page" +\i (00:00:28) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged HC_DFCD_Protocol_V3_0 +\i (00:00:28) opencd D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/south/HC_DFCD_Source_Eload_V1_1/PCB/HC_DFCD_Source_Eload_V1_1.brd +\t (00:00:28) Opening existing design... +\i (00:00:29) trapsize 283 +\t (00:00:29) Journal end - Tue Sep 15 20:17:15 2026 diff --git a/docs/allegro.jrl,1 b/docs/allegro.jrl,1 index f472350..b4d3f7f 100644 --- a/docs/allegro.jrl,1 +++ b/docs/allegro.jrl,1 @@ -1,953 +1,105 @@ -\t (00:00:02) allegro 17.2 S079 Windows SPB 64-bit Edition -\t (00:00:02) Journal start - Wed Aug 26 11:20:30 2026 -\t (00:00:02) Host=DESKTOP-5RA9F3K User=Adminuser Pid=37292 CPUs=20 -\t (00:00:02) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe -\t (00:00:02) - (00:00:02) Loading axlcore.cxt -\t (00:00:03) Starting new design... -\i (00:00:04) trapsize 29310 -\i (00:00:04) generaledit -\i (00:00:16) open -\i (00:00:19) fillin "HC_DFCD_Protocol_V3_0.brd" -\i (00:00:19) trapsize 1230 -\i (00:00:19) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed -\t (00:00:19) Opening existing design... -\i (00:00:20) trapsize 8018 -\d (00:00:20) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd -\i (00:00:20) generaledit -\i (00:00:21) zoom in 1 -\i (00:00:21) setwindow pcb -\i (00:00:21) zoom in 9.3881 57.0243 -\i (00:00:21) trapsize 4009 -\i (00:00:21) zoom in 1 -\i (00:00:21) setwindow pcb -\i (00:00:21) zoom in 9.3881 57.1046 -\i (00:00:21) trapsize 2005 +\t (00:00:06) allegro 17.2 S079 Windows SPB 64-bit Edition +\t (00:00:06) Journal start - Fri Sep 11 15:37:07 2026 +\t (00:00:06) Host=DESKTOP-5RA9F3K User=Adminuser Pid=13160 CPUs=20 +\t (00:00:06) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe +\t (00:00:06) + (00:00:06) Loading axlcore.cxt +\t (00:00:06) Starting new design... +\i (00:00:07) trapsize 29310 +\i (00:00:08) generaledit +\i (00:00:11) open +\i (00:00:12) fillin "HC_DFCD_Protocol_V3_0.brd" +\i (00:00:12) trapsize 1230 +\i (00:00:12) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed +\t (00:00:12) Opening existing design... +\i (00:00:12) trapsize 2757 +\d (00:00:12) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd +\i (00:00:13) generaledit +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 27.8998 58.3935 +\i (00:00:13) trapsize 5515 +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 27.7896 58.0627 +\i (00:00:13) trapsize 11030 +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 96.9925 57.6215 +\i (00:00:13) trapsize 22060 +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 299.2792 77.8006 +\i (00:00:13) trapsize 44119 +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 710.9119 236.1887 +\i (00:00:13) trapsize 88239 +\i (00:00:13) zoom out 1 +\i (00:00:13) setwindow pcb +\i (00:00:13) zoom out 1546.5306 547.6707 +\i (00:00:13) trapsize 176477 +\i (00:00:14) zoom in 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom in 101.1838 -64.7046 +\i (00:00:14) trapsize 88239 +\i (00:00:14) zoom in 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom in 99.4190 -62.9398 +\i (00:00:14) trapsize 44119 +\i (00:00:14) zoom in 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom in 92.3600 -31.1739 +\i (00:00:14) trapsize 22060 +\i (00:00:14) zoom in 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom in 92.3600 -30.7327 +\i (00:00:14) trapsize 11030 +\i (00:00:14) zoom in 1 +\i (00:00:14) setwindow pcb +\i (00:00:14) zoom in 92.3600 -30.5121 +\i (00:00:14) trapsize 5515 +\i (00:00:15) drag_start grid 110.6695 -6.4671 +\i (00:00:15) drag_stop 188.9811 -20.1441 +\i (00:00:15) zoom out 1 +\i (00:00:15) setwindow pcb +\i (00:00:15) zoom out 102.1765 2.3567 +\i (00:00:15) trapsize 11030 +\i (00:00:15) zoom out 1 +\i (00:00:15) setwindow pcb +\i (00:00:15) zoom out 102.3972 1.6950 +\i (00:00:15) trapsize 22060 +\i (00:00:15) zoom out 1 +\i (00:00:15) setwindow pcb +\i (00:00:15) zoom out 104.6031 47.3583 +\i (00:00:15) trapsize 44119 +\i (00:00:16) zoom in 1 +\i (00:00:16) setwindow pcb +\i (00:00:16) zoom in -19.8131 37.6521 +\i (00:00:16) trapsize 22060 +\i (00:00:16) zoom in 1 +\i (00:00:16) setwindow pcb +\i (00:00:16) zoom in -5.2538 42.5053 +\i (00:00:16) trapsize 11030 +\i (00:00:16) zoom in 1 +\i (00:00:16) setwindow pcb +\i (00:00:16) zoom in -5.2537 42.7259 +\i (00:00:16) trapsize 5515 +\i (00:00:17) zoom in 1 +\i (00:00:17) setwindow pcb +\i (00:00:17) zoom in 48.1306 62.4692 +\i (00:00:17) trapsize 2757 +\i (00:00:20) zoom in 1 +\i (00:00:20) setwindow pcb +\i (00:00:20) zoom in 64.2893 72.1203 +\i (00:00:20) trapsize 1379 \i (00:00:21) zoom out 1 \i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 11.3926 53.3761 -\i (00:00:21) trapsize 4009 +\i (00:00:21) zoom out 61.4492 70.2728 +\i (00:00:21) trapsize 2757 \i (00:00:21) zoom out 1 \i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 11.3926 53.3762 -\i (00:00:21) trapsize 8018 -\i (00:00:21) zoom out 1 -\i (00:00:21) setwindow pcb -\i (00:00:21) zoom out 11.3925 53.3762 -\i (00:00:21) trapsize 16037 -\i (00:00:22) zoom in 1 -\i (00:00:22) setwindow pcb -\i (00:00:22) zoom in -23.2465 36.3774 -\i (00:00:22) trapsize 8018 -\i (00:00:22) zoom in 1 -\i (00:00:22) setwindow pcb -\i (00:00:22) zoom in 1.2895 29.4817 -\i (00:00:22) trapsize 4009 -\i (00:00:26) zoom out 1 -\i (00:00:26) setwindow pcb -\i (00:00:26) zoom out 34.8060 21.2229 -\i (00:00:26) trapsize 8018 -\i (00:00:27) zoom out 1 -\i (00:00:27) setwindow pcb -\i (00:00:27) zoom out 28.8724 21.5436 -\i (00:00:27) trapsize 16037 -\i (00:00:27) zoom out 1 -\i (00:00:27) setwindow pcb -\i (00:00:27) zoom out -0.5732 30.8448 -\i (00:00:27) trapsize 32073 -\i (00:00:27) zoom out 1 -\i (00:00:27) setwindow pcb -\i (00:00:27) zoom out 91.7976 36.6180 -\i (00:00:27) trapsize 64146 -\i (00:00:28) zoom in 1 -\i (00:00:28) setwindow pcb -\i (00:00:28) zoom in -3.7805 8.3937 -\i (00:00:28) trapsize 32073 -\i (00:00:28) zoom in 1 -\i (00:00:28) setwindow pcb -\i (00:00:28) zoom in -6.9878 8.3937 -\i (00:00:28) trapsize 16037 -\i (00:00:28) zoom in 1 -\i (00:00:28) setwindow pcb -\i (00:00:28) zoom in -4.1012 1.0169 -\i (00:00:28) trapsize 8018 -\i (00:00:29) zoom in 1 -\i (00:00:29) setwindow pcb -\i (00:00:29) zoom in -4.1012 1.0169 -\i (00:00:29) trapsize 4009 -\i (00:00:30) zoom in 1 -\i (00:00:30) setwindow pcb -\i (00:00:30) zoom in 32.5425 24.1097 -\i (00:00:30) trapsize 2005 -\i (00:00:30) zoom in 1 -\i (00:00:30) setwindow pcb -\i (00:00:30) zoom in 32.8232 23.3480 -\i (00:00:30) trapsize 1002 -\i (00:00:30) zoom in 1 -\i (00:00:30) setwindow pcb -\i (00:00:30) zoom in 33.2241 22.9672 -\i (00:00:30) trapsize 501 -\i (00:01:29) zoom out 1 -\i (00:01:29) setwindow pcb -\i (00:01:29) zoom out 31.5303 24.9216 -\i (00:01:29) trapsize 1002 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 30.3075 24.9016 -\i (00:01:30) trapsize 2005 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 29.9467 24.7012 -\i (00:01:30) trapsize 4009 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 29.7062 24.6211 -\i (00:01:30) trapsize 8018 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 28.4233 35.8467 -\i (00:01:30) trapsize 16037 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 28.1026 71.2708 -\i (00:01:30) trapsize 32073 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 98.2122 245.1074 -\i (00:01:30) trapsize 64146 -\i (00:01:30) zoom out 1 -\i (00:01:30) setwindow pcb -\i (00:01:30) zoom out 296.4245 590.2147 -\i (00:01:30) trapsize 128293 -\i (00:01:31) zoom in 1 -\i (00:01:31) setwindow pcb -\i (00:01:31) zoom in -97.4341 64.2147 -\i (00:01:31) trapsize 64146 -\i (00:01:31) zoom in 1 -\i (00:01:31) setwindow pcb -\i (00:01:31) zoom in -97.4341 64.2147 -\i (00:01:31) trapsize 32073 -\i (00:01:31) zoom in 1 -\i (00:01:31) setwindow pcb -\i (00:01:31) zoom in -97.4340 64.8562 -\i (00:01:31) trapsize 16037 -\i (00:01:31) zoom in 1 -\i (00:01:31) setwindow pcb -\i (00:01:31) zoom in -78.5108 74.7989 -\i (00:01:31) trapsize 8018 -\i (00:01:32) zoom in 1 -\i (00:01:32) setwindow pcb -\i (00:01:32) zoom in 38.0752 90.8355 -\i (00:01:32) trapsize 4009 -\i (00:01:32) zoom in 1 -\i (00:01:32) setwindow pcb -\i (00:01:32) zoom in 36.0707 90.8356 -\i (00:01:32) trapsize 2005 -\i (00:01:32) zoom in 1 -\i (00:01:32) setwindow pcb -\i (00:01:32) zoom in 30.8187 90.1942 -\i (00:01:32) trapsize 1002 -\i (00:01:33) zoom in 1 -\i (00:01:33) setwindow pcb -\i (00:01:33) zoom in 21.8583 91.4170 -\i (00:01:33) trapsize 501 -\i (00:01:33) zoom out 1 -\i (00:01:33) setwindow pcb -\i (00:01:33) zoom out 21.9585 91.5072 -\i (00:01:33) trapsize 1002 -\i (00:01:34) zoom in 1 -\i (00:01:34) setwindow pcb -\i (00:01:34) zoom in 18.3102 91.2667 -\i (00:01:34) trapsize 501 -\i (00:01:35) zoom out 1 -\i (00:01:35) setwindow pcb -\i (00:01:35) zoom out 18.3403 91.3670 -\i (00:01:35) trapsize 1002 -\i (00:01:35) zoom out 1 -\i (00:01:35) setwindow pcb -\i (00:01:35) zoom out 18.3604 91.2667 -\i (00:01:35) trapsize 2005 -\i (00:01:35) zoom out 1 -\i (00:01:35) setwindow pcb -\i (00:01:35) zoom out 18.2803 90.5050 -\i (00:01:35) trapsize 4009 -\i (00:01:35) zoom out 1 -\i (00:01:35) setwindow pcb -\i (00:01:35) zoom out 18.2803 90.1842 -\i (00:01:35) trapsize 8018 -\i (00:01:36) zoom out 1 -\i (00:01:36) setwindow pcb -\i (00:01:36) zoom out 19.2424 88.9014 -\i (00:01:36) trapsize 16037 -\i (00:01:36) zoom out 1 -\i (00:01:36) setwindow pcb -\i (00:01:36) zoom out 19.2424 88.5806 -\i (00:01:36) trapsize 32073 -\i (00:01:36) zoom out 1 -\i (00:01:36) setwindow pcb -\i (00:01:36) zoom out 19.2425 60.9977 -\i (00:01:36) trapsize 64146 -\i (00:01:37) zoom out 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom out 17.9595 115.5317 -\i (00:01:37) trapsize 128293 -\i (00:01:37) zoom out 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom out 17.9595 323.3659 -\i (00:01:37) trapsize 256585 -\i (00:01:37) zoom in 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom in -79.5429 23.1610 -\i (00:01:37) trapsize 128293 -\i (00:01:37) zoom in 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom in -79.5429 23.1610 -\i (00:01:37) trapsize 64146 -\i (00:01:37) zoom in 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom in -79.5429 23.1610 -\i (00:01:37) trapsize 32073 -\i (00:01:37) zoom in 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom in -76.9770 37.2732 -\i (00:01:37) trapsize 16037 -\i (00:01:37) zoom in 1 -\i (00:01:37) setwindow pcb -\i (00:01:37) zoom in -75.0526 41.7635 -\i (00:01:37) trapsize 8018 -\i (00:01:38) zoom in 1 -\i (00:01:38) setwindow pcb -\i (00:01:38) zoom in -3.0483 90.8355 -\i (00:01:38) trapsize 4009 -\i (00:01:38) zoom in 1 -\i (00:01:38) setwindow pcb -\i (00:01:38) zoom in -0.7229 92.4392 -\i (00:01:38) trapsize 2005 -\i (00:01:39) zoom in 1 -\i (00:01:39) setwindow pcb -\i (00:01:39) zoom in 22.9712 93.2811 -\i (00:01:39) trapsize 1002 -\i (00:01:39) zoom in 1 -\i (00:01:39) setwindow pcb -\i (00:01:39) zoom in 22.9712 93.2811 -\i (00:01:39) trapsize 501 -\i (00:01:54) zoom out 1 -\i (00:01:54) setwindow pcb -\i (00:01:54) zoom out 19.1125 92.5294 -\i (00:01:54) trapsize 1002 -\i (00:07:02) zoom in 1 -\i (00:07:02) setwindow pcb -\i (00:07:02) zoom in 18.4710 93.8724 -\i (00:07:02) trapsize 501 -\i (00:07:04) zoom out 1 -\i (00:07:04) setwindow pcb -\i (00:07:04) zoom out 19.5334 91.9480 -\i (00:07:04) trapsize 1002 -\i (00:07:09) zoom in 1 -\i (00:07:09) setwindow pcb -\i (00:07:09) zoom in 18.4911 91.9882 -\i (00:07:09) trapsize 501 -\i (00:07:10) zoom out 1 -\i (00:07:10) setwindow pcb -\i (00:07:10) zoom out 19.2128 91.7075 -\i (00:07:10) trapsize 1002 -\i (00:07:25) zoom out 1 -\i (00:07:25) setwindow pcb -\i (00:07:25) zoom out 18.4110 90.8857 -\i (00:07:25) trapsize 2005 -\i (00:07:25) zoom in 1 -\i (00:07:25) setwindow pcb -\i (00:07:25) zoom in 19.7340 89.8032 -\i (00:07:25) trapsize 1002 -\i (00:07:25) zoom in 1 -\i (00:07:25) setwindow pcb -\i (00:07:25) zoom in 20.3755 89.3422 -\i (00:07:25) trapsize 501 -\i (00:07:29) drag_start grid 20.6361 90.3947 -\i (00:07:29) drag_stop 20.6361 90.5751 -\i (00:07:51) zoom out 1 -\i (00:07:51) setwindow pcb -\i (00:07:51) zoom out 21.4980 90.2343 -\i (00:07:51) trapsize 1002 -\i (00:07:57) zoom out 1 -\i (00:07:57) setwindow pcb -\i (00:07:57) zoom out 26.5496 91.6375 -\i (00:07:57) trapsize 2005 -\i (00:07:57) zoom out 1 -\i (00:07:57) setwindow pcb -\i (00:07:57) zoom out 26.5497 91.6375 -\i (00:07:57) trapsize 4009 -\i (00:07:57) zoom out 1 -\i (00:07:57) setwindow pcb -\i (00:07:57) zoom out 29.5966 88.4301 -\i (00:07:57) trapsize 8018 -\i (00:07:57) zoom out 1 -\i (00:07:57) setwindow pcb -\i (00:07:57) zoom out 94.8445 88.4302 -\i (00:07:57) trapsize 16037 -\i (00:07:58) zoom in 1 -\i (00:07:58) setwindow pcb -\i (00:07:58) zoom in 28.6134 86.8265 -\i (00:07:58) trapsize 8018 -\i (00:07:58) zoom in 1 -\i (00:07:58) setwindow pcb -\i (00:07:58) zoom in 39.8390 91.4771 -\i (00:07:58) trapsize 4009 -\i (00:07:58) zoom in 1 -\i (00:07:58) setwindow pcb -\i (00:07:58) zoom in 39.8391 91.3969 -\i (00:07:58) trapsize 2005 -\i (00:07:59) zoom in 1 -\i (00:07:59) setwindow pcb -\i (00:07:59) zoom in 38.3557 90.8757 -\i (00:07:59) trapsize 1002 -\i (00:07:59) zoom in 1 -\i (00:07:59) setwindow pcb -\i (00:07:59) zoom in 36.6719 90.9960 -\i (00:07:59) trapsize 501 -\i (00:08:03) zoom out 1 -\i (00:08:03) setwindow pcb -\i (00:08:03) zoom out 41.0920 90.8257 -\i (00:08:03) trapsize 1002 -\i (00:08:13) zoom out 1 -\i (00:08:13) setwindow pcb -\i (00:08:13) zoom out 47.9476 90.6251 -\i (00:08:13) trapsize 2005 -\i (00:08:14) zoom in 1 -\i (00:08:14) setwindow pcb -\i (00:08:14) zoom in 33.2742 88.2999 -\i (00:08:14) trapsize 1002 -\i (00:08:16) zoom out 1 -\i (00:08:16) setwindow pcb -\i (00:08:16) zoom out 20.1643 90.6653 -\i (00:08:16) trapsize 2005 -\i (00:08:16) zoom out 1 -\i (00:08:16) setwindow pcb -\i (00:08:16) zoom out 20.1241 90.6653 -\i (00:08:16) trapsize 4009 -\i (00:08:17) zoom in 1 -\i (00:08:17) setwindow pcb -\i (00:08:17) zoom in 15.1528 89.7031 -\i (00:08:17) trapsize 2005 -\i (00:08:17) zoom in 1 -\i (00:08:17) setwindow pcb -\i (00:08:17) zoom in 15.1529 89.7031 -\i (00:08:17) trapsize 1002 -\i (00:23:54) zoom out 1 -\i (00:23:54) setwindow pcb -\i (00:23:54) zoom out 36.2810 91.7077 -\i (00:23:54) trapsize 2005 -\i (00:23:55) zoom in 1 -\i (00:23:55) setwindow pcb -\i (00:23:55) zoom in 38.2858 92.3893 -\i (00:23:55) trapsize 1002 -\i (00:23:55) zoom in 1 -\i (00:23:55) setwindow pcb -\i (00:23:55) zoom in 38.2857 92.3893 -\i (00:23:55) trapsize 501 -\i (00:23:55) zoom out 1 -\i (00:23:55) setwindow pcb -\i (00:23:55) zoom out 38.8972 92.3492 -\i (00:23:55) trapsize 1002 -\i (00:23:55) zoom out 1 -\i (00:23:55) setwindow pcb -\i (00:23:55) zoom out 38.8971 92.3492 -\i (00:23:55) trapsize 2005 -\i (00:23:58) zoom out 1 -\i (00:23:58) setwindow pcb -\i (00:23:58) zoom out 39.6189 90.6253 -\i (00:23:58) trapsize 4009 -\i (00:23:58) zoom in 1 -\i (00:23:58) setwindow pcb -\i (00:23:58) zoom in 39.2180 90.0640 -\i (00:23:58) trapsize 2005 -\i (00:23:58) zoom in 1 -\i (00:23:58) setwindow pcb -\i (00:23:58) zoom in 39.2180 90.0641 -\i (00:23:58) trapsize 1002 -\i (00:23:59) zoom in 1 -\i (00:23:59) setwindow pcb -\i (00:23:59) zoom in 39.2180 90.0641 -\i (00:23:59) trapsize 501 -\i (00:24:00) zoom out 1 -\i (00:24:00) setwindow pcb -\i (00:24:00) zoom out 32.0116 89.7134 -\i (00:24:00) trapsize 1002 -\i (00:24:02) zoom out 1 -\i (00:24:02) setwindow pcb -\i (00:24:02) zoom out 23.3319 88.5707 -\i (00:24:02) trapsize 2005 -\i (00:24:02) zoom out 1 -\i (00:24:02) setwindow pcb -\i (00:24:02) zoom out 22.4498 88.2099 -\i (00:24:02) trapsize 4009 -\i (00:24:02) zoom out 1 -\i (00:24:02) setwindow pcb -\i (00:24:02) zoom out 22.3697 88.2100 -\i (00:24:02) trapsize 8018 -\i (00:24:02) zoom out 1 -\i (00:24:02) setwindow pcb -\i (00:24:02) zoom out 22.3697 88.2099 -\i (00:24:02) trapsize 16037 -\i (00:24:03) zoom in 1 -\i (00:24:03) setwindow pcb -\i (00:24:03) zoom in 23.0111 88.5306 -\i (00:24:03) trapsize 8018 -\i (00:24:03) zoom in 1 -\i (00:24:03) setwindow pcb -\i (00:24:03) zoom in 23.0111 88.5307 -\i (00:24:03) trapsize 4009 -\i (00:24:04) zoom out 1 -\i (00:24:04) setwindow pcb -\i (00:24:04) zoom out 20.8462 88.2902 -\i (00:24:04) trapsize 8018 -\i (00:24:04) zoom out 1 -\i (00:24:04) setwindow pcb -\i (00:24:04) zoom out 20.8462 88.2902 -\i (00:24:04) trapsize 16037 -\i (00:24:04) zoom out 1 -\i (00:24:04) setwindow pcb -\i (00:24:04) zoom out 17.9597 86.0450 -\i (00:24:04) trapsize 32073 -\i (00:24:04) zoom out 1 -\i (00:24:04) setwindow pcb -\i (00:24:04) zoom out 16.6768 83.4792 -\i (00:24:04) trapsize 64146 -\i (00:24:05) zoom in 1 -\i (00:24:05) setwindow pcb -\i (00:24:05) zoom in -2.5671 69.3464 -\i (00:24:05) trapsize 32073 -\i (00:24:05) zoom in 1 -\i (00:24:05) setwindow pcb -\i (00:24:05) zoom in -2.5671 69.3464 -\i (00:24:05) trapsize 16037 -\i (00:24:06) zoom in 1 -\i (00:24:06) setwindow pcb -\i (00:24:06) zoom in -0.0012 80.8927 -\i (00:24:06) trapsize 8018 -\i (00:24:06) zoom in 1 -\i (00:24:06) setwindow pcb -\i (00:24:06) zoom in -0.0011 80.8928 -\i (00:24:06) trapsize 4009 -\i (00:24:06) zoom in 1 -\i (00:24:06) setwindow pcb -\i (00:24:06) zoom in 8.4181 88.3498 -\i (00:24:06) trapsize 2005 -\i (00:24:06) zoom in 1 -\i (00:24:06) setwindow pcb -\i (00:24:06) zoom in 8.4181 88.3499 -\i (00:24:06) trapsize 1002 -\i (00:26:42) zoom out 1 -\i (00:26:42) setwindow pcb -\i (00:26:42) zoom out 12.4874 88.6506 -\i (00:26:42) trapsize 2005 -\i (00:26:43) zoom out 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom out 12.2870 87.2074 -\i (00:26:43) trapsize 4009 -\i (00:26:43) zoom out 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom out 12.2069 84.7216 -\i (00:26:43) trapsize 8018 -\i (00:26:43) zoom out 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom out 12.5276 82.4765 -\i (00:26:43) trapsize 16037 -\i (00:26:43) zoom in 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom in -19.5456 56.1766 -\i (00:26:43) trapsize 8018 -\i (00:26:43) zoom in 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom in -19.7060 56.1766 -\i (00:26:43) trapsize 4009 -\i (00:26:43) zoom in 1 -\i (00:26:43) setwindow pcb -\i (00:26:43) zoom in -19.7059 56.1767 -\i (00:26:43) trapsize 2005 -\i (00:26:44) zoom out 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom out 2.9458 64.2752 -\i (00:26:44) trapsize 4009 -\i (00:26:44) zoom in 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom in 2.7854 63.8743 -\i (00:26:44) trapsize 2005 -\i (00:26:44) zoom out 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom out 2.7854 63.8744 -\i (00:26:44) trapsize 4009 -\i (00:26:44) zoom out 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom out 2.7854 63.8743 -\i (00:26:44) trapsize 8018 -\i (00:26:44) zoom in 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom in 39.0372 93.7024 -\i (00:26:44) trapsize 4009 -\i (00:26:44) zoom in 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom in 34.3866 95.6268 -\i (00:26:44) trapsize 2005 -\i (00:26:44) zoom in 1 -\i (00:26:44) setwindow pcb -\i (00:26:44) zoom in 28.3328 95.3863 -\i (00:26:44) trapsize 1002 -\i (00:26:48) zoom in 1 -\i (00:26:48) setwindow pcb -\i (00:26:48) zoom in 31.0991 90.2947 -\i (00:26:48) trapsize 501 -\i (00:26:52) zoom out 1 -\i (00:26:52) setwindow pcb -\i (00:26:52) zoom out 24.5141 90.1143 -\i (00:26:52) trapsize 1002 -\i (00:26:53) zoom in 1 -\i (00:26:53) setwindow pcb -\i (00:26:53) zoom in 24.1733 91.3772 -\i (00:26:53) trapsize 501 -\i (00:26:54) zoom out 1 -\i (00:26:54) setwindow pcb -\i (00:26:54) zoom out 25.6667 91.2369 -\i (00:26:54) trapsize 1002 -\i (00:26:54) zoom out 1 -\i (00:26:54) setwindow pcb -\i (00:26:54) zoom out 25.6667 91.0967 -\i (00:26:54) trapsize 2005 -\i (00:26:55) zoom out 1 -\i (00:26:55) setwindow pcb -\i (00:26:55) zoom out 17.8489 90.8962 -\i (00:26:55) trapsize 4009 -\i (00:26:55) zoom in 1 -\i (00:26:55) setwindow pcb -\i (00:26:55) zoom in 15.8442 91.6981 -\i (00:26:55) trapsize 2005 -\i (00:26:56) zoom in 1 -\i (00:26:56) setwindow pcb -\i (00:26:56) zoom in 15.8443 91.6981 -\i (00:26:56) trapsize 1002 -\i (00:28:55) zoom out 1 -\i (00:28:55) setwindow pcb -\i (00:28:55) zoom out 24.3237 90.7159 -\i (00:28:55) trapsize 2005 -\i (00:28:55) zoom in 1 -\i (00:28:55) setwindow pcb -\i (00:28:55) zoom in 14.4612 92.3997 -\i (00:28:55) trapsize 1002 -\i (03:15:24) xrefdes K1 -\i (03:15:24) xname_flush -\i (03:15:24) trapsize 4733 -\i (03:15:26) xrefdes K3 -\i (03:15:26) xname_flush -\i (03:15:26) trapsize 4733 -\i (03:15:28) xrefdes K1 -\i (03:15:28) xname_flush -\i (03:15:28) trapsize 4733 -\i (03:15:56) xrefdes U21 -\i (03:15:56) xname_flush -\i (03:15:56) trapsize 1890 -\i (03:16:30) xNet Vbus+ -\i (03:16:30) xname_flush -\i (03:16:30) trapsize 7236 -\i (03:16:34) xNet Vbus+_Sw -\i (03:16:34) xname_flush -\i (03:16:34) trapsize 2674 -\i (03:16:38) xrefdes U5 -\i (03:16:38) xname_flush -\i (03:16:38) trapsize 2201 -\i (04:19:50) zoom out 1 -\i (04:19:50) setwindow pcb -\i (04:19:50) zoom out 28.4704 33.3770 -\i (04:19:50) trapsize 4401 -\i (04:19:50) zoom out 1 -\i (04:19:50) setwindow pcb -\i (04:19:50) zoom out 28.4704 33.3770 -\i (04:19:50) trapsize 8803 -\i (04:20:05) zoom in 1 -\i (04:20:05) setwindow pcb -\i (04:20:05) zoom in 67.9549 43.7641 -\i (04:20:05) trapsize 4401 -\i (04:20:07) zoom in 1 -\i (04:20:07) setwindow pcb -\i (04:20:07) zoom in 45.7722 39.8910 -\i (04:20:07) trapsize 2201 -\i (04:20:17) zoom out 1 -\i (04:20:17) setwindow pcb -\i (04:20:17) zoom out 51.8021 36.7661 -\i (04:20:17) trapsize 4401 -\i (04:20:18) zoom out 1 -\i (04:20:18) setwindow pcb -\i (04:20:18) zoom out 37.8939 32.3647 -\i (04:20:18) trapsize 8803 -\i (04:20:19) zoom out 1 -\i (04:20:19) setwindow pcb -\i (04:20:19) zoom out 13.0703 40.4631 -\i (04:20:19) trapsize 17605 -\i (04:20:20) zoom in 1 -\i (04:20:20) setwindow pcb -\i (04:20:20) zoom in 16.1952 5.2524 -\i (04:20:20) trapsize 8803 -\i (04:20:20) zoom in 1 -\i (04:20:20) setwindow pcb -\i (04:20:20) zoom in 15.4910 4.9004 -\i (04:20:20) trapsize 4401 -\i (04:20:22) zoom in 1 -\i (04:20:22) setwindow pcb -\i (04:20:22) zoom in 33.5365 21.7135 -\i (04:20:22) trapsize 2201 -\i (04:20:22) zoom in 1 -\i (04:20:22) setwindow pcb -\i (04:20:22) zoom in 34.5488 22.3737 -\i (04:20:22) trapsize 1100 -\i (04:20:22) zoom in 1 -\i (04:20:22) setwindow pcb -\i (04:20:22) zoom in 34.5488 22.3737 -\i (04:20:22) trapsize 550 -\i (04:20:23) zoom in 1 -\i (04:20:23) setwindow pcb -\i (04:20:23) zoom in 33.8446 23.6061 -\i (04:20:23) trapsize 275 -\i (04:20:23) zoom in 1 -\i (04:20:23) setwindow pcb -\i (04:20:23) zoom in 33.1183 23.8152 -\i (04:20:23) trapsize 138 -\i (04:20:23) zoom out 1 -\i (04:20:23) setwindow pcb -\i (04:20:23) zoom out 33.3383 23.8345 -\i (04:20:23) trapsize 275 -\i (04:20:23) zoom out 1 -\i (04:20:23) setwindow pcb -\i (04:20:23) zoom out 33.3438 23.7850 -\i (04:20:23) trapsize 550 -\i (04:20:33) zoom out 1 -\i (04:20:33) setwindow pcb -\i (04:20:33) zoom out 34.9944 23.6969 -\i (04:20:33) trapsize 1100 -\i (04:20:33) zoom out 1 -\i (04:20:33) setwindow pcb -\i (04:20:33) zoom out 35.2585 23.6970 -\i (04:20:33) trapsize 2201 -\i (04:20:34) zoom out 1 -\i (04:20:34) setwindow pcb -\i (04:20:34) zoom out 35.0825 22.9047 -\i (04:20:34) trapsize 4402 -\i (04:20:34) zoom out 1 -\i (04:20:34) setwindow pcb -\i (04:20:34) zoom out 35.0824 22.9047 -\i (04:20:34) trapsize 8803 -\i (04:20:35) zoom in 1 -\i (04:20:35) setwindow pcb -\i (04:20:35) zoom in 33.6739 48.2577 -\i (04:20:35) trapsize 4402 -\i (04:20:35) zoom in 1 -\i (04:20:35) setwindow pcb -\i (04:20:35) zoom in 36.9311 22.7287 -\i (04:20:35) trapsize 2201 -\i (04:20:35) zoom in 1 -\i (04:20:35) setwindow pcb -\i (04:20:35) zoom in 36.1389 22.1125 -\i (04:20:35) trapsize 1100 -\i (04:20:36) zoom in 1 -\i (04:20:36) setwindow pcb -\i (04:20:36) zoom in 31.9134 24.1592 -\i (04:20:36) trapsize 550 -\i (04:20:36) zoom in 1 -\i (04:20:36) setwindow pcb -\i (04:20:36) zoom in 31.9134 24.1592 -\i (04:20:36) trapsize 275 -\i (04:20:37) zoom out 1 -\i (04:20:37) setwindow pcb -\i (04:20:37) zoom out 34.8459 23.5815 -\i (04:20:37) trapsize 550 -\i (04:20:38) zoom in 1 -\i (04:20:38) setwindow pcb -\i (04:20:38) zoom in 36.3204 23.2514 -\i (04:20:38) trapsize 275 -\i (04:20:40) zoom out 1 -\i (04:20:40) setwindow pcb -\i (04:20:40) zoom out 35.9188 23.9722 -\i (04:20:40) trapsize 550 -\i (04:20:41) zoom out 1 -\i (04:20:41) setwindow pcb -\i (04:20:41) zoom out 37.6905 23.9502 -\i (04:20:41) trapsize 1100 -\i (04:20:41) zoom in 1 -\i (04:20:41) setwindow pcb -\i (04:20:41) zoom in 39.2309 23.4440 -\i (04:20:41) trapsize 550 -\i (04:20:42) zoom in 1 -\i (04:20:42) setwindow pcb -\i (04:20:42) zoom in 38.5377 23.6861 -\i (04:20:42) trapsize 275 -\i (04:20:42) zoom in 1 -\i (04:20:42) setwindow pcb -\i (04:20:42) zoom in 38.5377 23.6861 -\i (04:20:42) trapsize 138 -\i (04:20:43) zoom out 1 -\i (04:20:43) setwindow pcb -\i (04:20:43) zoom out 38.2736 23.7027 -\i (04:20:43) trapsize 275 -\i (04:20:45) zoom out 1 -\i (04:20:45) setwindow pcb -\i (04:20:45) zoom out 35.2366 23.8787 -\i (04:20:45) trapsize 550 -\i (04:20:46) zoom out 1 -\i (04:20:46) setwindow pcb -\i (04:20:46) zoom out 36.1169 24.6599 -\i (04:20:46) trapsize 1100 -\i (04:20:46) zoom out 1 -\i (04:20:46) setwindow pcb -\i (04:20:46) zoom out 36.1169 24.5499 -\i (04:20:46) trapsize 2201 -\i (04:20:46) zoom out 1 -\i (04:20:46) setwindow pcb -\i (04:20:46) zoom out 36.6011 24.6819 -\i (04:20:46) trapsize 4402 -\i (04:20:47) zoom out 1 -\i (04:20:47) setwindow pcb -\i (04:20:47) zoom out 35.1925 31.9005 -\i (04:20:47) trapsize 8803 -\i (04:20:47) zoom in 1 -\i (04:20:47) setwindow pcb -\i (04:20:47) zoom in 32.9036 29.6117 -\i (04:20:47) trapsize 4402 -\i (04:20:47) zoom out 1 -\i (04:20:47) setwindow pcb -\i (04:20:47) zoom out 32.7276 30.4920 -\i (04:20:47) trapsize 8803 -\i (04:20:47) zoom out 1 -\i (04:20:47) setwindow pcb -\i (04:20:47) zoom out 32.5515 30.4920 -\i (04:20:47) trapsize 17606 -\i (04:20:48) zoom in 1 -\i (04:20:48) setwindow pcb -\i (04:20:48) zoom in 18.3135 52.8216 -\i (04:20:48) trapsize 8803 -\i (04:20:48) zoom in 1 -\i (04:20:48) setwindow pcb -\i (04:20:48) zoom in 18.3135 52.8216 -\i (04:20:48) trapsize 4402 -\i (04:20:49) zoom in 1 -\i (04:20:49) setwindow pcb -\i (04:20:49) zoom in 34.3352 20.6903 -\i (04:20:49) trapsize 2201 -\i (04:20:50) zoom in 1 -\i (04:20:50) setwindow pcb -\i (04:20:50) zoom in 32.7506 19.7220 -\i (04:20:50) trapsize 1100 -\i (04:20:50) zoom in 1 -\i (04:20:50) setwindow pcb -\i (04:20:50) zoom in 33.0587 21.2626 -\i (04:20:50) trapsize 550 -\i (04:20:50) zoom in 1 -\i (04:20:50) setwindow pcb -\i (04:20:50) zoom in 33.0587 21.2626 -\i (04:20:50) trapsize 275 -\i (04:20:51) zoom out 1 -\i (04:20:51) setwindow pcb -\i (04:20:51) zoom out 33.0587 23.3203 -\i (04:20:51) trapsize 550 -\i (04:20:55) zoom in 1 -\i (04:20:55) setwindow pcb -\i (04:20:55) zoom in 34.3352 23.7385 -\i (04:20:55) trapsize 275 -\i (04:20:56) drag_start grid 34.3023 23.7275 -\i (04:20:56) zoom in 1 -\i (04:20:56) setwindow pcb -\i (04:20:56) zoom in 34.3408 23.0673 -\i (04:20:56) trapsize 138 -\i (04:20:56) drag_stop 34.3573 22.9353 -\i (04:20:57) zoom out 1 -\i (04:20:57) setwindow pcb -\i (04:20:57) zoom out 34.3436 22.9793 -\i (04:20:57) trapsize 275 -\i (04:20:57) zoom out 1 -\i (04:20:57) setwindow pcb -\i (04:20:57) zoom out 34.3436 22.9793 -\i (04:20:57) trapsize 550 -\i (04:20:57) zoom out 1 -\i (04:20:57) setwindow pcb -\i (04:20:57) zoom out 34.3545 22.9353 -\i (04:20:57) trapsize 1100 -\i (04:20:57) zoom in 1 -\i (04:20:57) setwindow pcb -\i (04:20:57) zoom in 33.4742 26.5226 -\i (04:20:57) trapsize 550 -\i (04:20:58) zoom in 1 -\i (04:20:58) setwindow pcb -\i (04:20:58) zoom in 34.8717 23.7717 -\i (04:20:58) trapsize 275 -\i (04:21:36) help -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 36.1042 24.5970 -\i (04:22:22) trapsize 550 -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 36.1041 24.5090 -\i (04:22:22) trapsize 1100 -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 36.1701 24.3990 -\i (04:22:22) trapsize 2201 -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 37.1825 23.6948 -\i (04:22:22) trapsize 4402 -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 46.2497 31.2655 -\i (04:22:22) trapsize 8803 -\i (04:22:22) zoom out 1 -\i (04:22:22) setwindow pcb -\i (04:22:22) zoom out 85.7451 31.2656 -\i (04:22:22) trapsize 17606 -\i (04:22:23) zoom in 1 -\i (04:22:23) setwindow pcb -\i (04:22:23) zoom in 13.7359 82.0478 -\i (04:22:23) trapsize 8803 -\i (04:22:26) zoom in 1 -\i (04:22:26) setwindow pcb -\i (04:22:26) zoom in 33.2788 57.5752 -\i (04:22:26) trapsize 4402 -\i (04:22:26) zoom in 1 -\i (04:22:26) setwindow pcb -\i (04:22:26) zoom in 33.2788 57.5753 -\i (04:22:26) trapsize 2201 -\i (04:22:27) zoom out 1 -\i (04:22:27) setwindow pcb -\i (04:22:27) zoom out 36.7560 59.1599 -\i (04:22:27) trapsize 4402 -\i (04:22:27) zoom out 1 -\i (04:22:27) setwindow pcb -\i (04:22:27) zoom out 36.7559 59.1599 -\i (04:22:27) trapsize 8803 -\i (04:22:27) zoom in 1 -\i (04:22:27) setwindow pcb -\i (04:22:27) zoom in 2.7760 75.0054 -\i (04:22:27) trapsize 4402 -\i (04:22:32) zoom out 1 -\i (04:22:32) setwindow pcb -\i (04:22:32) zoom out 69.6795 77.9985 -\i (04:22:32) trapsize 8803 -\i (04:22:34) zoom in 1 -\i (04:22:34) setwindow pcb -\i (04:22:34) zoom in 73.5968 80.6394 -\i (04:22:34) trapsize 4402 -\i (04:22:34) zoom in 1 -\i (04:22:34) setwindow pcb -\i (04:22:34) zoom in 73.5968 80.6395 -\i (04:22:34) trapsize 2201 -\i (04:22:34) zoom in 1 -\i (04:22:34) setwindow pcb -\i (04:22:34) zoom in 71.6601 81.1677 -\i (04:22:34) trapsize 1100 -\i (04:22:35) zoom in 1 -\i (04:22:35) setwindow pcb -\i (04:22:35) zoom in 72.6285 80.9257 -\i (04:22:35) trapsize 550 -\i (04:22:35) zoom in 1 -\i (04:22:35) setwindow pcb -\i (04:22:35) zoom in 72.6285 80.9257 -\i (04:22:35) trapsize 275 -\i (04:23:52) zoom out 1 -\i (04:23:52) setwindow pcb -\i (04:23:52) zoom out 70.3892 79.9464 -\i (04:23:52) trapsize 550 -\i (04:23:55) zoom in 1 -\i (04:23:55) setwindow pcb -\i (04:23:55) zoom in 66.5489 80.1885 -\i (04:23:55) trapsize 275 -\i (04:23:55) zoom in 1 -\i (04:23:55) setwindow pcb -\i (04:23:55) zoom in 66.0538 80.2106 -\i (04:23:55) trapsize 138 -\i (04:23:55) zoom in 1 -\i (04:23:55) setwindow pcb -\i (04:23:55) zoom in 66.0538 80.2106 -\i (04:23:55) trapsize 69 -\i (04:23:55) zoom out 1 -\i (04:23:55) setwindow pcb -\i (04:23:55) zoom out 66.1597 80.2492 -\i (04:23:55) trapsize 138 -\i (04:23:55) zoom out 1 -\i (04:23:55) setwindow pcb -\i (04:23:55) zoom out 66.1597 80.2492 -\i (04:23:55) trapsize 275 -\i (04:23:56) zoom out 1 -\i (04:23:56) setwindow pcb -\i (04:23:56) zoom out 66.5283 80.3812 -\i (04:23:56) trapsize 550 -\i (04:23:58) zoom in 1 -\i (04:23:58) setwindow pcb -\i (04:23:58) zoom in 71.8655 80.6564 -\i (04:23:58) trapsize 275 -\i (04:23:59) zoom out 1 -\i (04:23:59) setwindow pcb -\i (04:23:59) zoom out 71.7500 80.5023 -\i (04:23:59) trapsize 550 -\i (04:28:30) zoom out 1 -\i (04:28:30) setwindow pcb -\i (04:28:30) zoom out 73.0154 79.4459 -\i (04:28:30) trapsize 1100 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 72.3551 79.1158 -\i (04:28:31) trapsize 2201 -\i (04:28:31) zoom in 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom in 70.6824 76.9588 -\i (04:28:31) trapsize 1100 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 70.0882 77.3990 -\i (04:28:31) trapsize 2201 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 69.7801 77.3990 -\i (04:28:31) trapsize 4402 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 55.2541 77.8392 -\i (04:28:31) trapsize 8804 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 54.1977 69.5637 -\i (04:28:31) trapsize 17607 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 108.1170 57.9431 -\i (04:28:31) trapsize 35214 -\i (04:28:31) zoom out 1 -\i (04:28:31) setwindow pcb -\i (04:28:31) zoom out 319.7555 52.1262 -\i (04:28:31) trapsize 70429 -\i (04:28:46) xdehilite -\i (04:28:46) xrefdes U5 -\i (04:28:46) xname_flush -\i (04:28:46) done -\i (04:28:46) generaledit -\i (04:29:34) xNet Pb10_Usart3_Tx -\i (04:29:34) xname_flush -\i (04:29:34) trapsize 710 -\i (04:39:25) xNet Pb9 -\i (04:39:25) xname_flush -\i (04:39:25) trapsize 580 -\i (04:42:22) xNet Pb10_Usart3_Tx -\i (04:42:22) xname_flush -\i (04:42:22) trapsize 710 -\i (04:42:36) xNet N3579505 -\i (04:42:36) xname_flush -\i (04:42:36) trapsize 137 -\i (04:43:09) xNet N3579545 -\i (04:43:09) xname_flush -\i (04:43:09) trapsize 290 -\i (04:43:17) xNet N3579545 -\i (04:43:17) xname_flush -\i (04:43:17) trapsize 290 -\i (04:43:23) xNet Pa9_Usart1_Tx -\i (04:43:23) xname_flush -\i (04:43:23) trapsize 2757 -\i (06:32:33) exit -\e (06:32:33) Do you want to save the changes you made to HC_DFCD_Protocol_V3_0.brd? -\i (06:32:34) fillin yes -\t (06:32:34) Journal end - Wed Aug 26 17:53:03 2026 +\i (00:00:21) zoom out 58.1402 66.3021 +\i (00:00:21) trapsize 5515 +\i (00:10:52) exit +\t (00:10:53) Journal end - Fri Sep 11 15:47:54 2026