wrh
1fe2ca7658
1. apps/chrg/applications/utils/chrg_sink.c：更新初始化流程注释，调整状态判断条件，避免初始化批次被永久跳过 2. apps/chrg/applications/thread/chrg_comm.c：新增备份并恢复测试相关状态变量的逻辑，修复参数同步时状态丢失问题 3. docs/Allegro.jrl、docs/allegro.jrl,1：更新Cadence Allegro操作日志文件内容
16 lines
774 B
Plaintext
16 lines
774 B
Plaintext
\t (00:00:05) allegro 17.2 S079 Windows SPB 64-bit Edition
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\t (00:00:05) Journal start - Wed Sep 16 22:17:09 2026
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\t (00:00:05) Host=DESKTOP-5RA9F3K User=Adminuser Pid=19892 CPUs=20
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\t (00:00:05) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe
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\t (00:00:05)
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(00:00:05) Loading axlcore.cxt
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\t (00:00:06) Starting new design...
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\i (00:00:06) trapsize 29310
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\i (00:00:07) generaledit
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\i (00:00:08) trapsize 1230
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\i (00:00:08) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed
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\i (00:00:08) opencd D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/south/HC_DFCD_Source_Eload_V1_1/PCB/HC_DFCD_Source_Eload_V1_1.brd
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\t (00:00:08) Opening existing design...
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\i (00:00:08) trapsize 283
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\t (00:00:08) Journal end - Wed Sep 16 22:17:12 2026
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