wrh
1fe2ca7658
1. apps/chrg/applications/utils/chrg_sink.c：更新初始化流程注释，调整状态判断条件，避免初始化批次被永久跳过 2. apps/chrg/applications/thread/chrg_comm.c：新增备份并恢复测试相关状态变量的逻辑，修复参数同步时状态丢失问题 3. docs/Allegro.jrl、docs/allegro.jrl,1：更新Cadence Allegro操作日志文件内容
56 lines
2.0 KiB
Plaintext
56 lines
2.0 KiB
Plaintext
\t (00:00:06) allegro 17.2 S079 Windows SPB 64-bit Edition
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\t (00:00:06) Journal start - Tue Sep 15 20:16:48 2026
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\t (00:00:06) Host=DESKTOP-5RA9F3K User=Adminuser Pid=8232 CPUs=20
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\t (00:00:06) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe
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\t (00:00:06)
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(00:00:06) Loading axlcore.cxt
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\t (00:00:07) Starting new design...
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\i (00:00:09) trapsize 29310
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\i (00:00:10) generaledit
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\i (00:00:18) xhilite
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\i (00:00:18) xname_flush
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\i (00:00:18) done
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\i (00:00:19) generaledit
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\i (00:00:33) xhilite
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\i (00:00:34) xname_flush
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\i (00:00:34) done
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\i (00:00:34) generaledit
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\i (00:20:00) exit
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\e (00:20:00) Do you want to save the changes you made to unnamed.brd?
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\i (12:51:55) fillin no
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\t (12:51:56) Journal end - Wed Sep 16 09:08:37 2026
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\i (00:00:13) generaledit
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\i (00:00:14) zoom out 1
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\i (00:00:14) setwindow pcb
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\i (00:00:14) zoom out 17.5318 56.5185
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\i (00:00:14) trapsize 5515
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\i (00:00:14) zoom out 1
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\i (00:00:14) setwindow pcb
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\i (00:00:14) zoom out 21.9438 59.0553
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\i (00:00:14) trapsize 11030
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\i (00:00:14) zoom out 1
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\i (00:00:14) setwindow pcb
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\i (00:00:14) zoom out 64.3442 57.9524
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\i (00:00:14) trapsize 22060
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\i (00:00:17) open
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\i (00:00:20) fillin "menu_cancel"
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\i (00:00:20) generaledit
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\i (00:00:20) zoom in 1
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\i (00:00:20) setwindow pcb
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\i (00:00:20) zoom in 19.5632 59.7117
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\i (00:00:20) trapsize 11030
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\i (00:00:20) zoom in 1
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\i (00:00:20) setwindow pcb
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\i (00:00:20) zoom in 11.6217 57.0646
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\i (00:00:20) trapsize 5515
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\i (00:00:22) open
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\i (00:00:26) fillin "menu_cancel"
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\i (00:00:26) generaledit
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\i (00:00:26) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "Start Page"
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\i (00:00:28) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged HC_DFCD_Protocol_V3_0
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\i (00:00:28) opencd D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/south/HC_DFCD_Source_Eload_V1_1/PCB/HC_DFCD_Source_Eload_V1_1.brd
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\t (00:00:28) Opening existing design...
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\i (00:00:29) trapsize 283
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\t (00:00:29) Journal end - Tue Sep 15 20:17:15 2026
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