wrh
9254c82547
- 删除chrg_comm.h和chrg_def.h中的旧YMODEM状态枚举及注释代码 - 删除chrg_comm.c中已废弃的旧YMODEM重发和会话管理代码 - 更新协议板版本寄存器编码为十进制143 - 新增chrg_ymodem_proxy模块的详细中文注释，明确升级代理职责 - 更新changelog记录V1.1.43版本变更 - 删除无用的Allegro日志文件，优化PCB设计相关文档 本次提交将YMODEM升级功能重构为独立代理模块，不再依赖旧版自动重发逻辑，提升升级流程的可维护性和可靠性。
79 lines
2.8 KiB
Plaintext
79 lines
2.8 KiB
Plaintext
\t (00:00:05) Allegro 17.2 S079 Windows SPB 64-bit Edition
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\t (00:00:05) Journal start - Mon Sep 28 10:42:59 2026
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\t (00:00:05) Host=DESKTOP-5RA9F3K User=Adminuser Pid=31016 CPUs=20
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\t (00:00:05) CmdLine= D:\Cadence\SPB_17.2\tools\bin\Allegro.exe D:\HC-PMP-SW\Power_ControlPannel\MP_Control_sw_405\MP_SW_Chrg\chrg\docs\HC_DFCD_Protocol_V3_0.brd
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\t (00:00:05)
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(00:00:05) Loading axlcore.cxt
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\t (00:00:06) Opening existing design...
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\i (00:00:06) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged HC_DFCD_Protocol_V3_0
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\d (00:00:06) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd
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\i (00:00:08) trapsize 3087
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\i (00:00:08) trapsize 3181
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\i (00:00:08) trapsize 3224
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\i (00:00:09) trapsize 2757
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\i (00:00:09) trapsize 2757
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\i (00:00:10) generaledit
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\i (00:00:13) xhilite
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\i (00:00:13) xname_flush
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\i (00:00:13) done
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\i (00:00:13) generaledit
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\i (00:01:43) xhilite
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\i (00:01:43) xname_flush
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\i (00:01:43) done
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\i (00:01:43) generaledit
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\i (00:01:46) exit
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\e (00:01:46) Do you want to save the changes you made to HC_DFCD_Protocol_V3_0.brd?
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\i (00:01:46) fillin no
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\t (00:01:47) Journal end - Mon Sep 28 10:44:41 2026
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i (00:01:38) trapsize 1379
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\i (00:01:38) zoom in 1
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\i (00:01:38) setwindow pcb
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\i (00:01:38) zoom in -9.3258 62.5298
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\i (00:01:38) trapsize 689
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\i (00:01:38) zoom in 1
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\i (00:01:38) setwindow pcb
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\i (00:01:38) zoom in -9.3258 62.5298
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\i (00:01:38) trapsize 345
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\i (00:01:38) zoom in 1
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\i (00:01:38) setwindow pcb
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\i (00:01:38) zoom in -9.3258 62.5298
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\i (00:01:38) trapsize 172
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\i (00:01:38) zoom out 1
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\i (00:01:38) setwindow pcb
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\i (00:01:38) zoom out -8.5709 62.0783
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\i (00:01:38) trapsize 345
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\i (00:01:38) zoom out 1
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\i (00:01:38) setwindow pcb
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\i (00:01:38) zoom out -8.5916 62.0782
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\i (00:01:38) trapsize 689
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\i (00:01:38) zoom out 1
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\i (00:01:38) setwindow pcb
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\i (00:01:38) zoom out -8.6055 62.0645
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\i (00:01:38) trapsize 1379
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\i (00:01:38) zoom out 1
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\i (00:01:38) setwindow pcb
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\i (00:01:38) zoom out -8.6055 62.0645
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\i (00:01:38) trapsize 2757
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\i (00:01:39) zoom out 1
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\i (00:01:39) setwindow pcb
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\i (00:01:39) zoom out -8.2746 62.0646
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\i (00:01:39) trapsize 5515
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\i (00:01:39) zoom out 1
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\i (00:01:39) setwindow pcb
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\i (00:01:39) zoom out -8.2745 62.0645
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\i (00:01:39) trapsize 11030
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\i (00:01:39) zoom out 1
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\i (00:01:39) setwindow pcb
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\i (00:01:39) zoom out -2.9386 62.0645
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\i (00:01:39) trapsize 22059
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\i (00:01:39) zoom out 1
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\i (00:01:39) setwindow pcb
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\i (00:01:39) zoom out 94.1228 62.0646
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\i (00:01:39) trapsize 44119
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\i (00:01:41) pick grid 679.1382 312.9521
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\t (00:01:41) last pick: 679.1400 312.9500
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\i (00:01:42) exit
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\e (00:01:42) Do you want to save the changes you made to HC_DFCD_Protocol_V3_0.brd?
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\i (00:01:43) fillin no
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\t (00:01:43) Journal end - Mon Sep 28 10:44:38 2026
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