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fix: 修复初始化批次状态被去重跳过的问题

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1.  apps/chrg/applications/utils/chrg_sink.c：更新初始化流程注释，调整状态判断条件，避免初始化批次被永久跳过
2.  apps/chrg/applications/thread/chrg_comm.c：新增备份并恢复测试相关状态变量的逻辑，修复参数同步时状态丢失问题
3.  docs/Allegro.jrl、docs/allegro.jrl,1：更新Cadence Allegro操作日志文件内容
This commit is contained in:
wrh
2026-09-17 12:09:18 +08:00
parent b58b47f64a
commit 1fe2ca7658
3 changed files with 66 additions and 151 deletions
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docs/Allegro.jrl
+15 -55
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@@ -1,55 +1,15 @@
\t (00:00:06) allegro 17.2 S079 Windows SPB 64-bit Edition
\t (00:00:06) Journal start - Tue Sep 15 20:16:48 2026
\t (00:00:06) Host=DESKTOP-5RA9F3K User=Adminuser Pid=8232 CPUs=20
\t (00:00:06) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe
\t (00:00:06)
(00:00:06) Loading axlcore.cxt
\t (00:00:07) Starting new design...
\i (00:00:09) trapsize 29310
\i (00:00:10) generaledit
\i (00:00:18) xhilite
\i (00:00:18) xname_flush
\i (00:00:18) done
\i (00:00:19) generaledit
\i (00:00:33) xhilite
\i (00:00:34) xname_flush
\i (00:00:34) done
\i (00:00:34) generaledit
\i (00:20:00) exit
\e (00:20:00) Do you want to save the changes you made to unnamed.brd?
\i (12:51:55) fillin no
\t (12:51:56) Journal end - Wed Sep 16 09:08:37 2026
\i (00:00:13) generaledit
\i (00:00:14) zoom out 1
\i (00:00:14) setwindow pcb
\i (00:00:14) zoom out 17.5318 56.5185
\i (00:00:14) trapsize 5515
\i (00:00:14) zoom out 1
\i (00:00:14) setwindow pcb
\i (00:00:14) zoom out 21.9438 59.0553
\i (00:00:14) trapsize 11030
\i (00:00:14) zoom out 1
\i (00:00:14) setwindow pcb
\i (00:00:14) zoom out 64.3442 57.9524
\i (00:00:14) trapsize 22060
\i (00:00:17) open
\i (00:00:20) fillin "menu_cancel"
\i (00:00:20) generaledit
\i (00:00:20) zoom in 1
\i (00:00:20) setwindow pcb
\i (00:00:20) zoom in 19.5632 59.7117
\i (00:00:20) trapsize 11030
\i (00:00:20) zoom in 1
\i (00:00:20) setwindow pcb
\i (00:00:20) zoom in 11.6217 57.0646
\i (00:00:20) trapsize 5515
\i (00:00:22) open
\i (00:00:26) fillin "menu_cancel"
\i (00:00:26) generaledit
\i (00:00:26) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "Start Page"
\i (00:00:28) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged HC_DFCD_Protocol_V3_0
\i (00:00:28) opencd D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/south/HC_DFCD_Source_Eload_V1_1/PCB/HC_DFCD_Source_Eload_V1_1.brd
\t (00:00:28) Opening existing design...
\i (00:00:29) trapsize 283
\t (00:00:29) Journal end - Tue Sep 15 20:17:15 2026
\t (00:00:05) allegro 17.2 S079 Windows SPB 64-bit Edition
\t (00:00:05) Journal start - Wed Sep 16 22:17:09 2026
\t (00:00:05) Host=DESKTOP-5RA9F3K User=Adminuser Pid=19892 CPUs=20
\t (00:00:05) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe
\t (00:00:05)
(00:00:05) Loading axlcore.cxt
\t (00:00:06) Starting new design...
\i (00:00:06) trapsize 29310
\i (00:00:07) generaledit
\i (00:00:08) trapsize 1230
\i (00:00:08) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed
\i (00:00:08) opencd D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/south/HC_DFCD_Source_Eload_V1_1/PCB/HC_DFCD_Source_Eload_V1_1.brd
\t (00:00:08) Opening existing design...
\i (00:00:08) trapsize 283
\t (00:00:08) Journal end - Wed Sep 16 22:17:12 2026