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当前版本存在偶然性失败——电压到了之后没电流

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1.  apps/chrg/applications/thread/chrg_north.h: 更新版本号到V1.1.22
2.  apps/chrg/applications/utils/chrg_eload.c: 清理冗余注释和调试打印代码
3.  apps/chrg/applications/thread/chrg_comm.c: 更新版本号到V1.1.24，重构测试模式切换逻辑，新增优先级命令处理
4.  apps/chrg/applications/thread/chrg_roll_sou.c: 新增优先级命令调度逻辑，优先处理测试停止/切换命令
5.  apps/chrg/applications/utils/chrg_sink.c: 更新版本号到V1.1.24，重构初始化命令构建流程，新增初始化状态跟踪，增加调试打印开关
6.  docs/Allegro.jrl和docs/allegro.jrl,1: 更新Allegro设计日志文件
This commit is contained in:
wrh
2026-09-15 20:51:50 +08:00
parent 05309dfb41
commit 8327cb3500
7 changed files with 286 additions and 1102 deletions
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docs/Allegro.jrl
+44 -100
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@@ -1,105 +1,49 @@
\t (00:00:06) allegro 17.2 S079 Windows SPB 64-bit Edition
\t (00:00:06) Journal start - Fri Sep 11 15:37:07 2026
\t (00:00:06) Host=DESKTOP-5RA9F3K User=Adminuser Pid=13160 CPUs=20
\t (00:00:06) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe
\t (00:00:06)
(00:00:06) Loading axlcore.cxt
\t (00:00:06) Starting new design...
\i (00:00:07) trapsize 29310
\i (00:00:08) generaledit
\i (00:00:11) open
\i (00:00:12) fillin "HC_DFCD_Protocol_V3_0.brd"
\i (00:00:12) trapsize 1230
\i (00:00:12) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed
\t (00:00:12) Opening existing design...
\i (00:00:12) trapsize 2757
\d (00:00:12) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd
\t (00:00:01) allegro 17.2 S079 Windows SPB 64-bit Edition
\t (00:00:01) Journal start - Tue Sep 15 20:16:48 2026
\t (00:00:01) Host=DESKTOP-5RA9F3K User=Adminuser Pid=20076 CPUs=20
\t (00:00:01) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe
\t (00:00:01)
(00:00:01) Loading axlcore.cxt
\t (00:00:02) Starting new design...
\i (00:00:04) trapsize 29310
\i (00:00:05) generaledit
\i (00:00:12) open
\i (00:00:13) fillin "HC_DFCD_Protocol_V3_0.brd"
\i (00:00:13) trapsize 1230
\i (00:00:13) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed
\t (00:00:13) Opening existing design...
\i (00:00:13) trapsize 2757
\d (00:00:13) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd
\i (00:00:13) generaledit
\i (00:00:13) zoom out 1
\i (00:00:13) setwindow pcb
\i (00:00:13) zoom out 27.8998 58.3935
\i (00:00:13) trapsize 5515
\i (00:00:13) zoom out 1
\i (00:00:13) setwindow pcb
\i (00:00:13) zoom out 27.7896 58.0627
\i (00:00:13) trapsize 11030
\i (00:00:13) zoom out 1
\i (00:00:13) setwindow pcb
\i (00:00:13) zoom out 96.9925 57.6215
\i (00:00:13) trapsize 22060
\i (00:00:13) zoom out 1
\i (00:00:13) setwindow pcb
\i (00:00:13) zoom out 299.2792 77.8006
\i (00:00:13) trapsize 44119
\i (00:00:13) zoom out 1
\i (00:00:13) setwindow pcb
\i (00:00:13) zoom out 710.9119 236.1887
\i (00:00:13) trapsize 88239
\i (00:00:13) zoom out 1
\i (00:00:13) setwindow pcb
\i (00:00:13) zoom out 1546.5306 547.6707
\i (00:00:13) trapsize 176477
\i (00:00:14) zoom in 1
\i (00:00:14) zoom out 1
\i (00:00:14) setwindow pcb
\i (00:00:14) zoom in 101.1838 -64.7046
\i (00:00:14) trapsize 88239
\i (00:00:14) zoom in 1
\i (00:00:14) setwindow pcb
\i (00:00:14) zoom in 99.4190 -62.9398
\i (00:00:14) trapsize 44119
\i (00:00:14) zoom in 1
\i (00:00:14) setwindow pcb
\i (00:00:14) zoom in 92.3600 -31.1739
\i (00:00:14) trapsize 22060
\i (00:00:14) zoom in 1
\i (00:00:14) setwindow pcb
\i (00:00:14) zoom in 92.3600 -30.7327
\i (00:00:14) trapsize 11030
\i (00:00:14) zoom in 1
\i (00:00:14) setwindow pcb
\i (00:00:14) zoom in 92.3600 -30.5121
\i (00:00:14) zoom out 17.5318 56.5185
\i (00:00:14) trapsize 5515
\i (00:00:15) drag_start grid 110.6695 -6.4671
\i (00:00:15) drag_stop 188.9811 -20.1441
\i (00:00:15) zoom out 1
\i (00:00:15) setwindow pcb
\i (00:00:15) zoom out 102.1765 2.3567
\i (00:00:15) trapsize 11030
\i (00:00:15) zoom out 1
\i (00:00:15) setwindow pcb
\i (00:00:15) zoom out 102.3972 1.6950
\i (00:00:15) trapsize 22060
\i (00:00:15) zoom out 1
\i (00:00:15) setwindow pcb
\i (00:00:15) zoom out 104.6031 47.3583
\i (00:00:15) trapsize 44119
\i (00:00:16) zoom in 1
\i (00:00:16) setwindow pcb
\i (00:00:16) zoom in -19.8131 37.6521
\i (00:00:16) trapsize 22060
\i (00:00:16) zoom in 1
\i (00:00:16) setwindow pcb
\i (00:00:16) zoom in -5.2538 42.5053
\i (00:00:16) trapsize 11030
\i (00:00:16) zoom in 1
\i (00:00:16) setwindow pcb
\i (00:00:16) zoom in -5.2537 42.7259
\i (00:00:16) trapsize 5515
\i (00:00:17) zoom in 1
\i (00:00:17) setwindow pcb
\i (00:00:17) zoom in 48.1306 62.4692
\i (00:00:17) trapsize 2757
\i (00:00:14) zoom out 1
\i (00:00:14) setwindow pcb
\i (00:00:14) zoom out 21.9438 59.0553
\i (00:00:14) trapsize 11030
\i (00:00:14) zoom out 1
\i (00:00:14) setwindow pcb
\i (00:00:14) zoom out 64.3442 57.9524
\i (00:00:14) trapsize 22060
\i (00:00:17) open
\i (00:00:20) fillin "menu_cancel"
\i (00:00:20) generaledit
\i (00:00:20) zoom in 1
\i (00:00:20) setwindow pcb
\i (00:00:20) zoom in 64.2893 72.1203
\i (00:00:20) trapsize 1379
\i (00:00:21) zoom out 1
\i (00:00:21) setwindow pcb
\i (00:00:21) zoom out 61.4492 70.2728
\i (00:00:21) trapsize 2757
\i (00:00:21) zoom out 1
\i (00:00:21) setwindow pcb
\i (00:00:21) zoom out 58.1402 66.3021
\i (00:00:21) trapsize 5515
\i (00:10:52) exit
\t (00:10:53) Journal end - Fri Sep 11 15:47:54 2026
\i (00:00:20) zoom in 19.5632 59.7117
\i (00:00:20) trapsize 11030
\i (00:00:20) zoom in 1
\i (00:00:20) setwindow pcb
\i (00:00:20) zoom in 11.6217 57.0646
\i (00:00:20) trapsize 5515
\i (00:00:22) open
\i (00:00:26) fillin "menu_cancel"
\i (00:00:26) generaledit
\i (00:00:26) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "Start Page"
\i (00:00:28) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged HC_DFCD_Protocol_V3_0
\i (00:00:28) opencd D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/south/HC_DFCD_Source_Eload_V1_1/PCB/HC_DFCD_Source_Eload_V1_1.brd
\t (00:00:28) Opening existing design...
\i (00:00:29) trapsize 283
\t (00:00:29) Journal end - Tue Sep 15 20:17:15 2026
docs/allegro.jrl,1
+101 -949
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