chore: 更新协议板版本、通信重试次数及宏定义

1. 修改apps/chrg/applications/thread/chrg_roll_sou.c：将通信最大尝试次数从3改为10
2. 修改apps/chrg/applications/thread/chrg_comm.c：更新协议板固件版本为0x0129(V1.1.25)
3. 修改apps/chrg/applications/utils/chrg_sink.c：替换初始化命令相关的硬编码宏为更语义化的常量
4. 更新docs/Allegro.jrl：更新Cadence Allegro操作日志记录

docs/Allegro.jrl

@@ -1,19 +1,25 @@
-\t (00:00:01) allegro 17.2 S079 Windows SPB 64-bit Edition
-\t (00:00:01)     Journal start - Tue Sep 15 20:16:48 2026
-\t (00:00:01)         Host=DESKTOP-5RA9F3K User=Adminuser Pid=20076 CPUs=20
-\t (00:00:01) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe
-\t (00:00:01) 
-   (00:00:01) Loading axlcore.cxt 
-\t (00:00:02) Starting new design...
-\i (00:00:04) trapsize 29310
-\i (00:00:05) generaledit 
-\i (00:00:12) open 
-\i (00:00:13) fillin "HC_DFCD_Protocol_V3_0.brd"
-\i (00:00:13) trapsize 1230
-\i (00:00:13) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed
-\t (00:00:13) Opening existing design...
-\i (00:00:13) trapsize 2757
-\d (00:00:13) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd
+\t (00:00:06) allegro 17.2 S079 Windows SPB 64-bit Edition
+\t (00:00:06)     Journal start - Tue Sep 15 20:16:48 2026
+\t (00:00:06)         Host=DESKTOP-5RA9F3K User=Adminuser Pid=8232 CPUs=20
+\t (00:00:06) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe
+\t (00:00:06) 
+   (00:00:06) Loading axlcore.cxt 
+\t (00:00:07) Starting new design...
+\i (00:00:09) trapsize 29310
+\i (00:00:10) generaledit 
+\i (00:00:18) xhilite 
+\i (00:00:18) xname_flush 
+\i (00:00:18) done 
+\i (00:00:19) generaledit 
+\i (00:00:33) xhilite 
+\i (00:00:34) xname_flush 
+\i (00:00:34) done 
+\i (00:00:34) generaledit 
+\i (00:20:00) exit 
+\e (00:20:00) Do you want to save the changes you made to unnamed.brd?
+\i (12:51:55) fillin no 
+\t (12:51:56)     Journal end - Wed Sep 16 09:08:37 2026
+
 \i (00:00:13) generaledit 
 \i (00:00:14) zoom out 1 
 \i (00:00:14) setwindow pcb