wrh
05309dfb41
二、修改了负载启动的顺序，先开启辅助继电器使地相通，再开启D+D-继电器 feat: 发布V1.1.23版本，优化负载初始化继电器时序 - 更新所有头文件版本号至V1.1.21~V1.1.23，协议板固件版本更新为0x0127 - 新增纹波滤波相关宏定义与函数，实现继电器闭合后纹波过滤 - 调整负载初始化流程：先下发辅助继电器，等待回码后延迟30ms再打开北向继电器 - 优化D+/D-寄存器上位机显示单位，适配0.001V解析格式 - 补充YMODEM升级文档说明，完善传输校验与重发规则 - 清理冗余调试打印与Allegro工程日志文件
106 lines
3.4 KiB
Plaintext
106 lines
3.4 KiB
Plaintext
\t (00:00:06) allegro 17.2 S079 Windows SPB 64-bit Edition
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\t (00:00:06) Journal start - Fri Sep 11 15:37:07 2026
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\t (00:00:06) Host=DESKTOP-5RA9F3K User=Adminuser Pid=13160 CPUs=20
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\t (00:00:06) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe
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\t (00:00:06)
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(00:00:06) Loading axlcore.cxt
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\t (00:00:06) Starting new design...
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\i (00:00:07) trapsize 29310
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\i (00:00:08) generaledit
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\i (00:00:11) open
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\i (00:00:12) fillin "HC_DFCD_Protocol_V3_0.brd"
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\i (00:00:12) trapsize 1230
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\i (00:00:12) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed
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\t (00:00:12) Opening existing design...
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\i (00:00:12) trapsize 2757
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\d (00:00:12) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd
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\i (00:00:13) generaledit
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\i (00:00:13) zoom out 1
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\i (00:00:13) setwindow pcb
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\i (00:00:13) zoom out 27.8998 58.3935
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\i (00:00:13) trapsize 5515
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\i (00:00:13) zoom out 1
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\i (00:00:13) setwindow pcb
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\i (00:00:13) zoom out 27.7896 58.0627
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\i (00:00:13) trapsize 11030
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\i (00:00:13) zoom out 1
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\i (00:00:13) setwindow pcb
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\i (00:00:13) zoom out 96.9925 57.6215
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\i (00:00:13) trapsize 22060
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\i (00:00:13) zoom out 1
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\i (00:00:13) setwindow pcb
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\i (00:00:13) zoom out 299.2792 77.8006
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\i (00:00:13) trapsize 44119
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\i (00:00:13) zoom out 1
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\i (00:00:13) setwindow pcb
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\i (00:00:13) zoom out 710.9119 236.1887
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\i (00:00:13) trapsize 88239
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\i (00:00:13) zoom out 1
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\i (00:00:13) setwindow pcb
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\i (00:00:13) zoom out 1546.5306 547.6707
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\i (00:00:13) trapsize 176477
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\i (00:00:14) zoom in 1
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\i (00:00:14) setwindow pcb
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\i (00:00:14) zoom in 101.1838 -64.7046
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\i (00:00:14) trapsize 88239
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\i (00:00:14) zoom in 1
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\i (00:00:14) setwindow pcb
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\i (00:00:14) zoom in 99.4190 -62.9398
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\i (00:00:14) trapsize 44119
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\i (00:00:14) zoom in 1
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\i (00:00:14) setwindow pcb
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\i (00:00:14) zoom in 92.3600 -31.1739
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\i (00:00:14) trapsize 22060
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\i (00:00:14) zoom in 1
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\i (00:00:14) setwindow pcb
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\i (00:00:14) zoom in 92.3600 -30.7327
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\i (00:00:14) trapsize 11030
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\i (00:00:14) zoom in 1
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\i (00:00:14) setwindow pcb
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\i (00:00:14) zoom in 92.3600 -30.5121
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\i (00:00:14) trapsize 5515
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\i (00:00:15) drag_start grid 110.6695 -6.4671
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\i (00:00:15) drag_stop 188.9811 -20.1441
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\i (00:00:15) zoom out 1
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\i (00:00:15) setwindow pcb
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\i (00:00:15) zoom out 102.1765 2.3567
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\i (00:00:15) trapsize 11030
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\i (00:00:15) zoom out 1
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\i (00:00:15) setwindow pcb
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\i (00:00:15) zoom out 102.3972 1.6950
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\i (00:00:15) trapsize 22060
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\i (00:00:15) zoom out 1
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\i (00:00:15) setwindow pcb
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\i (00:00:15) zoom out 104.6031 47.3583
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\i (00:00:15) trapsize 44119
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\i (00:00:16) zoom in 1
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\i (00:00:16) setwindow pcb
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\i (00:00:16) zoom in -19.8131 37.6521
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\i (00:00:16) trapsize 22060
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\i (00:00:16) zoom in 1
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\i (00:00:16) setwindow pcb
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\i (00:00:16) zoom in -5.2538 42.5053
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\i (00:00:16) trapsize 11030
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\i (00:00:16) zoom in 1
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\i (00:00:16) setwindow pcb
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\i (00:00:16) zoom in -5.2537 42.7259
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\i (00:00:16) trapsize 5515
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\i (00:00:17) zoom in 1
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\i (00:00:17) setwindow pcb
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\i (00:00:17) zoom in 48.1306 62.4692
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\i (00:00:17) trapsize 2757
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\i (00:00:20) zoom in 1
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\i (00:00:20) setwindow pcb
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\i (00:00:20) zoom in 64.2893 72.1203
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\i (00:00:20) trapsize 1379
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\i (00:00:21) zoom out 1
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\i (00:00:21) setwindow pcb
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\i (00:00:21) zoom out 61.4492 70.2728
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\i (00:00:21) trapsize 2757
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\i (00:00:21) zoom out 1
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\i (00:00:21) setwindow pcb
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\i (00:00:21) zoom out 58.1402 66.3021
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\i (00:00:21) trapsize 5515
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\i (00:10:52) exit
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\t (00:10:53) Journal end - Fri Sep 11 15:47:54 2026
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