wrh
4a79d9a4de
北向轮询无回码让行逻辑 当空载时电流显示为0 1. 修改chrg_comm.c：更新协议板固件版本为0x0133，新增Source初始化事务保护逻辑 2. 修改chrg_roll_nor.c：优化北向轮询机制，单次请求超时后直接切换通道 3. 修改chrg_eload.h/c：新增小电流归零阈值宏，实现功率板小电流采样归零处理 4. 更新chrg_def.h版本号为V1.1.35 5. 更新修改日志文档，补充V1.1.33~V1.1.35版本更新内容
16 lines
774 B
Plaintext
16 lines
774 B
Plaintext
\t (00:00:05) allegro 17.2 S079 Windows SPB 64-bit Edition
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\t (00:00:05) Journal start - Wed Sep 16 22:17:09 2026
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\t (00:00:05) Host=DESKTOP-5RA9F3K User=Adminuser Pid=19892 CPUs=20
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\t (00:00:05) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe
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\t (00:00:05)
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(00:00:05) Loading axlcore.cxt
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\t (00:00:06) Starting new design...
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\i (00:00:06) trapsize 29310
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\i (00:00:07) generaledit
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\i (00:00:08) trapsize 1230
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\i (00:00:08) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed
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\i (00:00:08) opencd D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/south/HC_DFCD_Source_Eload_V1_1/PCB/HC_DFCD_Source_Eload_V1_1.brd
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\t (00:00:08) Opening existing design...
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\i (00:00:08) trapsize 283
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\t (00:00:08) Journal end - Wed Sep 16 22:17:12 2026
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