wrh
8327cb3500
1. apps/chrg/applications/thread/chrg_north.h: 更新版本号到V1.1.22 2. apps/chrg/applications/utils/chrg_eload.c: 清理冗余注释和调试打印代码 3. apps/chrg/applications/thread/chrg_comm.c: 更新版本号到V1.1.24，重构测试模式切换逻辑，新增优先级命令处理 4. apps/chrg/applications/thread/chrg_roll_sou.c: 新增优先级命令调度逻辑，优先处理测试停止/切换命令 5. apps/chrg/applications/utils/chrg_sink.c: 更新版本号到V1.1.24，重构初始化命令构建流程，新增初始化状态跟踪，增加调试打印开关 6. docs/Allegro.jrl和docs/allegro.jrl,1: 更新Allegro设计日志文件
50 lines
2.0 KiB
Plaintext
50 lines
2.0 KiB
Plaintext
\t (00:00:01) allegro 17.2 S079 Windows SPB 64-bit Edition
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\t (00:00:01) Journal start - Tue Sep 15 20:16:48 2026
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\t (00:00:01) Host=DESKTOP-5RA9F3K User=Adminuser Pid=20076 CPUs=20
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\t (00:00:01) CmdLine= D:\Cadence\SPB_17.2\tools\bin\allegro.exe
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\t (00:00:01)
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(00:00:01) Loading axlcore.cxt
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\t (00:00:02) Starting new design...
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\i (00:00:04) trapsize 29310
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\i (00:00:05) generaledit
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\i (00:00:12) open
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\i (00:00:13) fillin "HC_DFCD_Protocol_V3_0.brd"
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\i (00:00:13) trapsize 1230
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\i (00:00:13) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged unnamed
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\t (00:00:13) Opening existing design...
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\i (00:00:13) trapsize 2757
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\d (00:00:13) Design opened: D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/MP_SW_Chrg/chrg/docs/HC_DFCD_Protocol_V3_0.brd
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\i (00:00:13) generaledit
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\i (00:00:14) zoom out 1
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\i (00:00:14) setwindow pcb
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\i (00:00:14) zoom out 17.5318 56.5185
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\i (00:00:14) trapsize 5515
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\i (00:00:14) zoom out 1
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\i (00:00:14) setwindow pcb
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\i (00:00:14) zoom out 21.9438 59.0553
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\i (00:00:14) trapsize 11030
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\i (00:00:14) zoom out 1
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\i (00:00:14) setwindow pcb
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\i (00:00:14) zoom out 64.3442 57.9524
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\i (00:00:14) trapsize 22060
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\i (00:00:17) open
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\i (00:00:20) fillin "menu_cancel"
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\i (00:00:20) generaledit
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\i (00:00:20) zoom in 1
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\i (00:00:20) setwindow pcb
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\i (00:00:20) zoom in 19.5632 59.7117
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\i (00:00:20) trapsize 11030
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\i (00:00:20) zoom in 1
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\i (00:00:20) setwindow pcb
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\i (00:00:20) zoom in 11.6217 57.0646
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\i (00:00:20) trapsize 5515
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\i (00:00:22) open
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\i (00:00:26) fillin "menu_cancel"
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\i (00:00:26) generaledit
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\i (00:00:26) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged "Start Page"
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\i (00:00:28) QtSignal SPBFoldDockArea FoldAreaTabWidget currentChanged HC_DFCD_Protocol_V3_0
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\i (00:00:28) opencd D:/HC-PMP-SW/Power_ControlPannel/MP_Control_sw_405/south/HC_DFCD_Source_Eload_V1_1/PCB/HC_DFCD_Source_Eload_V1_1.brd
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\t (00:00:28) Opening existing design...
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\i (00:00:29) trapsize 283
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\t (00:00:29) Journal end - Tue Sep 15 20:17:15 2026
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